JPH02270443A - Data transmission system - Google Patents

Abstract

PURPOSE:To attain the transmission of a data with various length and to attain efficient data transmission by adding an identification data only to the specific bit of the leading word data of a frame data and allowing a reception side to identify the specific bit of each word data. CONSTITUTION:An identification bit being the loading bit of each frame is used to take the synchronization of a frame and a leading bit (identification bit) of a 1st word is logic 1 and the leading bit (identification bit) of a 2nd word is logic 0. Thus, even when an error takes place on the way of transmis sion, it is possible to take synchronization of the succeeding frame. Even when one frame is 3 words or above, a leading bit (identification bit) of the 3rd and subsequent words is selected to be logic 0, the synchronization of the frame is taken.

Description

[Detailed Description of the Invention] Kousyodate! The present invention relates to a data transmission method that transmits one frame of data by transmitting word data of a predetermined bit length multiple times.

For example, in an image recording device such as a copying machine, a large number of optional devices (attached devices) such as a sorter and a document feeder are prepared for the main body of the copying machine. Select one and connect it to the copier.

In such a copying machine, various data such as control signals are transmitted from the host control device (hereinafter referred to as host CP LJ) of the copying machine to control the optional devices. Device control bag f
From f1 (hereinafter referred to as option CPU), data indicating the status of each option device, etc. is transmitted to the host CPU.

On the other hand, in conventional data transmission methods, data transmission in word data units consisting of a predetermined number of hits is repeated a predetermined number of times.
It was transmitting frame data such as fixed length commands.

When such a data transmission method is used in the copying machine system, the data to be transmitted is of a fixed length even though long data and short data are mixed in the system. In this case, all the data had to be transmitted in alignment with the longest data, resulting in very long data as a whole, resulting in poor data transmission efficiency.

OBJECTS OF THE INVENTION The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a data transmission system that allows data to be transmitted to be made variable and allows efficient data transmission.

Summary of the Invention According to the present invention, since data is transmitted with identification data attached only to specific bits of the first word data of frame data, on the receiving side, by identifying the specific bits of each word data, It is sufficient to recognize the data up to the reception of the next word data attached with identification data as frame data such as one command, and data of various lengths can be transmitted.

1 is a diagram showing an example of a copying machine to which the present invention is applied, in which 1 is a main body of the copying machine, 2 is a paper feeding device, 3 is a document conveyance device, and 4 is a sorter.

Next, lO is a host CPU, 11 is a master CPU for copy control of the copying machine main body l, 12 is a first option CPU for paper feed control, and 513 is a second option CPU for document transport control.
U, 14 is a third optional CPU for sorter control. Note that the mask CPU is also one of the optional CPUs.

Master CPU11 and each option CPUI2゜13.1
4, as shown in FIG. 2 or 3, is connected to the middle CPU 10 via a common data bus 20 for data communication.

In FIG. 3, 16A and 16I3 are addable option CPLIs capable of transmitting and receiving, and 17 and 18 are optional CPUs dedicated to reception such as display devices.

FIG. 4 is a block diagram of the CPU used in this embodiment.

Host CPU10. Optional CPU1l-14 (4th
It is indicated by 11 in the figure. ) is the control unit CC and RAM (rtA)
In addition to the input/output section I10, it has a timer T, a reception register RR for communication, and a transmission register SR. Timer T
generates a timer interrupt signal to the control unit CC at regular intervals.

In addition, the reception register RR is capable of asynchronous communication,
When data reception is completed, a reception interrupt signal is generated to the control unit CC. The transmission register is also capable of asynchronous communication, and when the transmission of data set by the control section is completed, it generates a transmission trimming signal to the control section.

The RAM (RA) also includes a register RMODE whose contents change according to a change in state during reception and a register TMODE whose contents change according to a change in state during transmission. The operations of both registers will be described later.

In Figure 2, H-DATA is the first common connection line for transmitting data from host CPU10 to option C)) Ull-14, and 0-DATA is conversely from option CPLII&-14 to host A second common connection line for transmitting data to cputo. Elx and EO are an input port and an output port of connection lines for controlling data transmission, and by cascading each input port and output port via the control connection line 21, all CPUs 10 to 14 are connected in a circular manner. Connect to.

Returning to FIG. 4 again, each CPU further includes a virtual common RAM (CRAM) that stores the same information. This virtual common RAM (CRAM) stores all information transmitted through communication. This information includes:
It includes the current status of the copying machine and the status of each cputo~i4, and each CPUl0~14 has its own virtual common FiLAM.
(By referring to CI (AM), it is possible to obtain information about the entire system. In this case, each CP
Information at the same address in U's virtual common RAM (ORAM) must always match each other;
This is done as follows.

In any CPLJ, virtual common RAM (CIlAM
), the first common connection line H-
The address of the changed data and the changed data are transmitted to other CPUs using DATA or 0-DATA (see FIG. 2). When all CPUs receive the above data through the common connection line H-DATA or 0-DATA, they change the data at the corresponding address in each virtual common RAM (CRAM).

According to such a method, since only changed data is transmitted regardless of the size of the virtual common RAM, the average data transmission speed is high and the CPU processing time required for data transmission is shortened. In addition, compared to the common RAM method using time-sharing access that was conventionally used in minicomputers, each CPU uses its own virtual common 1NAM (CRAM).
It has the advantage of shortening the average access time because it can be referenced.

Table 1 shows the virtual common RAM (CRAM) in this embodiment.
This is the data stored in the .

(Leaving space below) Table 1 Data contents include, for example, the copying status signal covers each status of the copying process such as paper feed signal, ejection signal, copy command signal, return signal, wait signal, etc. The signal contains data such as vapor size, paper feed port, magnification, etc. The trouble information signal contains jam code and trouble code, and the operation panel information signal contains numeric keypad manual information, number of sheets displayed, etc. ing.

Further, the various signals of the copying process include, for example, information at predetermined timings regarding the status of various sensors in the copying machine main body l and a control timer in the CPU.

Basically, this information is stored in the virtual common RAM (CRAM) of all CPUs, but it is also possible to selectively store necessary information in each CPU. In this case, when data changed by another CPU is received, each 01) U virtual common RAM (CR
AM) will not be updated.

FIG. 5 is a timing chart of data transmission between CPUs.

Transmission from the host CPU 10 to the options CPU II to 14 is performed at any timing via the connection line H-DATA. On the other hand, transmission from the option CPU11-14 to the host CPU10 is performed by time-sharingly using the connection line 0-DATA among a plurality of options CPLIII to 凰4. For time division control, each CPU's control input port E
control connection line 21 connected to l and control output boat EO
This is done by The control connection line 21 has “[I” and “L”
Each option CPU becomes capable of transmitting data when the control input port El of each option CPU changes from one level to the other level.

At this time, if there is data to be sent from the optional CPU, the host CPU sends it via the first common connection line 0-DATA.
Sends to Ul0. Then, when the transmission is completed or there is no data to be transmitted, the second common connection line 0-
In order to transfer the right to use DATA to the next optional CPU, the level of the vote EO of the optional CPU is inverted.

The second common connection line 0-DATA can be used with optimal efficiency by sequentially performing the above operations by each option CPU.

The last option CPU EO (i.e., host) CPU
When El of lO changes from one level to the other, the host CPU l0 connects the second common connection line 0-DATA
It is assumed that the right to use the CPIJ has come to an end, and the host CPIJ
l Inverts the EO of O and allows transmission of the next transmission.

Even during the above sequence, data is constantly transmitted from the host CPU 1O to the option CPU.

FIG. 6 shows a data format used for data transmission in the embodiment.

The communication hardware built into each CPU is
Word and 8-bit asynchronous communication is possible. In the case of a data format in which the l frame consists of 16 bits, the transmission of one frame is completed by transmitting the l word twice, as shown in FIG. The identification bit, which is the first bit of each frame, is used to synchronize the frames.
The first bit (identification bit) of the second word is "BI", and the first bit (identification bit) of the second word is "θ".

This makes it possible to synchronize the next frame even if an error occurs during transmission.

Also, even if the l frame has a data format of 3 words or more, the first bit (identification bit) from the third word onwards is set to 0.
”, it becomes possible to synchronize the frames.

In Figure 6, 7 bits of bo""'b6 are the data of the virtual common RAM to be sent, and 7 bits of b8 to b14 indicate the address of the virtual common RAM, and 2 words are 1 bit.
It can handle up to 28 types of data.

Next, the programs of each CPU will be explained with reference to flowcharts.

FIGS. 8-1 to 8-5 are flowcharts showing the transmission from the host CPU, and FIGS. 9-1 to 9-4 are flowcharts showing the operation of the option CPUll-14. Here, only the communication control portion related to this embodiment will be explained.

First, the communication control program of host CPU10 will be explained. The communication control program of the host CPLIIO consists of four interrupt processing routines. These are the 01 interrupt, timer interrupt, transmission interrupt, and reception interrupt processing routines. These interrupt handling routines operate independently of the main routine (FIG. 8-1) when six interrupt signals are input.

FIG. 8-2 shows a flowchart of the 91 interrupt 4'. 9
1 interrupt operates at the rising or falling level of the U El port (CI). In the 91 interrupt routine, when the level of the boat El changes from "0" to "l", the boat EO is set to "0", and conversely, when the level of El changes from "B" to "0", the boat EO is set to "0". Set to “l”.

FIG. 8-3 shows a timer interrupt routine, which is activated at regular intervals determined by a timer T built into each CPU. The timer interrupt routine searches for changed data in virtual common RAM (ORAM) and initiates transmission to the optional CPU. Change data is determined by the most significant bit of each data in virtual common RAM (CRAM). When data received from the optional CPU or data is changed in the post CPLJ main routine, the most significant bit is set to 1. In the timer interrupt routine, first, in step #20, the transmission state TMODE is checked to see if data is currently being transmitted. When the transmission of the previous data is completed, 'I' is sent in step #32 (Figure 8-4).
” The contents of MOD E will be 3.The initial value is
It is set to 3 by the routine. If it is not being transmitted, the virtual common RAM (CR
Search for change data in AM). If there is change data, the answer is YES in step #23, and the process proceeds to step #24, where the data address “I” and the data are sent to the sending buffer T.
DATA (not shown). At this time, "l" is set in the most significant bit (identification bit) of the first data (first word) to be written to the buffer TDATA.

Next, in #25, TMODE is set to "B", the first data is set in the transmission register SR, and in #26, transmission is started, the specified data is sent, and the process ends. From then on, processing is performed by a transmission interrupt. .Furthermore, in #25, the most significant bit of each data in the virtual common RAM (CRAM) of the CPU is reset to "0".

#27 and #28 are steps for accessing the address of the virtual common RAM (CRAM), and the above-described operation is repeated until the address to be accessed reaches 128.

FIG. 8-4 shows a flowchart of the transmission interrupt routine. A transmission interrupt occurs when the transfer of data in the transmission register Sl (is completed. In the transmission interrupt routine, first, in step #30, TMODE is used to check which data has been transmitted. If the contents of TMODE are "1'', the previous data is the first data, so in step #31 the second data (word data) is set in the transmission register.Finally, in step #32, the T
Add "I" to MODE. When the transmission of the second data is completed, the content of TMODE becomes "3".

Figure 8-5 is a flowchart of the reception interrupt routine.
This occurs when data reception in the reception register 1111 of the CPU is completed. In the reception interrupt routine, first, in step #40, a reception status aRM is received.

The DE checks whether reception of the l frame is completed. The initial value for RMODE is set by the main routine.
1" is set. If RM OD E is "1", the most significant bit (identification bit) of the received data (word data) is checked in #46 to check whether it is the first data. This causes the frame to be If it is the first data, the received data is transferred to the reception buffer yRDA.
It is saved to TA in step #47. And step #
Set RMODE to "2" in 4B. On the other hand, if the content of RMODE is "2", the received data is saved to the receive buffer in step #41, and the address in the virtual common RAM (ORAM) is saved from the first data in step #42. Then, in step #43, the lower 7 bits of the second data are stored as update data in the above-mentioned address of the virtual common RAM (CRAM).
At step 44, the most significant bit of the lower seven bits is set to "1". In the timer interrupt routine, this “
1" and sends it to the option CPU.Finally, set RMODE to "1" for receiving the next frame.

Next, the communication control program of the optional CPU will be explained. Basically, it is the same as in the case of the host CPU, but the difference is that the search and transmission of transmission data is synchronized with changes in El, and the reception data is not transmitted.

Therefore, no timer interrupt processing is performed.

FIG. 9-2 is a flowchart of the 81 interrupt processing routine.

First, search the transmitted data, and if there is any changed data,
Start sending the first data (first word data). This is the same as the host CPU's timer interrupt processing.

However, if there is no change data on the optional cPU,
In order to transfer the right to use the data bus 0-DATA to the next option cPU, the state of the input terminal El is output to the output terminal EO in step #68. The transmission of the second data is also performed by a transmission interrupt, similar to the host CPU.

FIG. 9-3 shows a flowchart of the transmission interrupt processing routine. This is also basically the same as the transmission interrupt processing from the host CPU. The difference is step #73.
E after the transmission of the th data (word data) is completed.
The purpose is to output l to EO.

Figure 9-4 is a flowchart of the reception interrupt routine. In this case as well, the host CPU's reception interrupt processing is different in that a bit for a transmission request is not added to the updated data in the virtual common RAM (CRAM). different. Optional CPU
In this case, the transmitted data is changed only in the main routine.

As is clear from the above explanation, the present invention transmits word data of a predetermined bit length multiple times.
This is a data transmission method for transmitting one frame of data, in which a specific bit of each word data is an identification bit indicating whether or not it is the first word of one frame, and the first word data is set as the identification bit of the first word data of each frame. Since the data is transmitted with identification data indicating that the Increases the efficiency of data transmission.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example in which the data transmission system of this invention is applied to a copying machine, FIGS. 2 and 3 are block diagrams showing an embodiment of this invention, and FIG. 4 is a CPU used in this invention. FIG. 5 is a time chart showing the operation of the embodiment of FIG. 2, and FIGS. 6 and 7 are block diagrams showing the internal details of the embodiment of FIG. diagram showing,
Figures 8-1 to 8-5, Figures 9-1 to 9-
FIG. 4 is a flowchart showing the operation of the embodiment shown in FIG. 10...Host CPU, 11...Master CPU, 1
2 to I4...Optional CPU, 20...Data bus, If-DATAA-...First common connection line, O
-DATA ・Second common connection line. Patent Applicant Minolta Camera Co., Ltd. Agent Patent Attorney 1 other person (1 person) Figure 1 Figure 3 Figure 4 Figure 5 Figure 8-2 Section 8-3 Figure 8-4 Section 8-5 Figure 9-4

Claims (1)

[Claims] (1) A data transmission method that transmits one frame of data by transmitting word data of a predetermined bit length multiple times, and indicates whether a specific bit of each word data is the first word of one frame or not. A data transmission method characterized in that data is transmitted by attaching identification data indicating that the data is the first word to the identification bit of the first word data of each frame.