JPH02266572A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH02266572A
JPH02266572A JP8763489A JP8763489A JPH02266572A JP H02266572 A JPH02266572 A JP H02266572A JP 8763489 A JP8763489 A JP 8763489A JP 8763489 A JP8763489 A JP 8763489A JP H02266572 A JPH02266572 A JP H02266572A
Authority
JP
Japan
Prior art keywords
conductive layer
type conductive
static electricity
contact
diode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8763489A
Other languages
Japanese (ja)
Inventor
Yuki Maeda
前田 志
Tetsuaki Wada
哲明 和田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP8763489A priority Critical patent/JPH02266572A/en
Publication of JPH02266572A publication Critical patent/JPH02266572A/en
Pending legal-status Critical Current

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  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To improve static electricity resistance and prevent element area from increasing by forming the plane shape of the contact for leading out an N-type conductive layer and that for leading out a P-type conductive layer longer in parallel to the junction part located between both contacts. CONSTITUTION:A P-type conductive layer lead-out contact 10 and an N-type conductive layer lead-out contact 11 are formed in longer shape being in parallel to a junction part 12. With this structure, it is possible to reduce effective current density flowing crossly through the junction part 12 when static electricity is applied to and it is not necessary to adopt a simple expansion method of junction area which has been made conventionally, thus improving static electricity resistance of a diode efficiently. Therefore, it is possible to improve static electricity resistance of a semiconductor device drastically and to prevent unneeded element area from increasing.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は半導体装置に関し、さらに詳述すれば、外部か
らの静電気に対して保護効果の高いチップ上に形成され
たダイオード構造に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor device, and more specifically, to a diode structure formed on a chip that is highly effective in protecting against external static electricity.

従来の技術 集積回路半導体装置はその取り扱い過程で静電気が外部
端子リードを介して外囲部内に収納された半導体チップ
に印加されることにより、集積回路を構成する素子を破
壊する、いわゆる静電気破壊故障を発生しやすく、中で
もダイオードの接合破壊は最も多い静電気破壊故障の1
つである。このため外部端子への引き出し用としてチッ
プ周辺部に形成された電極に金属配線パターンによって
直結されたダイオードの場合、静電気によるダメージを
最も受けやすいことから、静電気対策が構造的にとられ
ていた。
Conventional technologyIn the handling process of integrated circuit semiconductor devices, static electricity is applied to the semiconductor chip housed in the outer enclosure through the external terminal leads, resulting in so-called electrostatic breakdown failure, which destroys the elements that make up the integrated circuit. Among them, diode junction breakdown is one of the most common electrostatic breakdown breakdowns.
It is one. For this reason, in the case of a diode that is directly connected to an electrode formed on the periphery of the chip by a metal wiring pattern for leading out to an external terminal, it is most susceptible to damage from static electricity, so static electricity countermeasures have been taken structurally.

従来のダイオードの静電気対策構造について第4図のP
型導電層領域内にN型の導電層領域を設けたダイオード
の場合を例に説明する。同図においてP型導電層1およ
びN型導電層2はダイオード素子上部に配置された2つ
の金属配線3,4にコンタクト5,6を介してそれぞれ
電気的に結線された構造になっている。このダイオード
構造において接合部はほぼN型導電層2の平面形状と−
致する。従来、静電気により金属配線4からダイオード
に印加された電荷はほぼ接合部全面すなわちN型導電層
2の平面形状全体を流れてP型厚電層1に入り、コンタ
クト5を介して金属配線3に逃げるものと説明されてい
た。このため、同図のようにできるだけN型導電層2の
平面面積を大きくすることで静電気印加時の接合面の実
効電流密度を低下させ、ダイオードの静電気耐量を向上
させる方法がとられていた。
Regarding the static electricity countermeasure structure of conventional diodes, see P in Figure 4.
The case of a diode in which an N-type conductive layer region is provided within the N-type conductive layer region will be described as an example. In the figure, a P-type conductive layer 1 and an N-type conductive layer 2 are electrically connected via contacts 5 and 6 to two metal wirings 3 and 4 arranged above a diode element, respectively. In this diode structure, the junction is approximately connected to the planar shape of the N-type conductive layer 2.
I will. Conventionally, the electric charge applied from the metal wiring 4 to the diode due to static electricity flows through almost the entire surface of the junction, that is, the entire planar shape of the N-type conductive layer 2, enters the P-type thick conductive layer 1, and is transferred to the metal wiring 3 via the contact 5. It was described as something to run away from. For this reason, as shown in the figure, a method has been used to increase the planar area of the N-type conductive layer 2 as much as possible to reduce the effective current density at the junction surface when static electricity is applied, and to improve the static electricity resistance of the diode.

発明が解決しようとする課題 しかし、このように接合面積を大きくすることによるダ
イオードの静電気耐量の改善は言うまでもなく素子面積
の増大を招き、最終的にチップ面積の縮小化の妨げにな
る場合があった。また、期待したほど静電気耐量が改善
しないことがあり、効果的な静電気耐量改善手法の開発
が望まれていた。
Problems to be Solved by the Invention However, improving the electrostatic resistance of the diode by increasing the junction area in this way may of course lead to an increase in the element area, which may ultimately hinder the reduction of the chip area. Ta. Furthermore, the static electricity resistance may not be improved as much as expected, and it has been desired to develop an effective method for improving the static electricity resistance.

本発明はかかる点に鑑みてなされたもので、筏状は静電
気により印加された電荷が接合部全面2ではなく、N型
導電層引き出し用コンタクト6とP型厚電層引き出し用
コンタクト5の間に位置する接合部7を横断的に流れる
ことを見い出した上で効果的なダイオードの静電気耐量
改善構造を提供するものである。
The present invention has been made in view of this point, and the raft shape allows the electric charge applied by static electricity to be applied not to the entire surface of the joint 2, but between the N-type conductive layer lead-out contact 6 and the P-type thick conductive layer lead-out contact 5. The present invention provides an effective structure for improving the static electricity resistance of a diode by discovering that the current flows across the junction 7 located at the junction 7.

課題を解決するための手段 前記問題点を解決するため、本発明は、N型導電層引き
出し用コンタクトとP型厚電層引き出しコンタクト部の
平面形状が前記両コンタクト間に位置する接合部とほぼ
平行する形で細長く形成された構造にしたものである。
Means for Solving the Problems In order to solve the above-mentioned problems, the present invention provides that the planar shape of the N-type conductive layer lead-out contact and the P-type thick conductive layer lead-out contact portion is approximately the same as the junction located between the two contacts. It has a parallel elongated structure.

作用 本発明によると、静電気によりダイオードに印加された
電荷の放電が接合面積全体ではなく両コンタクト間に位
置する接合部を横断的に流れることに着眼し、両コンタ
クト部の平面形状を接合部に沿って細長く形成した構造
であるので、この構造によって静電気印加時に接合部を
横断的に流れる実効的な電流密度を低下させることがで
き、また従来行なわれていた接合面精の単純な拡大手法
を取る必要はなく、結果的に効率的にダイオードの静電
耐量を改善することができる。
According to the present invention, focusing on the fact that the discharge of the charge applied to the diode due to static electricity flows not across the entire junction area but across the junction located between the two contacts, the planar shape of both the contact parts is adjusted to the junction. Since the structure is formed in a long and narrow direction, it is possible to reduce the effective current density that flows across the joint when static electricity is applied. It is not necessary to remove the capacitance, and as a result, the electrostatic withstand capacity of the diode can be efficiently improved.

実施例 次に本発明を実施例により説明する。Example Next, the present invention will be explained by examples.

第1図はP型導電層領域8内にN型導電層領域9を設け
た構造の本発明による最も基本的なダイオードの平面図
である。同図においてP型厚電層引き出しコンタクト1
0とN型導電層引き出しコンタクト11は接合部12と
平行して細長く形成された構造になっている。長手方向
のコンタクト長としては50μm以上あれば十分な静電
気耐量がほぼ得られる。
FIG. 1 is a plan view of the most basic diode according to the present invention having a structure in which an N-type conductive layer region 9 is provided within a P-type conductive layer region 8. In the figure, P-type thick electric layer lead-out contact 1
The 0 and N type conductive layer lead-out contacts 11 have an elongated structure parallel to the bonding portion 12. If the contact length in the longitudinal direction is 50 μm or more, sufficient electrostatic resistance can be obtained.

第2図は、第1図と異なり、コンタクト部を複数の小コ
ンタクト13を用いて形成した例である。この場合も第
1図の例と同様の効果が得られる。
Unlike FIG. 1, FIG. 2 shows an example in which the contact portion is formed using a plurality of small contacts 13. In this case as well, the same effect as in the example of FIG. 1 can be obtained.

第3図は本発明を高電位電源用金属配線I4と低電位電
源用金属配線15に接合されたダイオード構造に適用し
た例である。高電位電源用金属配!1I114はN型導
電領域16とコンタクト部17を介して接続され、低電
位電源用金属配線15はP型導電領域18とコンタクト
19を介して接続されている。P型導電領域18のコン
タクト19は静電気の放電電流密度を効率良く下げるた
めN型導電領域16のコンタクト部17の両側に設けら
れた構造になっている。この場合、上記2つの金属配線
14.15がチップ内部回路を囲むように並んで配置さ
れている場合に特に効果的に適用できる。
FIG. 3 shows an example in which the present invention is applied to a diode structure connected to a metal wiring I4 for a high potential power source and a metal wiring 15 for a low potential power source. Metal wiring for high potential power supply! 1I 114 is connected to the N-type conductive region 16 through a contact portion 17, and the low-potential power supply metal wiring 15 is connected to the P-type conductive region 18 through a contact 19. The contacts 19 of the P-type conductive region 18 are provided on both sides of the contact portion 17 of the N-type conductive region 16 in order to efficiently reduce the discharge current density of static electricity. In this case, it can be applied particularly effectively when the two metal interconnections 14 and 15 are arranged side by side so as to surround the chip internal circuit.

以上説明してきたようなダイオードの引き出し用コンタ
クト構造にすることにより、静電気が印加されても破壊
しにくいダイオードを得ることができる。
By adopting the contact structure for drawing out the diode as described above, it is possible to obtain a diode that is difficult to break down even when static electricity is applied.

なお本実施例ではP型導電領域内にN型導電領域を設け
たダイオードを用いて説明したが、当然N型導電領域内
にP型導電領域を設けたダイオードに対しても同じ効果
がある。
Although this embodiment has been described using a diode in which an N-type conductive region is provided within a P-type conductive region, the same effect can naturally be obtained for a diode in which a P-type conductive region is provided within an N-type conductive region.

また、N型導電層領域とP型溝電層領域のコンタクト引
き出し配線が結線される外部端子引寺出し電極は、それ
ぞれ、高電位設定電源端子と低電位設定電源端子である
場合、高電位設定電源端子と外部出力用端子または外部
入力用端子である場合、低電位設定電源端子と外部出力
用端子または外部入力用端子のどの場合のいずれにも適
用が可能である。
In addition, if the external terminal lead-out electrodes to which the contact lead-out wiring in the N-type conductive layer region and the P-type trench conductive layer region are connected are a high potential setting power supply terminal and a low potential setting power supply terminal, respectively, the high potential setting In the case of a power supply terminal and an external output terminal or an external input terminal, the present invention can be applied to any case of a low potential setting power supply terminal and an external output terminal or an external input terminal.

発明の効果 以上述べたように、本発明のダイオードを有する半導体
装置により、半導体装置の静電気耐量を著しく改善する
とともに無駄な素子面積の増大防止を図ることが可能と
なった。
Effects of the Invention As described above, the semiconductor device having the diode of the present invention makes it possible to significantly improve the electrostatic resistance of the semiconductor device and to prevent unnecessary increase in element area.

【図面の簡単な説明】[Brief explanation of drawings]

第1図、第2図および第3図は本発明の実施例ダイオー
ドの平面図、第4図は従来ダイオードの平面図である。 1・・・・・・P型厚電層領域、2・・・・・・N型導
電層領域、3・・・・・・P型導電層からの引き出し配
線、4・・・・・・N型導電層からの引き出し配線、5
・・・・・・P型厚電層コンタクト、6・・・・・・N
型導電層コンタクト、7・・・・・・コンタクト間に位
置する接合部、8・・・・・・P型厚電層領域、9・・
・・・・N型導電層領域、10・・・・・・P型厚電層
コンタクト、11・・・・・・N型導電層コンタクト、
12・・・・・・コンタクト間に位置する接合部、13
・・・・・・小コンタクト、14・・・・・・高電位電
源用金属配線、15・・・・・・低電位電源用金属配線
、16・・・・・・N型導電領域、17・・・・・・N
型導電層コンタクト、18・・・・・・P型導電領域、
19・・・・・・P型厚電層コンタクト。 代理人の氏名 弁理士 粟野正字 ほか1名第3図
1, 2, and 3 are plan views of a diode according to an embodiment of the present invention, and FIG. 4 is a plan view of a conventional diode. 1... P-type thick electric layer region, 2... N-type conductive layer region, 3... Extract wiring from the P-type conductive layer, 4... Extract wiring from N-type conductive layer, 5
・・・・・・P type thick electric layer contact, 6・・・・・・N
type conductive layer contact, 7... junction located between contacts, 8... P type thick conductive layer region, 9...
...N-type conductive layer region, 10...P-type thick conductive layer contact, 11...N-type conductive layer contact,
12... Joint portion located between contacts, 13
...Small contact, 14...Metal wiring for high potential power supply, 15...Metal wiring for low potential power supply, 16...N-type conductive region, 17・・・・・・N
type conductive layer contact, 18...P type conductive region,
19...P-type thick electrical layer contact. Name of agent: Patent attorney Masaji Awano and one other person Figure 3

Claims (1)

【特許請求の範囲】[Claims] 半導体シリコン基板の表面部に形成されたプレーナ型ダ
イオードを構成するN型導電層領域の電極引き出し用コ
ンタクト部とP型導電層領域の電極引き出し用コンタク
ト部の平面形状が前記ダイオードの前記両コンタクト間
に位置するPN接合部とほぼ平行する形で50μm以上
の長さに細長く形成され、かつ、前記N型導電層領域と
P型導電層領域との各コンタクト引き出し配線がそれぞ
れ異なる外部端子への引き出し電極に接続されたことを
特徴とする半導体装置。
A planar shape of a contact portion for drawing out an electrode in an N-type conductive layer region and a contact portion for drawing out an electrode in a P-type conductive layer region constituting a planar diode formed on a surface portion of a semiconductor silicon substrate is between the two contacts of the diode. The contact lead wires are formed in a long and narrow shape approximately parallel to the PN junction located in the area and have a length of 50 μm or more, and each of the contact lead wires between the N-type conductive layer region and the P-type conductive layer region leads to different external terminals. A semiconductor device characterized by being connected to an electrode.
JP8763489A 1989-04-06 1989-04-06 Semiconductor device Pending JPH02266572A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8763489A JPH02266572A (en) 1989-04-06 1989-04-06 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8763489A JPH02266572A (en) 1989-04-06 1989-04-06 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH02266572A true JPH02266572A (en) 1990-10-31

Family

ID=13920410

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8763489A Pending JPH02266572A (en) 1989-04-06 1989-04-06 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH02266572A (en)

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