KR101050456B1

KR101050456B1 - Static electricity protection device

Info

Publication number: KR101050456B1
Application number: KR20080111248A
Authority: KR
Inventors: 최낙헌
Original assignee: 주식회사 하이닉스반도체
Priority date: 2008-11-10
Filing date: 2008-11-10
Publication date: 2011-07-19
Also published as: KR20100052293A

Abstract

The present invention relates to an electrostatic protection device, comprising: a first well; A second well formed inside the first well; A guard formed by implanting a first impurity into a ring shape along an edge of the first well on the first well while having a plurality of first input / output contact regions in which the plurality of separated first wells are exposed. ring; A first contact region having a plurality of second input / output contact regions in which a plurality of separated second wells are exposed, and having a second impurity injected into a region extending between the first well and the second well; A second contact region formed by implanting the second impurity into a region adjacent to the first contact region on the first well; A gate pattern formed on a space in which the first contact region and the second contact region are spaced apart from each other; A plurality of first input / output contacts formed by implanting the second impurities into a plurality of first input / output contact regions; And a plurality of second input / output contacts formed by implanting the first impurities inside the plurality of second input / output contact regions; The plurality of first input / output contacts and the plurality of second input / output contacts may be electrically connected to one input / output pad.

Antistatic Circuits, Capacitances, Wells, Conductive Layers

Description

Static protection device {A DEVICE FOR PREVENTING CIRCUIT FROM DISCHARGE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrostatic protection device, and more particularly, to an electrostatic protection device for minimizing input capacitance of a high speed semiconductor by minimizing a contact area between an area connected to an input / output terminal and a well to increase electrostatic discharge efficiency.

In general, when a semiconductor integrated circuit is in contact with a human body or a machine, the static electricity charged in the human body or the machine is discharged into the semiconductor, and thus the semiconductor internal circuit may be greatly damaged.

The semiconductor integrated circuit configures an electrostatic protection circuit between the input / output pad and the semiconductor internal circuit to protect the semiconductor internal circuit from such damage.

1 illustrates a layout of a static electricity protection circuit provided in a conventional input / output terminal.

Referring to FIG. 1, the conventional static electricity protection circuit 100 includes an N-type well 120 formed by being surrounded by a P-type well 110, and the P-type well 110 includes N + impurity zero having a bar shape. An inverse 130 is formed, and a P-type impurity region 140 having a bar shape is formed in the N-type well 120.

At this time, a guard ring 150 formed by P + impurities is formed at the periphery of the P-type well 110.

Meanwhile, a bar-shaped N + impurity region 160 is formed at a portion where the P-type well 110 and the N-type well 120 are joined, while the N + impurity region 170 is a P-type spaced apart from the N + impurity region 160. Formed on the well 110.

The gate pattern 180 is formed between the N + impurity region 160 and the N + impurity region 170.

In the conventional static electricity protection circuit 100 as shown in FIG. 1, the input / output terminal I / O is connected to the N + impurity region 130 and the P + impurity region 140, and the ground voltage pad VSS is connected to the gate 180. It is connected to the N + impurity region 170 and the guard ring 150.

By the above configuration, the static electricity protection circuit of FIG. 1 serves to discharge static electricity applied from the input / output terminal I / O.

However, the conventional static electricity protection circuit has a bar shape that makes electrical contact with the input / output pad (I / O), thereby increasing the junction area between the N type well and the P type well with each P + impurity region and the N + impurity region.

Therefore, the capacitance component at the input and output terminals is increased due to the large bonding area, which leads to a problem of lowering the electrostatic discharge efficiency. As a result, the junction between each well and an impurity in a high-speed semiconductor device requiring a device having a higher electrostatic discharge efficiency compared to the capacitance. There was a need for a technique that could reduce area.

The present invention provides an electrostatic protection device in which the electrostatic discharge efficiency of the capacitance is greatly increased by reducing the contact area between impurities connected to the input and output terminals and each well bonded to the input and output terminals.

Electrostatic protection device according to the invention the first well; A second well formed inside the first well; A guard formed by implanting a first impurity into a ring shape along an edge of the first well on the first well while having a plurality of first input / output contact regions in which the plurality of separated first wells are exposed. ring; A first contact region having a plurality of second input / output contact regions in which a plurality of separated second wells are exposed, and having a second impurity injected into a region extending between the first well and the second well; A second contact region formed by implanting the second impurity into a region adjacent to the first contact region on the first well; A gate pattern formed on a space in which the first contact region and the second contact region are spaced apart from each other; A plurality of first input / output contacts formed by implanting the second impurities into a plurality of first input / output contact regions; And a plurality of second input / output contacts formed by implanting the first impurities inside the plurality of second input / output contact regions; The plurality of first input / output contacts and the plurality of second input / output contacts may be electrically connected to one input / output pad.

Preferably, the first well is characterized in that the P-type.

In addition, the second well is characterized in that the N-type.

In addition, the guard ring is preferably formed of a P-type impurity, characterized in that the ground voltage is connected.

In addition, the first contact region is preferably formed of an N-type impurity, characterized in that the power supply voltage is connected.

In addition, the second contact region is preferably formed of an N-type impurity, characterized in that the power supply voltage is connected.

Preferably, the first input / output contact is formed of an N-type impurity.

In addition, preferably, the second input / output contact is formed of a P-type impurity.

In addition, preferably, a resistance is connected between the gate and the second contact region, and the first contact region is connected with the gate and the resistor interposed between the capacitor.

According to the present invention, in the formation of the electrostatic discharge element at the input / output terminal, by forming a small number of impurities connected to the input / output terminal, the electrostatic discharge efficiency is greatly increased compared to the capacitance while reducing the contact area of each well bonded thereto. There is an effect that can increase the stability and reliability of the semiconductor.

In addition, the present invention is composed of a small number of impurities connected to the input and output terminals, the current is proportional to the parameter (PERIMETER) due to the characteristic that there is no loss in the amount of current compared to the conventional, so conducting a large amount of electrostatic current even in a small junction area It can be effected.

The electrostatic protection device according to the present invention discloses a configuration in which P-type or N-type impurities are formed to have a small contact area with respect to N-type wells and P-type wells.

2 and 3 to describe in detail, the electrostatic protection device 200 according to the present invention first. The first well 210 and the second well 220 formed inside the first well 210 are formed, the first well 210 is formed in a P type, and the second well 220 is an N type. Is formed.

The guard ring 230 is formed on the first well 210 to form a ring shape along an edge of the first well 210.

The guard ring 230 is formed by implanting a first impurity and is formed to have a plurality of first input / output contact regions 231 in which a plurality of separated first wells 210 are exposed.

A second impurity is injected into each of the plurality of first input / output contact regions 231 to form the first input / output contact 240.

In this case, the guard ring 230 is formed of P-type impurities, and the first input / output contact 240 is formed of N-type impurities.

A ground voltage is connected to the guard ring 230, and an input / output terminal I / O is connected to the first input / output contact 240 so as to be connected to one input / output pad (not shown), and the first input / output contact 240 may be connected to the guard ring 230. The region A including the guard ring 230 acts as a diode.

Meanwhile, the first contact region 250 is formed in the region spanning the first well 210 and the second well 220.

The first contact region 250 is formed by implanting second impurities, and has a plurality of second input / output contact regions 251 in which a plurality of separated second wells 220 are exposed.

A first impurity is implanted into each of the second input / output contact regions 251 to form a second input / output contact 260.

The first contact region 250 is formed of N-type impurities, and the second input / output contact 260 is formed of P-type impurities.

A power supply voltage is connected to the first contact region 250, and the second input / output contact 260 is connected to one input / output pad (not shown) by connecting an input / output terminal I / O.

Meanwhile, a second contact region 270 formed by implanting a second impurity is formed in a region adjacent to the first contact region 250 on the first well 210.

The second contact region 270 is formed of N-type impurities and is connected to the ground voltage.

The region B including the second input / output contact 260 of the first contact region 250 acts as a diode, and the first contact region 250 includes the gate 280 from the first contact region 250 including the gate 280 to the second contact region 270. The leading region C acts as an NMOS transistor.

Meanwhile, referring to FIG. 4, a resistor 291 is connected between the gate 280 and the second contact region 270, and the first contact region 250 has a capacitor 292 interposed therebetween, and the gate 280 is interposed therebetween. And another embodiment in connection with the resistor 291 is possible.

According to another embodiment of the present invention, the static electricity applied to the input / output terminal is discharged at a low voltage, thereby further increasing the discharge efficiency.

As described above, the configuration of the electrostatic protection device according to the preferred embodiment of the present invention is illustrated in the drawings and described as described above, but this is merely described, for example, and various designs without departing from the technical spirit of the present invention. And it will be readily apparent to those skilled in the art that modifications and variations are possible within the scope of the invention.

1 is a layout of a conventional static electricity protection device.

2 is a layout of the electrostatic protection device according to the present invention.

3 is a sectional view taken along line D-D 'of the electrostatic protection device according to the present invention;

4 is a sectional view taken along the line D-D 'according to another embodiment of the present invention.

Claims

First well;

A second well formed inside the first well;

A guard formed by implanting a first impurity into a ring shape along an edge of the first well on the first well while having a plurality of first input / output contact regions in which the plurality of separated first wells are exposed. ring;

A first contact region having a plurality of second input / output contact regions in which a plurality of separated second wells are exposed, and having a second impurity injected into a region extending between the first well and the second well;

A second contact region formed by implanting the second impurity into a region adjacent to the first contact region on the first well;

A gate pattern formed on a space in which the first contact region and the second contact region are spaced apart from each other;

A plurality of first input / output contacts formed by implanting the second impurities into a plurality of first input / output contact regions; And

A plurality of second input / output contacts formed by injecting the first impurities into a plurality of second input / output contact regions;

And the plurality of first input / output contacts and the plurality of second input / output contacts are electrically connected to one input / output pad.

Claim 2 has been abandoned due to the setting registration fee.

The method of claim 1,

The first well is a static electricity protection device, characterized in that the P-type.

Claim 3 was abandoned when the setup registration fee was paid.

The method of claim 2,

And the second well is N-type.

Claim 4 was abandoned when the registration fee was paid.

The method of claim 3, wherein

The guard ring is formed of a P-type impurity, characterized in that the ground voltage is connected to the electrostatic protection device.

Claim 5 was abandoned upon payment of a set-up fee.

The method of claim 4, wherein

The first contact region is formed of N-type impurities, characterized in that the power supply voltage is connected.

Claim 6 was abandoned when the registration fee was paid.

The second contact region is formed of an N-type impurities, characterized in that the ground voltage is connected to the electrostatic protection device.

Claim 7 was abandoned upon payment of a set-up fee.

The method of claim 6,

And the first input / output contact is formed of an N-type impurity.

Claim 8 was abandoned when the registration fee was paid.

The method of claim 7, wherein

And the second input / output contact is formed of a P-type impurity.

Claim 9 was abandoned upon payment of a set-up fee.

9. The method according to any one of claims 1 to 8,

A resistor is connected between the gate and the second contact region, and the first contact region is connected with the gate and the resistor interposed between the capacitor and the capacitor.