JPH02264434A - Automatic wiring system - Google Patents

Abstract

PURPOSE:To automatically decide the main line layers for avoiding the intersection of the main lines with branch lines by a method wherein the main line layers are automatically decided in an LSI automatic wiring system meeting the requirements specified for respective branch line layers and then the algorism assigned to a truck is adopted to designate the layers per terminal. CONSTITUTION:A CPU 6 firstly reads out the program of a memory 1 successively reading put respective logic data, terminal data and figure data of the memories 2-4; performs wiring processes by the program read out of the memory 1 using the said data as the premises; decides the wiring route main line layer by using and renewing the main line layer data from a memory 5 processed by a terminal layer of the memory 3 so as to store the decided wiring route main line layer. When a wiring shortage occurs during the wiring process, the wiring can be performed by changing the processing order of the main line and deciding the main line layer. Through these procedures; the main line layers can be decided in the assigned order by making use of the adopted algorism.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention relates to an automatic wiring system for LSI, and in particular to an automatic wiring system for LSI.
This relates to a wiring system between internal circuit blocks, particularly a channel wiring system.

[Conventional technology]

FIG. 9 is an inter-block pattern diagram for explaining the channel wiring inside the conventional LSI, and FIGS. 10 and 11 are pattern diagrams for explaining the case where the channel wiring inside the conventional LSI becomes impossible.

In FIG. 9, circuit block AαQ and circuit block B0
The pattern between υ lies on the virtual mesh of the wiring channel C■. Terminals on circuit block AQO and circuit block BCIIJ are connected according to a given netlist (connection information between terminals).

The connection network between these terminals is called a net. A net consists of a main line, which is a horizontal wiring, and a branch line, which is a vertical wiring. The main line of each net is assigned to track α or day α, and the branch lines are assigned to columns. FIG. 9 is a pattern diagram based on the conventional two-layer automatic wiring method, which is based on the premise that all the main lines of the nets are assigned to one layer and the branch lines are assigned to another layer. Since trunk lines and branch lines are assigned to different layers, overlapping of trunk lines and branch lines on the same layer of different nets is not allowed, but since trunk lines and branch lines are completely different layers, they are allowed to intersect at any location.

(In addition, regarding the loop problem of the so-called constraint that upper and lower branch lines do not overlap - the upper and lower constraints between main lines, see, for example, 17+h DAG, °°A"G (1980)
rid Free”Channel Router”
It is assumed that the problem has been solved using a method such as ) [Problems to be Solved by the Invention] The conventional two-layer wiring system based on the fft-edge method, for example, is configured as described above. It was always necessary to define one layer different from the main layer. This could be applied to automatic wiring between macro cells in a cell-based (or building block) system or between standard cells in a gate array system, but it can be applied to more microscopic automatic wiring within functional blocks such as data buses. So Poly, All
, Al2, etc. are common, and users have been demanding to realize an automatic wiring system that can specify various layers as branch lines and minimize the number of via holes. For example, if you change some of the terminal layers in Figure 9 as shown in Figures 10 and 11, the conventional 1ef-edge
If the law is left unchanged, the X location shown in Figure 10 and the Y location shown in Figure 11 will be
An electrical short occurs at the location.

This invention was made to solve the above problem. When the user specifies a layer for each terminal (that is, for each branch line), the main line layer is automatically determined, and the main line layer of the same layer is The purpose is to obtain an automatic wiring method that allows wiring without crossing branch lines.

[Means to solve the problem]

Conventionally, LSI automatic wiring systems have made wiring algorithms easier by using the premise that trunk lines and branch lines of different signals can intersect at any location by uniformly placing trunk lines and branch lines in separate layers in wiring within a channel. By introducing an algorithm that allows the trunk layer to be automatically determined and assigned to a track under the conditions specified for each branch layer, the terminal layer and the branch layer connected to it can be specified by the user, making it more user-friendly. Achieve a good automatic wiring system. In addition, by allowing the user to specify the 1- of specific trunk lines such as path line companions and critical paths, the via h of those signal lines can be
By eliminating the ole, it is possible to improve electrical characteristics (elimination of delay variations, etc.).

For example, conventional left t-
If the main line layer is allocated only by the edge method, even if the main line layer is changed in various ways, the main line and the branch lines of other signal lines in the section will be short-circuited and wiring will not be possible. Therefore, in the automatic wiring method according to the present invention, the trunk line processing order is changed and the trunk line layer is appropriately determined, thereby eliminating the slope between the trunk line and the branch line, and wiring becomes possible.

[Effect]

The user can appropriately specify the layer of each terminal (i.e., the layer of the branch line) from among multiple types of layers, and
It becomes possible to extremely reduce the number of a holes.

In addition, by appropriately specifying the layer of a specific trunk line such as a pass line, it is possible to
By wiring in such a way that no a-hole occurs, it is possible to improve electrical characteristics.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure shows the pattern between circuit blocks inside the LSI, Figure 2 is a flowchart explaining the algorithm of the automatic wiring method, Figure 3 is a block diagram showing the configuration of the system that implements automatic wiring, and Figure 4 shows the flow of data. Flow diagram to explain,
FIG. 5 is a flowchart of the automatic wiring method, FIGS. 6 and 7 are examples of patterns according to this method, and FIG. 8 is a pattern diagram in which wiring is not possible, which corresponds to the pattern diagram of FIG.

In the figure, (1) to (5) are storage devices, and (6) is a CP.
U, (7) is block cell pattern information, (3) is wiring information, (9) is LSI pattern data, Q□ is a circuit block Alaη is a circuit block B%@ is a trunk line a% is a trunk line.

0, (g) is the track, 翺 is the wiring channel c,
(21a) is the circuit block C, (ztb) is the circuit block D%, is the wiring channel, (25a) is the first track,
(zsb) is the second track, (26a) is the first column, (2
6b) is the second column, (26C) is the third column, (26d) is the fourth column, (26e) is the fifth column, (26f) is the sixth column, (l
ω) to (110) are strokes. A storage device (1) stores a program for performing the processing shown in the flowchart of FIG. The storage device (2) stores data in which all logical connection information is defined using circuit block names and terminal names. The storage device (3) stores data for each terminal layer. The storage device (4) stores data on the shape and size of blocks, the positions of terminals, and the relative positional relationships of all blocks. Storage device (5)
stores grid-based wiring coordinate data and trunk layer data.

Next, the concept of operation will be explained. When wiring short circuits as shown in FIGS. 10 and 11 occur, wiring can be realized by changing the processing order of the main lines and determining the main line layer as shown in FIG. 1. The second layer is used to determine the layer of this trunk allocation order.
Using the algorithm shown in the figure. According to the left-edge method as in the conventional example shown in FIGS. 10 and 11, trunk line a (
Even if 2) is selected first, the permissible layers All and 41
If All and Al2, which are the cross branch layers of that section, are removed from z (assuming that Poly is prohibited), it becomes empty and cannot be allocated. Therefore, select trunk line b (6) that has the next starting terminal of trunk line a (b), and select All
If All, which is the intersecting branch layer of that section, is removed from and Al2, Al2 remains, and the layer of main line b (4) is assigned to the track as Al2.

Similarly, trunk line a(2) is next assigned to the track one virtual mesh above.

After that, as shown in Figure 4, like normal automatic wiring,
Block cell pattern information (7) in the circuit block,
The wiring information (8) obtained above is synthesized by a computer to obtain actual LSI pattern data (9).

Next, the operation will be explained.

The CPU (6) first reads the program from the storage device (1), and in that procedure, reads the logical information from the storage device (2), each terminal layer information from the storage device (3), and the graphical information from the storage device (4). The logic information, terminal information (including the terminal layer), and graphic information are used as prerequisites, and wiring processing is performed using the program read from the storage device (1), and the wiring is created from the terminal layer of the storage device (3). Using and updating the trunk layer information in the storage device (5), the wiring route and trunk layer are determined and stored in the storage device (5).

Next, the process of wiring the wiring example shown in FIG. 6 will be explained according to the flowchart shown in FIG. The direction in which the wiring should proceed is to the right, ゛, and upward. Here, the tracks are designated as a first track (zsa) and a second track (25b) in order from the bottom, and the columns are designated as a first column (26a), a second column (26bλ...) in order from the left side.
...Set as the 6th column (26f).

Hereinafter, the steps (101) to 1 shown in the flowchart of FIG.
The wiring example in FIG. 6 will be explained using (110).

Step (100): Assuming that Poly is prohibited in the main line layer, the allowable layer of the main line of terminals 31 to 42 is (1, 2), and the allowable layer of the main line of terminals 34 to 39 is (1, 2). (
Here, 1 represents Al1, and 2 represents Al2. )
Step (101): ) Select the rack (25a).

Step (102): Select the first column (2Ba) as the column in which to search for the starting point of the net.

Step (103): Select terminal 31 as an unprocessed terminal.

Step (104): Select the main line from terminal 31 to terminal 42 as CT (processing main line).

Step (105): Since the set of layers obtained by excluding the cross branch layer from the permissible layer of the processing trunk line [CTL) = φ, this processing trunk line is excluded from the processing target for the track, and the process moves to the next terminal.

Step (103): Select the terminal 34 as an unprocessed terminal.

Step (104): As CT, terminal 34 to terminal 39
Select the main line.

Step (105): [From CTLl = [1, 2), select the first layer and make it the main layer. (There are more ``1'' in the branch layer than ``2'', so if the trunk layer is made bi
The reason is that the number of a holes is smaller and the electrical characteristics are improved).

Step (106): There is no unprocessed terminal at the terminal 33°37 corresponding to the lower side of the terminal 34,38.

Step (107): Assignment of the terminals 34 to 39 to the first track (25a) of the main line.

Steps (10B), (103), (109): The first track (25a) is completed.

Step (101): Select the second track (25b).

Step (102): Select the first column (26a) as the column in which to search for the starting point of the net.

Step (103): Select terminal 31 as an unprocessed terminal.

Process (104): As CT, terminal 31 to terminal 42
Select the main line.

Step (105) : : [CTLl = [From 21, select the second layer and make it the main layer.

Step (106): Terminal 41 corresponding to the lower side of terminal 42
There are no unprocessed terminals.

Step (107): Assignment of the terminals 31 to 42 to the second track (25b) of the main line.

Steps (108), (103), (109), (1
10) : Processing is finished.

According to the automatic wiring method that allows specification of the terminal layer, that is, the branch line side, for example, when the pass lines intersect with each other as shown in Figure 8, the main line can also be fixed (specified) in advance. As shown in Figure 7, it is possible for the pass lines to not cross each other.

〔Effect of the invention〕

As described above, according to the present invention, when assigning trunk lines of several nets to tracks, the conventional two-layer automatic control system has control that trunk lines in the same layer do not overlap, and control that branch lines in the same layer do not overlap. In addition to the wiring method, if multiple layers are allowed in the branch line/trunk line layer and the user specifies the branch line layer, trunk line track assignment and This has the effect of performing layer allocation with the aim of minimizing the number of via holes.

Furthermore, by pre-limiting the permissible layer of the main line with path lines, critical paths, etc., the via of those signals can be reduced.
This has the effect of eliminating holes and improving electrical characteristics.

[Brief explanation of drawings]

1 to 7 relate to one embodiment of the present invention, in which FIG. 1 is a pattern diagram between circuit blocks inside an LSI, FIG. 2 is a flowchart explaining the algorithm of the automatic wiring system, and FIG. FIG. 4 is a block diagram showing the configuration of a system that performs automatic wiring, FIG. 4 is a flowchart explaining the flow of data, FIG. 5 is a flowchart of the automatic wiring method, and FIGS. 6 and 7 are pattern diagram examples. FIG. 8 is a pattern diagram that cannot be wired corresponding to the pattern diagram in FIG. 7, FIG. 9 is an inter-block pattern diagram for explaining channel wiring inside a conventional LSI, and FIGS. FIG. 3 is a pattern diagram illustrating a case where channel wiring inside an LSI becomes impossible. In the figure: (1), (2), (3), (4)
, (5) is the storage device, (6) is the CPU, (7) is the block cell pattern information, (8) is the wiring information, and (9) is the L
SI pattern data, αQ is circuit block A% (b) is circuit block A, (6) is main line a, α1 is main line b% Q4
．． Qf9 is a track, 4 is a wiring channel c, (21a)
is the circuit block C, (21b) is the circuit block D, (a) is the wiring channel, (25a) is the first track, (
zsb) is the second track, (26a) is the first column, (26
b) is the second column, (26C) is the third column, (26d) is the fourth column.
column, (26e) is the fifth column, (26f) is the sixth column, (1o
O) ~ (110) C process theal. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (3)

[Claims] (1) Horizontal wiring (
By allocating vertical wiring (called trunk lines) and vertical wiring (called branch lines) to tracks and columns, respectively, a so-called multilayer structure is created in which signal lines (nets) connect circuit block terminals with predetermined layers from among the multilayers. In the channel wiring method, the first process is to obtain a set of permissible layers for each main line from each predetermined terminal layer (branch layer), determine the track to which the main line should be allocated, and apply vertical constraints (branch lines of different signals). Select one unprocessed trunk that satisfies the constraint that comrades do not overlap (hereinafter referred to as the processing trunk), temporarily place it on the track, and select the second processing that satisfies the constraint that comrades do not overlap (constraint that comrades do not overlap). A first determination as to whether there are any remaining layers after removing the branch line layer of the unplaced trunk line that will be processed, and a branch line layer of the processed trunk line for each unplaced trunk line that the branch line will intersect in the future. a third process that performs a second determination as to whether there are any remaining layers in all of them, excluding the allowable layers; and when both the first and second determinations of the third process are positive, the processing main uia with the branch line among the remaining layers in the first determination
In a layer where the number of holes is minimized, it is allocated on a track and goes to the second process, and when the first judgment or the second judgment is negative, the processing trunk cannot be allocated on the track, so it is discarded and the second process is performed. An automatic wiring method consisting of a fourth processing procedure that goes to processing. (2) Claim 1 includes processing for setting the main layer of a specific signal.
2. The automatic wiring method according to claim 1, wherein by placing the method between the first and second processing described above, it is possible to perform partial single-layer wiring without generating a uihole in the net. (3) In the procedure described in claim 1, if a layer allocation impossible solution that negates the first determination or the second determination occurs on any track of a certain main line, the terminal layer of the circuit block is changed as appropriate. (For example, polysilicon (denoted as Poly), first metal layer (denoted as Al_1), second metal layer (denoted as Al_1),
In the case of three-layer wiring (denoted as _2), after changing all the Al_1 terminal layers to Poly or Al_2), the automatic wiring method according to claim 1 is characterized in that 100% wiring is guaranteed by the procedure described in claim 1. .