JPH0226410A - Delay circuit - Google Patents

Abstract

PURPOSE: To restrain the occurrence of data reading error by generating a delay automatically changing following the change of a parameter such as a speed of a tape driving unit. CONSTITUTION: A circuit for introducing time delay into an electric path is a closed loop, and includes an integrator 11 and a comparison state 10 which is connected to a voltage control pulse generator 12. The voltage control generator 12 is equipped with an input line 14 to which a delayed signal is applied and an output 15 connected to a logic circuit component 16, and the output of the logic circuit component 16 is fed back to one of the inputs 17 of the comparison stage 10. Then, the delay obtained by the pulse generator 12 is automatically regulated so as to automatically follow the variation of an input clock cycle such as the pulse signal of an input 18. Thus, even if the parameter like a speed of a tape driving unit changes, automatically changeable time delay is generated. Thus, data is correctly read.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to electrical circuits that introduce time delays into electrical paths.

[Prior Art and its Problems] In electronic circuits, where it is often necessary to delay one or more electrical signals by a certain time interval, a common way in which a zero time delay can be introduced is as follows: This is due to an analog delay line. These delay lines are physically bulky, which can cause problems when used in devices that utilize printed circuit boards, and have relatively poor tolerances, typically on the order of 5%, and some standard Often only values are available. When delaying an analog signal is required, a delay line is usually the only option available. Digital delay can be achieved in one of several ways, including: 1. Combining an analog delay line of the type described above with a logic buffer.

2. Use of monostable elements.

3. Use of high frequency clocks and counters.

Monostable elements are commonly used to provide time delays in digital electronic systems.

The delay provided by a monostable device is typically determined by the resistor and capacitor configuration external to the device. A major problem with such devices is the uncertainty of the actual value of the delay encountered. The delay is a function of resistor and capacitor values in the RC network, temperature and supply voltage, and variations in device parameters. And these differ from element to element. This uncertainty can often be very large and therefore make it unfeasible to use the device in applications that require reasonably accurate delays. A third technique relies on the use of a counter and a high frequency clock to introduce a delay that is a multiple of some fundamental delay. At the beginning of the time delay interval, the counter is loaded and the counter is loaded when the delay ends. This type of configuration requires a moderate amount of hardware and a high frequency clock to implement. However, this technique requires It has the advantage of being able to easily vary the delay in equal steps.The main drawback of the system is that the actual value of the delay generated includes a quantization error corresponding to one period of the high frequency clock, i.e. , IMHz high frequency clocks have the disadvantage that the delays will have a tolerance of 1 microsecond.

An example of a device that requires a time delay is the data separator of a digital tape recording device.
r) There is a circuit. These devices include a phase-locked loop that generates a read reference clock from the read transitions. A zero-phase control loop makes adjustments to the reference clock based on misalignment of the transitions with the edges of the clock signal. It works like this. To facilitate the measurement of this misalignment, the phase control loop incorporates a delay line that is used to provide the fact that a transition may occur after the reference clock edge has passed. In the ideal case, the delay introduced by the delay line should be equal to half the reference clock period; if the device operates under ideal conditions, i.e. the read transitions are at a predetermined constant frequency. If it occurs in
It is common to use a constant delay that produces a nominal delay. What the device essentially does is determine the center of the time window in which data arrives from the tape. If data arrives within that window, it will be decoded without error, but if it arrives outside of that window, a decoding error will occur. Such errors are clearly undesirable.A problem associated with tape drives is that small changes in the operating speed of the drive affect the size of the decoding time window.For example, if the drive is fast In operation, the window will shrink to just below its nominal value. Therefore, if the chosen delay is 12
When optimized for drives running at 0 inches,
If the same drive unit operates 1% slower, it will not be optimal (
This can lead to errors.

OBJECTIVE OF THE INVENTION 1 The present invention is to provide a circuit capable of generating a delay that can be automatically varied to follow changes in parameters such as the speed of a tape drive.

[Summary of the Invention] According to the present invention, an electrical circuit is provided which generates a time delay in the electrical circuit, and which, after an edge or transition is applied to the input thereof, at a predetermined time interval, It is designed to generate edges or transitions from the output,
a pulse generator further comprising a control input for applying a signal for varying said time interval; means for generating an electrical signal representative of said time interval; and receiving said signal and another signal representative of a reference time interval. and a comparator circuit for generating an error signal applied to the control input of the pulse generator to maintain the time interval in a predetermined relationship with respect to the reference time interval.

The pulse generator may be a voltage controlled pulse generator and the error signal may be a voltage signal.

A voltage-controlled pulse generator can be constructed of monostable elements with an associated RC network. The reference signal can be derived from a clock signal, the period of which varies according to some external parameter, such as the speed of the tape drive.

[Embodiment] FIG. 1 is a block diagram of a delay circuit according to an embodiment of the present invention. Referring to FIG. 1, a circuit for introducing a time delay into an electrical path includes an integrator 11 and a comparator stage 10 connected to a voltage-controlled pulse generator 12. Referring to FIG. The voltage-controlled generator 12 is provided with an input line 14, to which the signal to be delayed is applied, and an output 15, which is connected to a logic circuit element indicated at 16. Logic circuit element 1
The output of 6 is fed back to one input 17 of comparison stage 10. Comparison stage 10 has a second input 18;
A signal representing the time period to which the output of the delay circuit is to be referenced is applied to. This signal can, for example, be derived from a clock signal and represents the period of the clock signal.

The input 17 signal sent from the logic circuit element 16 is
It represents the time delay caused by circuit 12.

Comparison stage 10 consists of a differential integrator receiving two pulse inputs on lines 17 and 18.

One pulse has a width that corresponds to the period of the input clock, and the other pulse has a width that corresponds to the period of the delay generated by circuit 12. This integrator integrates both pulses and integrates the pulse on line 18 and line 17.
Compare with the integral of the pulse at . The output of the integrator is
It is therefore a function of the difference in pulse width between the two inputs on lines 18 and 17. The output from the differential integrator is a voltage signal that is sent to voltage controlled pulse generator 12. This can be constructed with simple monostable elements, and the time delay introduced into the signal path on line 14 by the output from the differential integrator reduces the error between inputs 17 and 18. controlled in such a way.

Increasing the input voltage to this element will reduce the resulting delay, and reducing the input voltage to this element will increase the resulting delay.

This is because the element has a threshold value, and as the input voltage increases, the time it takes to reach this threshold value becomes shorter. Therefore, the circuit shown in FIG.
Closed loop, the delay provided by pulse generator 12 is automatically adjusted to automatically track variations in the input clock period as represented by the pulse signal at input 18. The circuit needs to introduce a time delay related to some speed that may change over time, and the time delay needs to be adjusted to follow that speed change, or can be used when a high constant delay is required.

An example of such a need is digital tape devices. In such devices, data is recorded on tape in MFM format, and the read circuitry of such devices uses a phase-locked loop to generate read references from read transitions. In Figure 3, waveform A
The read signal (changes in magnetic flux occurring in the media) is shown in Figure 2. The zero-phase control loop converts the read signal (the change in magnetic flux occurring in the medium) into an edge as shown in waveform B (coinciding with the peak of signal A) by transitions and clock edges. It operates by making adjustments to the reference clock according to misalignment with the reference clock.

To facilitate the measurement of misalignment, a delay line is incorporated into the phase control loop, the purpose of which is to provide the fact that the transition arrives after the reference clock edge has passed. The delayed signal is shown in waveform C in Figure 3, and the voltage controlled oscillator clock signal with period T is shown in waveform C.
The measured time difference between the delayed edge of C and the trailing edge of clock D is used to adjust the edge position of the subsequently arriving waveform to align the delayed signal C with the trailing edge of the CO clock signal. It should be noted that FIG. 3 shows the optimum alignment between the edges of waveforms C and D.

The temporal location at which the transition occurs will determine whether the decoding circuit interprets it as a logic "1" or a logic "O". For a transition to be accurately decoded, it must occur within a certain time slot. Since we are using MFM decoding techniques, transitions from the tape must occur during the high logic state of the clock. If it arrives, it is decoded as "l".

This time slot is determined by the trailing edge of the vCO signal. Figure 3 shows that if the delay Td is equal to half the vCO period T (i.e., half the gap from trailing edge to trailing edge), then the read transition will be exactly halfway between the trailing edges of the CO signal. It shows that it will become. In addition, the third
In the figure, the rise of signal B does not coincide with the midpoint, but in the above state it comes to the midpoint. This is ideal as it allows the read signal to shift by an equally large amount T/2 to the left or right without introducing errors, as seen in Figure 3. be. The shift is actually caused by electrical noise and other factors, so T should be equal to T/2.
Setting d provides maximum margin for dealing with noise, which minimizes the possibility of error.

Traditionally, fixed delay times have been used in phase-controlled loops. This can cause problems because the delay is not always equal to T/2. For example, the CO signal may be It is subject to fluctuations, which reduces the margin of error. These problems can be overcome by using a circuit according to the invention, as shown in FIG.

FIG. 2 is a block diagram of a delay device according to one embodiment of the present invention that can be used in a tape drive. Referring to FIG. 2, there is shown a circuit that constitutes a tracking delay line configuration for use in such a tape device. A comparison or differential integrator stage is shown at 110 and is provided with two inputs 17 and 18. Input 17 is a pulse obtained from the output of circuit 112 by circuit element 116, and input on line 18 is a pulse signal whose width represents the period T/2 shown in FIG. 3D. The output of stage 110 is a voltage signal representing the difference between the two pulse forces 17 and 18, which can be used to convert monostable circuit 1 in the manner described above.
Control will be applied to the delay caused by 12. Monostable circuit 112 receives the signal to be delayed from line 123 at power 122 . The output from monostable circuit 112 is sent to another circuit 125 which generates a signal through gate 126 representing the time delay introduced by monostable circuit 112, which in turn is sent to input 17. It will be done. Therefore, the circuit is a monostable circuit 11
By comparing the time delay introduced at the output of 2 with the half period of the clock by the voltage controlled oscillator as represented by the pulse signal on input line 18,
Operate. In practice, a finite amount of time is required to reduce the error between the input period and the output delay, and this is called the settling time (7tring time). Once the device has settled, the output delay will accurately reflect the input period of the lock signal as shown at input 18. The typical delay introduced by the monostable circuit 112 is 200 ts, and the error can be less than igs, or better than 0.5%. This is better than 5% when using conventional analog delay lines.

If the settling time is short compared to the rate at which the input clock changes due to variations in tape drive speed, the system will be unable to follow changes in the input clock period without much error. It is possible; therefore, the time delay output will follow the change in drive speed, producing an optimal time delay under all conditions.

In FIG. 4, a circuit for generating the pulse signal at input 18 is shown. This circuit receives a signal on line 5 with twice the frequency of the voltage-controlled oscillator clock signal.
0, the circuit serves to send a pulse on output line 57 with a width equal to the clock period. It should be noted that the circuit shown in FIG. 4 has one more input, indicated at 52. This additional input receives the Q output from circuit 125 and is used to indicate the end of the delay generator pulse.

Another advantage provided by the circuit of FIG. 2 lies in the fact that a digital tape device may need to read two types of tape written at slightly different speeds. Changing the data rate
The size of the decoding window changes. By using an arrangement of the type shown in FIG. 2, the delay will be automatically optimized for the relevant data rate.

Of course, the delay circuit can also be applied to devices other than tape drives. For example, it can be used to implement a highly accurate delay system by adding various frequency clocks to the input of a control system. Additionally, miniaturized hybrid configurations may find use in replacing the fixed delay lines used in many digital applications.

[Effects of the Invention] As is clear from the above description, according to the present invention, even if a parameter such as the speed of the tape drive changes, a time delay that can automatically change can be generated;
For example, accurate reading of data can be realized.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a delay circuit according to an embodiment of the present invention, FIG. 2 is a detailed block diagram of a delay circuit according to an embodiment of the present invention that can be used in a tape drive, and FIG. 3 is a decoder for a digital tape drive. FIG. 4 is a circuit diagram for generating one input signal of the circuit of FIG. 2. FIG. 10: Comparison means 12: Monostable circuit (voltage controlled pulse generator)

Claims (1)

[Claims] a pulse generator for generating a transition at an output at a time interval after a transition of an input signal, said time interval being varied by an applied control signal; means for generating a signal representative of said time interval; and a variable reference. a signal source for generating a signal representative of a time interval; means for generating an error signal related to a difference between the time interval and the reference time interval; and providing the error signal as the control signal to the pulse generator. and a delay circuit comprising means.