JPH02260051A - Commodity identification system - Google Patents

Abstract

PURPOSE:To prevent the outsiders from giving accesses to a memory and reading/changing the contents of the memory by writing the secret data into a secret setting area by the memory in order to define a specific area of the memory as a secret area. CONSTITUTION:The secret data is written into a memory 1 of a data carrier 4 via a secret designating means 7a of a write/read unit 6 and a prescribed area of the memory 1 is defined as a secret area. Hereafter it is discriminated whether a secret area is designated or not for each access. If so, it is inhibited to write the new data into the secret area nor to read the data out of the secret area. Thus it is possible to designate a specific area of the memory 1 as a secret data area and to inhibit the accesses to the secret area even with a normal memory access instruction. As a result, the secret can be held.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to an identification system for tools for machine tools, parts in factories, products used in product management, distribution systems, and the like.

[Conventional technology]

In order to mechanize the tool management of conventional machine tools and the identification of parts and products on assembly lines in factories, tools 1
A system is needed to identify and manage various items such as parts and products. Therefore, as disclosed in Japanese Patent Application Laid-Open No. 63-221950, a memory unit having a memory is provided in the object to be identified, and necessary information is written in such memory by data transmission from the outside, and the information is transferred as needed. An article identification system has been proposed that reads out.

[Problem to be solved by the invention]

However, according to such conventional identification systems,
All of the data can be read by providing predetermined commands to the write/read control unit to access the memory holding the data. However, depending on the type of use, a function may be required that allows a third party to freely read a predetermined portion of the memory or prohibit data from being changed.

The present invention has been made in view of the problems of the conventional article identification system, and it is an object of the present invention to prohibit third parties from accessing a predetermined area of a memory unit so that the contents thereof cannot be read or changed. is a technical issue.

[Means for Solving the Problems] As shown in FIG. 1, the present invention comprises a memory 1 for holding data, a memory control means 2 for controlling writing and reading of data into the memory, and a command given from the outside. a data carrier 4 attached to an article to be identified; and a data carrier 4 that transmits data to the data carrier and sends out the data. an article identification system comprising a write/read control unit 6 having a data transmission means 5 for receiving data, the write/read control unit is configured to set a specific area of the memory of the data carrier as a secret area. secret specifying means 7a for writing the address and secret number into the secret setting area of the memory; secret specifying means 7a for changing the secret data in the secret area once written; fiI area changing means 7b; and clearing all data in the memory of the data carrier. The data carrier or write/read control unit performs memory access to read the secret data in the secret setting area and access areas other than the secret area when accessing the memory of the data carrier. It is characterized by having means 7d.

[Effect]

According to the present invention having such features, once secret data is written in the memory of the data carrier by the secret designating means and a predetermined area of the memory is set as the secret area, the data is designated as the secret area every time the data carrier is accessed. If the area is a secret area, new data cannot be written to or read from the area. Furthermore, since the memory cannot be accessed if the secret code is lost, an all-clear means for clearing all data in the memory is provided.

〔Effect of the invention〕

Therefore, according to the present invention, a specific area of each data memory can be set as a secret data area, and since the secret area cannot be accessed even by using a normal memory access command, secrecy can be maintained. Therefore, important data can be written on the data carrier, and the advantage is that it can be used together with articles in manufacturing processes and the like.

[Explanation of Examples]

FIG. 2 is a block diagram showing the structure of an article identification system according to an embodiment of the present invention.
A data carrier 12 that is directly attached to the data carrier 12, a read/write head (hereinafter referred to as RW head) 13 that writes and reads data to and from the data carrier 12, and an RW head 13.
ID controller 14 that is connected to and controls its operation.
is provided. RW head 13 and ID controller 1
4 constitutes a write/read control unit 6. Also ID
The controller 14 is connected to a host computer 15.

Now, as shown in the block diagram in FIG. 3, the ID controller 14 includes a microprocessor (CPU) 21 that controls writing and reading of data to and from the data carrier 12, and a memory 22 that holds the system program and data.
An input/output interface 23 for inputting and outputting father values to and from the computer 15 is provided. CPU2
An encoding circuit 24 and a decoding circuit 25 for encoding data to be transmitted to the data carrier 12 are connected to the input/output terminal of the data carrier 12. Now, the RW head 13 has a modulation circuit 26 that modulates the output of the encoding circuit 24, and a transmitter 27 driven by the output.

The transmitter 27 transmits data to the data carrier by outputting, for example, an FSK-modulated signal from a coil. Further, the received signal obtained from the data carrier is given to the demodulation circuit 29 via the receiving section 28. The demodulation circuit 29 demodulates this signal and provides it to the decoding circuit 25.

Next, the configuration of the data carrier 12 will be explained with reference to FIG. 4. In FIG. 4, a transmitting/receiving section 31 receives and transmits a frequency signal emitted from the RW head 13, and its received output is given to a demodulation circuit 32. The demodulation circuit 32 demodulates this signal and provides its output to the decoding circuit 33. The decoding circuit 33 decodes the encoded data into an original signal and provides it to the control section 34. The control unit 34 is connected to a memory 35 via a bus, for example, a memory 35 composed of a static RAM or an E"PROM backed up by a battery 36. The control unit 34 receives commands and data given from the ID controller 14. The read data is converted into a serial signal and given to the encoding circuit 37.The encoding circuit 37 is the memory control means 2 that controls writing or reading of data according to the encoding circuit 24 of the ID controller 14. It encodes a given signal in the same way as in the conventional example, and its output is given to the transmitting/receiving section 31 via the modulation circuit 38. RW signal by
This is given to the Hefd 13 side. Here, the transmitting/receiving section 31
．． The demodulation circuit 32 and the modulation circuit 38 constitute a data transmission means 3 that demodulates commands and data given from the ID controller and supplies them to the memory control means, and transmits the read data.

Next, the memory map of the data carrier of this embodiment will be explained with reference to FIG. The memory 35 of the data carrier has a secret setting area 35a as shown in FIG.
is provided. The secret setting area 35a includes a flag area indicating whether or not a secret is specified, a secret number area,
It consists of an area in which the start and end addresses of the secret are written. The area surrounded by the secret start and end addresses is the secret area 3 of the memory.
It is 5b.

Next, the operation of this embodiment will be explained with reference to a flowchart. FIG. 6 is a flowchart showing the operation of the ID controller 14. When the operation starts in this figure, a command from the host computer 15 is first awaited. If the command is received, the process advances to step 42 to check whether it is a secret designation command. If it is a secret designation command, the process advances to step 43 to read the secret setting area 35a of the memory 35, and if there is no communication error, the process advances to step 45 to check whether the secret designation flag has already been set. If the secret has already been specified, proceed to step 46 and send the secret specified response to the host computer 15.
, and end the process. If the secret is not specified, the process proceeds to step 47, sets the secret flag, and stores the secret number and the start and end addresses of the secret area in the memory 35 of the data carrier 12.
Write as shown. The process then proceeds to step 48 to check whether there is a communication error, and if there is no communication error, a secret designation completion response is sent (step 49) and the process ends. If there is a communication error, the process proceeds to step 50, where a communication error response is sent and the process is terminated. Here, CPU2i performs steps 42 to 45.
In this, the function of the secret designating means 7a is achieved, which makes a specific area of the memory of the data carrier 12 a secret area.

Now, if it is determined in step 42 that it is not a secret designation command, the process proceeds to step 51 to check whether it is a secret setting area change command.

In addition to the current secret number, this command includes a new secret number and the start and end addresses of the secret area.
Step 2 reads the secret setting area 35a. If there is no communication error, a check is made in step 54 to see if a secret designation has already been made. If there is no secret designation (1), the process proceeds to step 55, where a response with no secret designation is sent to the host computer 15 and the process ends. If secret is specified, step 5
In step 6, it is checked whether the secret numbers match, and if they do not match, a secret number mismatch response is sent (step 57) and the process ends. If the secret numbers match, proceed to step 58, change the data in the secret setting area of the data carrier 12, such as the secret number and the address of the secret area,
Check for communication errors. If there is no communication error, a secret area change completion response is sent in step 60, and the process ends. If there is a communication error, the process advances to step 50 and a communication error response is sent. Here, the CPU 21 achieves the function of the secret area changing means 7b that changes the secret data in the secret setting area in steps 51 to 60.

Now, in step 51, if it is not a secret setting area change command, the process advances to step 61 and checks whether it is a read or write command.

If it is a read or write command, the process advances to step 62 to read the secret setting area from the data carrier 12, and if there is no communication error, the process proceeds to step 64 to check whether it is a read or write command for the secret area 35b. If it is a read or write command to a secret area, the process proceeds to step 64 to prohibit read/write to this area, sends a response with secret designation to the host computer, and ends the process. If it is not the read/write to the secret area 35b, the process proceeds to step 66, executes the read or write command,
If there is no communication error, a read or write response is sent to the host computer (step 68) and the process ends. Here, in steps 61 to 65, the CPU 21 achieves the function of the memory access means 7d which reads the secret data in the secret setting area and accesses areas other than the secret area when accessing the memory of the data carrier.

Furthermore, if it is not a read/write command in step 61, the process advances to step 69 to check whether it is a clear all command. If this command is not used, step 7
Sends a command error at 0. If it is a clear all command, proceed to step 71 and send a clear all command to the data carrier to clear all data in the data carrier's memory, and if there is no communication error, send a data carrier memory clear completion response. (Step 73), the process ends. Here CP
U21 is a clear all means 7C that clears all data in the memory of the data carrier in steps 69 to 73.
It consists of

As described above, in the present invention, a predetermined area of the memory of a data carrier is set as a secret area, and access to the area is prohibited to protect data in the memory. When accessing the secret area, the secret area should be first cleared by setting the secret data or changing its address using the secret area changing means, and then the original secret area should be accessed by a normal read or write command. .

In this embodiment, the CPU 21 of the ID controller 14 determines whether or not it is a secret area at the time of reading or writing, and if it is this area, memory access is prohibited, but this memory access function may be provided in the data carrier itself. It is also possible to

In addition, in order to avoid abuse in which the secret number is found by repeating secret number mismatch errors, an error counter is incremented when a secret number mismatch error occurs, and when the counter reaches a predetermined value, the secret area change command is executed. It is also possible to prohibit its use.

[Brief explanation of drawings]

Figure 1 is a functional block diagram showing the overall configuration of the present invention, Figure 2 is a functional block diagram showing the overall configuration of the present invention.
The figure is a perspective view showing the overall structure of the article identification system, FIG. 3 is a block diagram showing the structure of the ID controller, FIG. 4 is a block diagram showing the structure of the data carrier, and FIG. 5 is the memory structure of the data carrier. 6 are flowcharts showing the operation of the ID controller. 7a...-Secret designation means 7b-...-
-Secret area changing means 7C...-Clear all means 7cl-...-Memory access means 13--Read/write head 14--
...-ID controller 15--Host computer 21--CPU 34--
-Control unit patent applicant Tateishi Electric Co., Ltd. agent Patent attorney Yoshiki Okamoto (and 1 other person) 1.35-----1--Memory 2...----
・Memory control means 3.5...-data transmission means 4
, 12・−・・Data carrier 6・・・・−・
・・Write/read control unit Fig. 1 Fig. 2 4 ------- Game A Yari completed 6 ------- @Include/1 and L outside I Ugami knit Fig Fig Fig

Claims (1)

[Claims] (1) A memory that holds data, a memory control means that controls writing and reading of data to the memory, demodulating commands and data given from the outside, and transmitting the read data to the memory control means. a data carrier that is attached to an article to be identified, and a write/read control unit that has a data transmission means that transmits data to the data carrier and receives the transmitted data. an article identification system, wherein the write/read control unit includes secret designating means for writing an address and a secret number into a secret setting area of the memory in order to make a specific area of the memory of the data carrier a secret area; It has a secret area changing means for changing the secret data in the secret area once written, and a clear all means for clearing all the data in the memory of the data carrier, and the data carrier or write/read control. An article identification system characterized in that the unit has memory access means for reading the secret data in the secret setting area and accessing areas other than the secret area when accessing the memory of the data carrier.