JPH0225955A - Single chip microcomputer - Google Patents

Abstract

PURPOSE:To improve the data transmission efficiency with a single chip microcomputer by setting a transmission error detecting circuit into a serial interface to detect the errors at transmission of data. CONSTITUTION:A transmission error detecting circuit 15 consisting of an exclusive OR gate (EOR gate) 92 and an AND gate 93 is added to a serial interface 9. At transmission of the serial data, a control circuit 91 sets a transmission mode signal 124 at 1 and therefore the output of the gate 92 is set at 1 only when no coincidence is obtained between a level set on a transmission line and the output of a shift register 122, i.e., at a transmission error. Therefore the output of the gate 93 is set at 1 at a transmission error only for a period when an output pulse 129 of a Baud rate generator BRG123 is kept at 1. Thus a transmission error signal 94 is set at 1 and sent to a CPU. As a result, a transmission error is detected in real time and the CPU performs the error processing at an early stage. Then the data transmission efficiency is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a single-chip microcomputer that integrates computer functions and a serial interface on a single semiconductor substrate.

[Conventional technology]

In recent years, advances in LSI manufacturing technology have led to higher integration in the field of single-chip microcomputers (hereinafter referred to as single-chip microcomputers), and the cost per unit function has also decreased significantly. with this,
The fields of use of single-chip microcontrollers are expanding, and they are used in various control fields. At this time, there are many single-chip microcomputers equipped with serial interfaces for transmitting and receiving data with other LSIs, and they are used in various fields. For example, a single-chip microcomputer used in an IC card uses an asynchronous serial interface to collectively transmit and receive several tens of bytes of data.

Figure 4 is a diagram of a conventional single-chip microcomputer. First, the constituent elements will be explained.

In FIG. 4, program counter 1 is a pointer with an increment function that points to an instruction storage address.

A read-only memory 2 (hereinafter referred to as ROM) is used to store user programs. The address/data bus 3 is a bus that transfers addresses and data in a time-division manner. Instruction register 4 stores the instruction read from ROMz at address/
This is a register that stores data via the data bus 3. The control section 5 outputs a control signal according to the contents stored in the instruction register 4, and executes an instruction function by operating each section. The arithmetic unit 6 performs arithmetic operations on input data via the address/data bus 3 and outputs the results to the address/data bus 3. Readable and writable memory 7 (
RAM (hereinafter referred to as RAM) is used for data storage in data processing. The general-purpose register 71 is a readable and writable register used for storing various processing data.
It is mapped to AM7.

The control unit 5 outputs a control signal and controls the designated general-purpose register 7.
The stored data of 1 is output to the address/data bus 3, or the data transferred via the address/data bus 3 is stored in the designated general-purpose register 71. Interrupt control unit 8
causes the CPU to execute interrupt processing in accordance with the interrupt request signal 15.

Program counter 1. Instruction register 4. Control unit 5. General purpose register 71. A block including the calculation unit 6 constitutes a central processing unit (hereinafter referred to as CPU).

The serial interface 12 outputs the parallel data input via the address/data bus 3 via an external terminal 10, or after receiving the serial data t input via the external terminal 10, outputs the parallel data input via the address/data bus 3. After conversion, it is output to the address/data bus 3.

The operation will be explained using the above components.

RO the instruction at the address specified by program counter 1.
Read from M2 and store in instruction register 4 via address/data bus 3. The control unit 5 includes an instruction register 4
After decoding the instructions stored in the controller, it generates control signals and operates each part to execute the instruction function. When the instruction execution is completed, 1 is added to the contents of the program counter 1, and a new instruction is stored in the instruction register 4 and then executed. By repeating the above operations, the programs stored in the OM2 are executed one after another.

Next, the configuration of the serial interface 12 will be explained based on FIG.

The serial interface 12 is a so-called UART (Universal As-y
chronous Receiver Transm
itter ) and a mode register 126 .itter that specifies the operating mode. A buffer 121 that holds transmission data input via the address/data bus 3 or reception data stored in the shift register 122. Shift register 122 for storing transmitted and received data. Baud rate generator 123 (hereinafter referred to as BRG) that specifies the sending and receiving baud rate
, a control circuit 125 that controls each of the above hardware, a 3-state buffer yL27 that is turned on when the transmission mode signal 124 is 1, and a 3-state buffer yL27 that is turned on when the transmission mode signal 124 is 0.
It consists of a state buffer 128.

The operation when transmitting serial data will be explained. The CPU writes data to the mode register 126.

When transmission data is written to the buffer 121 after setting the transmission mode, the control circuit 125 sets the transmission mode signal 124 to 1, turns on the 3-stage amplifier 127, and outputs the output of the shift register 122 to the external terminal 10. In addition, after the data stored in the buffer 7121 is loaded into the shift register 1220-, the data is shifted out in synchronization with the falling edge of the BRG output pulse 129 output from the BRIG 123, so that the data can be serially transferred to the shift register 1220- through the external terminal 1o. Output to outside. At this time, the control circuit 125 adds a start bit, parity bit, and stop bit.

The operation when receiving serial data will be explained. When the CPU writes data to the mode register 126 to set the reception mode, the control circuit 125 sets the transmission mode signal 124 to O.
Then, the 3-state buffer 128 is turned on. When a start bit is detected at the external terminal IO, the control circuit 125 shifts the input data into the shift register 122 via the external terminal 10 in synchronization with the rise of the BRG output pulse 129 output from the BRG 123. After receiving the data, the data is transferred to the buffer 121 in preparation for receiving the next data. The CPU receives the received data by reading the data stored in the buffer 121. At this time, the control circuit 125 checks the parity bit and stop bit of the received data.

FIG. 6 shows timing during serial data transmission. The data length is 8 bits. As shown in FIG. 6, data is transmitted serially in the order of start bit S+8-bit data d+validity bit, bit P+stop bit e. The transmission mode signal 124 becomes 1 only during data transmission. Further, the B-box G123 outputs a BRG output pulse 129.

Now, let's consider sending a large amount of data, several tens to hundreds of bytes, all at once. For example, in an IC card, a serial interface is used to transfer data of several tens of bytes. Suppose that a transmission error occurs at this time. Transmission errors are detected on the receiving side by checking the start bit, parity bit, and stop bit, and by checking an error check code that is usually added to the end of a large amount of transmitted data. Here, the above error check is performed only on the receiving side, and the transmitting side detects a transmission error in the transmission from the receiving side after all data has been transmitted.

Therefore, since the transmission process 2- cannot be detected until the end of the transmission of a large amount of data, the overflow is large. For example, 1
00 bytes of data to 9600BP8 (BIT P
Suppose that a transmission error occurs during batch transmission at a baud rate of ER5ECOND). If an error occurs when transmitting the first byte, the time from the occurrence of a transmission error to the detection of a transmission error on the data sending side is l÷9600 x 1
It takes 1 x 100 = 110m5. On the other hand, if data is transmitted multiple times after dividing the transfer data, the transmission efficiency will decrease.

[Problem to be solved by the invention]

As mentioned above, in conventional single-chip microcomputers, it is not possible to detect transmission errors on the sending side when transmitting large amounts of data all at once using a serial interface, so if a transmission error occurs during large data transmission, all the data is Perform error handling after sending.

Therefore, there was a drawback that the transmission efficiency was significantly reduced.

The above-mentioned conventional single-chip microcomputers have the drawback that transmission errors that occur during data transmission through the serial interface cannot be detected on the transmitting side, and transmission error processing is performed after all data has been transmitted, resulting in a decrease in transmission efficiency. However, the single-chip microcontroller according to the present invention has a built-in transmission error detection circuit, so that it is possible to detect transmission errors that occur during transmission on the data sending side, and to immediately start transmission error processing. Therefore, the difference is that the transmission efficiency is extremely high.

[Means to solve the problem]

The present invention provides a single-chip microcomputer in which a central processing unit and a serial interface are integrated on a single semiconductor substrate. It is characterized by detecting errors.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 shows the configuration of a first embodiment of a single-chip microcomputer according to the present invention. When a transmission error occurs during data transmission by the serial interface 9, a transmission error detection signal 94 is output from the serial interface 9,
This differs from the conventional single-chip microcomputer shown in FIG. 4 in that the CPU performs transmission error processing via the interrupt control section 6.

The configuration of the serial interface 9 is shown in FIG. 2 and its operation will be explained below. The serial interface 9 has an exclusive OR gate 92 (hereinafter referred to as an EOR gate) and an AND gate 93 (hereinafter referred to as an A
This is a configuration in which a transmission circuit 2 and a detection circuit 15, each consisting of a transmission circuit (referred to as an ND gate), are added.

The configuration and operation of the transmission error detection circuit 15 will be explained below.

The transmission error detection circuit 15 is connected to the EOR gate 92 and the AND
It consists of a gate 93. EOR gate 920 inputs are the output of 3-state output buffer 127 and shift register 1.
22, and the output of the EOR gate 92 becomes 0 only when the two match (only during normal transmission). AND gate 93 determines whether transmission mode signal 124 is 1. EOR gate 9
The output is set to 1 only when the output of 2 is 1 and the BRG output pulse 126 is 1.

When transmitting serial data, the control circuit 91 sets the transmission mode signal 124 to 1, so the output of the EOR gate 92 becomes 1 only when the level on the transmission line and the output of the shift register 122 do not match (only in the case of a transmission error). . Therefore, in the case of a transmission error, the period AN of the BRG output output bulk 129
The output of the D gate 93 becomes 1, and the transmission error signal 94 becomes 1.
shall be.

If no transmission error occurs, the output of the EOR gate 92 is 0, and the output of the fiAND gate 93 is 0°.Therefore, the transmission error signal 94 is 0.

When receiving serial data, the control circuit 91 sets the transmission mode signal 124 to 0, so the output of the AND gate 93 becomes 0 and the transmission error signal 124 becomes O. Therefore, the period transmission error signal 94 of the BRG output output bulk 129 becomes 1 only when a transmission error occurs during data transmission. Therefore, by detecting transmission errors that occur during bulk transmission of large amounts of data in real time and outputting the transmission error signal 94, the CPU can quickly perform error processing, thereby improving transmission efficiency.

For example, 100 bytes of data is 96008 P 5 (
Suppose that a transmission error occurs during batch transmission at a baud rate of BIT PE 5 ECOND). ζ If an error occurs during transmission of the first byte, the transmission error is detected during transmission of the first byte and transmission error processing is immediately performed. Therefore, conventionally it took 110ms from the occurrence of a transmission error until the transmission error was detected on the data sending side, but with the single-chip microcontroller according to this embodiment, a transmission error can be detected in the required time of 1÷9600÷2=52μs. 〇Detection is possible.

Next, a second embodiment of the single-chip microcomputer according to the present invention will be described.

In the single-chip microcomputer of the second embodiment of the present invention, the transmission error detection circuit built into the serial interface is equipped with latch circuits 1 and 2, and the latch circuit is set when a transmission error is detected, and the CPU latches. This differs from the single-chip microcomputer according to the first embodiment in that the occurrence of a transmission error is detected by checking the contents of the circuit.

The serial interface of the second embodiment of the present invention will be described below with reference to FIG. Second related to the present invention
In the single-chip microcontroller of the embodiment, the transmission error detection circuit 1 built in the serial interface 13
4, EOR gate 131, AND gate 132. It consists of a latch circuit 133. The reset signal 135 is C
This is a signal output when the PU writes to a specific address, and resets the latch circuit 133.

The latch circuit 133 latches the output of the AND gate 132 in synchronization with the BRG output bulk 129 output from the BRG 126 and outputs it to the control circuit 134 . The latch circuit 133 is memory mapped, and the CP
U reads the stored data by reading from the map address. EOR gate 131 outputs 0 only when the output value of shift register 122 and the output value of 3-state buffer 127 match. AND Kate 132 is E
The output is set to 1 only when the output of the OR gate 131 and the transmission mode signal 135 are both 1.

Hereinafter, it is assumed that the latch circuit 133 is set and set in advance by the CPU.

Consider when transmitting serial data. During serial data transmission, the control circuit 134 sets the transmission mode signal 124 to 1 and 3.
Turn on state buffer 7127.

The shift register 131 receives the B generated by the BRIG123.
The lower RG output output bulk 129 shifts out the stored data in synchronization with the 9th edge. At this time, shift register 1
When the output of the EOR gate 131 is different from the output of the 3-stage amplifier 127, the output of the EOR gate 131 becomes 1. Therefore, AN
D game) 132 output is 1, and the silatch circuit 133 is B
1 which is the output of the AND gate 132 in synchronization with the edge of the BRG output output bulk 129 outputted by the RG123.
Store. Finally, if a transmission error occurs during data transmission, the latch circuit 133 stores 1.

Consider when receiving serial data. At this time, the control circuit 13
4 sets the transmission mode signal 124 to 0, so the output of the AND gate 132 becomes O, and the output of the latch circuit 133 becomes O.
It remains as it is.

Therefore, by resetting the latch circuit 133 before transmitting data and checking the contents of the latch circuit during bulk data transmission, the CPU can know whether a transmission error has occurred up to that time.

When a transmission error is detected, the CPU immediately performs transmission error processing. Therefore, when sending bulk data, the CP
By checking the contents of the latch circuit 133 at regular time intervals, U can detect transmission errors that occur during data transmission at an early stage, and can quickly handle errors, thereby improving transmission efficiency. .

As mentioned above, by adding a simple hardware circuit, it is possible to detect transmission errors during data transmission and perform transmission error processing at an early stage, making it possible to improve serial data transmission efficiency. .

〔Effect of the invention〕

As explained above, in the present invention, by adding a simple transmission error detection circuit to the serial interface, it is possible for the transmitting side to detect transmission errors during data transmission. , it is possible to perform error processing at an early stage, which has the effect of improving transmission efficiency.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the first embodiment of the present invention, and FIG. 2 is a professional diagram of the serial interface 9 shown in FIG.
FIG. 3 is a schematic diagram of the serial interface 13 in the second embodiment of the present invention, FIG. 4 is a block diagram of a conventional single-chip microcomputer, and FIG. 5 is a diagram of the serial interface 12 shown in FIG. The block diagram in FIG. 6 shows the timing of data transfer by the serial interface 12 of the conventional single-chip microcomputer shown in FIG. 1...Program counter, 2...R
OM, 3...Address/data bus, 4...
...Instruction register, 5...Control unit, 6...
...Arithmetic unit, 7...RAM, 71...
・General-purpose register, 8...Interrupt control unit, 9...
... Serial interface, 91 ... Control circuit, 92 ... EOR gate, 93 ...
...AND gate, 94...Transmission error signal,
10... External terminal, 12... Serial interface, 121... Buffer, 122
...Shift register, 123...BR
G. 124...° transmission mode signal, 125 pa...
Control circuit, 126...Mode register, 127
°゛゛°°3 state buffer, 128...3
State buffer, 129...BRG output pulse, 13...Serial interface, 131
- Old: EO gate, 132: OR gate, 134: control circuit, 133: latch circuit, 135: reset signal. Agent Patent Attorney Uchihara Oto rJ3 Old Ga 5th BKlq Degari Harus 1st

Claims (1)

[Claims] In a single-chip microcomputer in which a central processing unit and a serial interface are integrated on a single semiconductor substrate, the serial interface has a built-in transmission error detection circuit, and the transmission error detection circuit detects transmission errors during data transmission. A single-chip microcomputer characterized by: