JPH0225837A - Distribution coupling type optical switch and its manufacture - Google Patents

Abstract

PURPOSE:To set a short switch length by executing a switching action in controlling it with a field effect transistor structure. CONSTITUTION:First and second light guide routes 34a and 34b are provided in parallel to a light guide direction on a lower side clad layer 32, and first and second main electrode areas 42a and 42b to compose the field effect transistor and a gate channel area 40c between them are provided on the upper sides of the first and second light guide routes 34a and 34b. Consequently, for example, the first main electrode area 42a on the first light guide route 34a is made into a drain area, the second main electrode area 42b on the second light guide route 34b is made into a source area, and the field effect transistor can be composed. By providing such a field effect transistor structure to control the switching action of a light output, the driving voltage of a driving circuit can be made small, and the short switch length can be set.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a distributed coupling type (directional coupler type) optical switch using a semiconductor waveguide and a method for manufacturing the same.

(Prior Art) This type of distributed coupling type optical switch is mainly used as an optical switch for optical exchangers. As an example of this optical switch, for example, Bunyu:rMIC日○0PTIC8NEWS (
Micro Optics News) Vol, s, No, 4
(November 24, 1987), pp. 32-37, discloses an optical switch having a lip waveguide structure with a slight upper cladding layer left between the lip portions to strengthen the electric field coupling between the waveguides. ing.

First, prior to explaining the present invention, this conventionally known distributed coupling type optical switch will be briefly explained.

FIG. 2 is a perspective view schematically showing the structure of the optical switch disclosed in the above-mentioned document.

A brief explanation of the conventionally structured optical switch shown in the figure is as follows.
10 is an n''-GaAs substrate, 12 is an n-AffiGaA3 lower cladding layer provided on this substrate 10, and 14 is an n--GaAs optical waveguide layer provided on this lower cladding layer 12. Two parallel rib portions 16 and 18 are provided on the wave layer 14 and extend in the waveguide direction, and the respective lip portions 16 and 18 are formed of a p-AuGaAs upper cladding layer 20 and a p-GaAs cap layer 22. The portions of the leading wave layer 14 directly under these rib portions 16 and 18 form optical waveguides. Note that 24 is an n-side electrode and 26 is a p-side electrode.Switching of this optical switch is performed on one side. By applying a switching voltage Vs between the p-side electrode 26 of the rib portion 16 or 18 and the n-side electrode 24 of the substrate 10, the p-n junction between the upper cladding layer 20 and the optical waveguide layer 14, which is in the dark, is reversed. This is done by applying a bias and utilizing the fact that the refractive index of the optical waveguide corresponding to the lower side of the rib portion 16 or 18 changes in response to this reverse bias.

By the way, the switch length Lc of such an optical switch is usually about 2 mm at the shortest. In order to construct a matrix switch using this optical switch or to construct a compact device incorporating this optical switch, the switch length Lc! It is hoped that the period will be shortened considerably.

Figures 3 to 5 are characteristic curve diagrams obtained under the conditions of obtaining good switching characteristics (for example, extinction ratio > 20 dB, switching voltage < 20 V, wavelength = 1.3 um) for this optical switch. be.

Figure 3 shows the switch length Lc (shown in mm on the vertical axis).
) and the rib width W (indicated in μm on the horizontal axis).
and the thickness of the p-upper cladding layer of 18 darkness. From this figure, it can be understood that by reducing the rib width W, the switch length Lc can be reduced.

FIG. 4 shows the switch length Lc (shown in mm on the vertical axis).
) and the layer thickness t of the optical waveguide layer 14 (shown in μm on the horizontal axis,
), in which the parameter is the layer thickness of the p-upper cladding layer between the two rib portions 16 and 18. From this figure, it can be understood that the switch length Lc can be reduced by increasing the layer thickness t of the optical waveguide layer 14.

FIG. 5 is a characteristic curve diagram showing the relationship between the switching voltage Vs (indicated in units of V on the vertical axis) and the layer thickness t of the optical waveguide layer 14 (indicated in units of Llm on the horizontal axis), The parameter was the layer thickness of the p-upper cladding layer between the two slope parts 16 and 18. From this figure, it can be understood that by increasing the layer thickness t of the optical waveguide layer 14, the switching voltage Vs can be increased.

As can be understood from these characteristic curves, in order to design the conventional optical switch shown in FIG. 2 to be compact, it is necessary to shorten the switch length Lc. This can be achieved by reducing the rib width W and increasing the layer thickness ti of the optical waveguide layer 14, but if the layer thickness t is increased, the switching voltage Vs becomes large.

(Issues to be Solved by the Invention) As already explained, this optical switch is attracting attention as an optical switch for optical exchangers.For this purpose, in order to function as an optical switch, it is generally necessary to increase the switching operation speed. In order to perform switching operations at such high speeds, it is necessary to set the switching voltage Vs to a low voltage, for example, within a range of about 0 to 10 V, thereby reducing the constraints on the drive circuit. However, in reality, this switching voltage Vs is as high as 20 to 30 V, and the switching voltage Vs is as high as 20 to 30 V. There was a problem with that.

On the other hand, when the switch length Lc is increased to reduce the switching voltage Vs, the resistance and parasitic capacitance in the longitudinal direction of the electrode (p-side electrode) on the rib portion 16 or 1B increase,
Furthermore, there is a problem in that the switching speed decreases because a shift occurs in the traveling direction of the modulated electromagnetic wave and the light wave.

The purpose of the present invention is to solve the above-mentioned two problems. Therefore, it is an object of the present invention to provide an optical switch having a structure in which both the switch length and the switching voltage can be reduced, and to provide a method for manufacturing the optical switch. There is a particular thing.

(Means for Solving Problem M) In order to achieve this objective, according to the distributed coupling optical switch of the first invention of this application, a p-type lower cladding layer provided on the upper side of a p-type substrate is provided. First and second optical waveguides of a multi-quantum well structure of p, n or i type are formed in stripes parallel to each other on the top, and n-type optical waveguides are provided directly above the first and second optical waveguides, respectively. Correspondence between the upper cladding layer vA region and the Zn diffusion region that defines this n-type upper cladding layer region and also defines these first and second optical waveguides by disordering the multiple quantum well structure. n-type first and second main electrode regions provided on each upper cladding layer drop region, and provided between the first and first main electrode regions and on the 2n diffusion region. and a field effect transistor having an i-type gate channel region.

According to the method for manufacturing a distributed coupling optical switch according to the second invention of this application, an n-type upper cladding layer is formed above a p-type substrate;

A process of sequentially growing crystals of an n-type or i-type multi-quantum well layer and an n-type upper cladding layer, and a step of growing crystals parallel to each other from this upper cladding layer to a depth reaching at least the surface of the lower cladding layer described above. forming a Zn diffusion region leaving a striped region to define an upper cladding layer region and defining first and second optical waveguides of a multi-quantum well structure; a step of growing i-type active N on the layer region and the Zn diffusion region; *
and forming respective electrodes on the upper surfaces of the first and second main electrode regions, the gate channel region which is the region of the i-type active layer between these electrodes, and the lower surface of the substrate. It is characterized by including the step of providing.

(Function) According to the distributed coupling optical switch having the above-described configuration according to the present invention, the first and second optical waveguides are provided on the lower cladding layer in parallel to the optical waveguide direction to form a rib structure, and these rib-like It has a structure in which first and second main electrode regions constituting a field effect transistor and a gate channel region between these are provided above the first and second optical waveguides. Therefore, for example, a field effect transistor can be constructed by using the first main electrode region on the first optical waveguide as a drain region and the second main electrode region on the second optical waveguide as a source region. Upper and lower cladding layers with refractive indexes smaller than these are provided above and below the first and second optical waveguides, and Zn diffusion regions are provided on the sides of these optical waveguides. This Zn diffusion region makes this multiple quantum well structure disordered, and the disordered region therefore Zn
Since the diffused region has a lower refractive index than that in the first and second optical waveguides, which are regions of the undisordered multi-quantum well structure, these disordered Zn diffused regions create an in-plane conformation including the optical waveguide direction. In addition to confining light in a plane parallel to the substrate surface, the upper and lower cladding layers can effectively confine light in a plane perpendicular to the optical waveguide and perpendicular to the substrate surface. It has a structure.

In this configuration, the train region t1i is connected to the positive terminal of the power supply through a resistor, and the source I! The gate channel region is connected to a common connection point, such as ground potential, at the same potential as the substrate to control the voltage applied to the gate channel region. This control turns the field effect transistor on and off, and in response, the first optical waveguide below the train region becomes reverse biased or debiased, so that the refractive index of this first optical waveguide changes. Light input from one end of the first optical waveguide of the switching lever is output from the first optical waveguide or from the second optical waveguide.

As described above, since the optical switch of the present invention includes a field effect transistor structure that controls the switching operation of its optical output, the driving voltage of the driving circuit can be reduced, and therefore the switching voltage of the optical switch can be reduced. Therefore, the maximum switch voltage Vs that can drive this optical switch can be increased, and a correspondingly short switch length Lc can be set.

Further, according to the manufacturing method of the present invention, Zn is easily diffused after providing the lower cladding layer, the multiple quantum well layer, and the upper cladding layer on the substrate, with a relatively small number of steps.
Rib-shaped first and second optical waveguides can be formed, respectively, and the guide waveguides can be surrounded by layers of semiconductor material having a lower refractive index than the guide waveguides. In general, each region of a field effect transistor can be easily formed above these optical waveguides with a relatively small number of steps.

(Embodiments) Hereinafter, embodiments of the distributed coupling type optical switch of the present invention will be described with reference to the drawings.

Note that the drawings showing the structure of the device described below are only schematic illustrations to the extent that the present invention can be understood. Therefore, the structure of the optical switch as well as the dimensions of each component
It should be understood that the shapes, W distribution relationships, numerical examples, etc. are not limited to the explanations using the illustrated embodiments, and are merely illustrative.

Figure 1 (A) is a perspective view showing an embodiment of the distributed coupling type optical switch of the present invention, and Figure 1 (8) is a cross-sectional view of this optical switch in a plane orthogonal to the waveguide direction. It is a figure showing an example of an electrical connection state. It should be noted that hatching etc. representing the cross section are omitted except for a part.

In the optical switch of the present invention, a field effect transistor is provided over the first and second optical waveguides and the region between them, and applies a reverse bias to one of the leading waveguides to change its refractive index to perform a switching operation. It has a structure. First, in the embodiment shown in FIGS. 1A and 1B, a p-(indicated by P in the figure)-AuGaAs lower cladding layer 32 is provided on a p-Ga1s substrate 30. First and second optical waveguides 34a and 34b having a stripe-like multi-quantum well structure are provided on the side cladding layer 32, extending parallel to each other in the waveguide direction to form a rib structure. The conductivity type of the optical waveguides 34a and 34b does not matter and may be p-type, n-type, or i (intrinsic), but in this embodiment, for example, it is i (intrinsic), and therefore, the optical waveguides are made of 1-GaAs and i. 1 consisting of -AβGaAs
- It is constructed as a GaAs/AfGaAs multiple quantum well structure. Further, these optical waveguides 34a and 34b are formed of a semiconductor material whose refractive index is larger than that of the lower cladding layer.

On these rib-shaped first and second optical waveguides 34a234b, n (indicated by N in the figure)-Aj2GaA, respectively.
s The upper cladding Il is provided with recessed areas t136a and 36b. These upper crat layer regions 36a.

38b is formed of a semiconductor material whose refractive index is smaller than that of the optical waveguides 34a and 34b.

In this invention, Zn diffusion regions 38a and 38b are used to define the laminated structure of the leg-guide waveguide 34a and the upper cladding layer region 36a, and the laminated structure of the second optical waveguide 34b and the upper cladding layer region 36b, respectively.

It has 38c. The technique for defining and forming these optical waveguides 34a, 34b and upper cladding layer regions 36a, 36b will be described in detail.
z GaAs/AuGaAs multiple quantum well layer and n-A1! For the GaAs upper cladding layer, from the surface side of the upper cladding layer to the lower cladding [3
These laminated structures are defined by selectively diffusing Zn until reaching 21. This Zn diffusion makes the multiple quantum structure of the i-type multiple quantum well layer disordered, lowering the refractive index and making it p-type. Therefore, the Zn diffusion regions 38a to 38
c is the region where Zn diffusion was not performed, that is, the optical waveguide 3
4a and 34b are defined and formed. Similar 1
Also in the upper cladding layer, p-type Znn expansion regions 38a to 38c are formed by this Z and n diffusion, and these regions become n-type cladding layer regions 3 in which Zn is not diffused.
6a and 36b are defined and formed.

Furthermore, 5, mainly these upper cladding layer regions 36a,
n”-Ga forming the first and second main electrode regions on 36b.
As ohmic m1li42a, 42b! In addition, the Zn diffusion regions 'ii 38a to 38c are each provided with one GaAs active layer '1i40a, 40b, 40C, and the j6 type active NI above the Zn diffusion region tff38e is provided.
The region 40c is used as a gate/channel region. The first and second main electrode regions 42a, 42b and the gate channel region 38c form a field effect transistor (indicated by the symbol FET).

Note that 40a and 40b are the gate channel regions 40 described above.
When forming cV, Zn diffusion li regions 38a, 38b
Although the 1-GaAs active layer regions are respectively formed on top, these layers 40a and 40b are not necessarily required and may be omitted.

Generally speaking, these first and second main electrode regions 42a.

Electrodes (ohmic electrodes) 44a and 44b made of a suitable conductive material are provided to apply a voltage to the gate 42b, and a gate electrode (ohmic electrode) made of a suitable conductive material is provided on the gate channel region 40e as a control electrode. Schottky electrode) 44C. Also, 50
is an electrode provided on the lower surface of the substrate 30, which in this case is a p-side electrode.

The optical switch configured as described above includes first and second optical waveguides 34a that are provided parallel to each other in the shape of ribs.

34b! The first and second optical waveguides 34a, 34b and the Z between them are surrounded by a layer having a smaller refractive index than this.
This is a distributed coupling type optical switch that switches the leading wave by controlling the switching of a field effect transistor provided over the n-diffusion region 1fi38c.

Next, the operation of the optical switch having the above-mentioned structure will be explained.

Figures 6 (A) to (H) are operation explanatory diagrams of the switching timing and output of various required signals (the vertical axis shows the magnitude of this signal, and the horizontal axis shows the time t). ),
Figure 7 shows the train current plot using the gate-source voltage Vos (in V units) of the field-effect transistor structure of the optical switch as a parameter. FIG. 3 is an operating characteristic curve diagram showing the relationship between the drain voltage VD (indicated in mA on the vertical axis) and the drain voltage VD (indicated in V units on the horizontal axis).

In order to operate this type of optical switch, the following connections are made, for example.

In the connection example shown in FIG. 1 CB), the p-side electrode 50 is connected to a common reference potential point, for example, the ground potential. Further, the first main electrode region 40a above the first optical waveguide 34a is used as a train region, and therefore the drain electrode 42 which is an ohmic electrode
The positive terminal of the power source E0 is connected to a through a resistor. The negative side terminal of this power source EOO is connected to a common reference potential point, and the voltage of the power source E0 is also indicated by Eo.

On the other hand, the second main electrode region 40b is connected to the source 9It! Ji, and therefore its ohmic electrode is the source electrode 42b.
is connected to a common reference potential point and the input signal source Ein
Gate electrode 4 which is a gate Schottky electrode through
Connect to 2c.

In this connection state, the field effect transistor (
The operating characteristics of the FET (FET) are similar to those of conventional bipolar transistors, such as those illustrated in FIG. 7, for example. As can be understood from the operating characteristic curve diagram in FIG. 7, the gate-source voltage VG of the transistor CFET)
When I is changed in the range of several volts, for example, in the range of 0 to -5v, the operating point moves from point 8 on negative rye to point A, so
Train electrician. The train voltage v0 can be varied over a range of several tens of volts, such as from about 5 volts to about 32 volts.

In the connection state described above, the dark potential difference between the source electrode 42b and the p-side electrode 50 is substantially 0, so that the second optical waveguide 34b is always in a state where no reverse bias voltage is applied (the 6 (F)), in this state, first, the voltage applied to the gate from the input signal source Ein! The initial state is set as Ein=O.

When the initial state is set in this way, the gate-source voltage v0. is substantially Ov (Figure 6(A))
, as is clear from the operating point B on the load line in Figure 7, the train current ◎ flows (Figure 6 (B)'), so the train voltage v0 is almost close to Ov (
6(C)), the field effect transistor FET is in the on state (FIG. 6(D)), so in this case:
The first optical waveguide 34a is also close to Ov and is not reverse biased (Fig. 6(E)'), and the optical signal input to the first optical waveguide 34a is transferred from the first optical waveguide 34a at the switch length Lc. rather, it is output from the second optical waveguide 34b (FIGS. 6(G) and (1-1)).

Next, apply the base voltage from the input signal source Ein and the gate-source voltage VGI so that the potential of the gate electrode is more negative than the potential of the source electrode, for example, on the load line as shown in FIG. When the operating point A is set (Fig. 6 (A)'
), drain current I.

6 (CB)'), the train voltage v0 increases to 32 to 33 V and the train electrode becomes almost at the voltage E0 (Fig. 6 (C)'). Therefore, The field effect transistor (FET) is turned off (FIG. 6(D)), a reverse bias voltage is applied to the first optical waveguide 34a, and the voltage of the first optical waveguide 34a is equal to the common reference potential of the p-side electrode 5o. When viewed from the point, the voltage is a positive value (Fig. 6(E)).

Due to this reverse bias voltage, the refractive index of the first optical waveguide 34a increases due to the first-order electro-optic effect, so the coupling conditions between the first optical waveguide 34a and the second optical waveguide 34b change, Therefore, the light incident on the first optical waveguide 34a propagates through the same optical waveguide 34a at the switch length Lc and is output from the same optical waveguide 34a (FIG. 6(G)), and the second optical waveguide 3
There is no output from 4b (Fig. 6 (H)).

Next, when the voltage applied from the input signal source Ein to the gate electrode 44c is returned to the operating point on the load line in FIG. 7, the voltage state of each part of the optical switch returns to the same voltage state as the initial state described above. Therefore, the reverse bias condition for the first optical waveguide 34a due to the aforementioned pn junction is eliminated, and therefore the first
The increase in the refractive index due to the secondary electro-optic effect disappears, and the refractive index of the first optical waveguide 34a returns to its original value. Therefore, the light incident on the first optical waveguide 34a is switched to the second optical waveguide 34b and output from the second optical waveguide 34b (FIG. 6(H)).

In this way, when the field effect transistor (FET) is turned on and off by controlling the gate voltage from the input signal source Ein, the refractive index of the first optical waveguide changes in response, and this refractive index changes. Since the switch length Lc changes due to the change, the switching operation of the optical switch can be performed repeatedly. In the optical switch of this embodiment, this switching operation can be performed with a gate voltage of several volts or less.

The optical switch of the present invention is not limited only to the first embodiment described above, but can be modified or modified in many ways.

For example, in the embodiment shown in FIG.
Field effect 1-range disk (F) installed above i38c
E lower) was provided over the entire length from the input end to the output end of the leading wavepath of this optical switch, but each layer constituting the field effect transistor FET was not provided over the entire length as in the other embodiment shown in FIG. The waveguide may be provided over a portion of the length of the leading waveguide.

Furthermore, since the j, - active layer regions 40a and 40b are not necessarily required, they may not be provided depending on the design.

In FIG. 8, constituent components (V) similar to those shown in FIG. 1(A) are designated with the same reference numerals (
] The detailed explanation will be omitted.

Furthermore, in the above-described embodiment C, the first and second conductivity types are p and n types, respectively, and l can be the n and p types of π, respectively.

Furthermore, in the optical switch of the embodiment described above, the material composition is G.
a A S /' A IlG a A 8, but it can be constructed using InP/InGaAsP or other combinations of materials depending on the design.

Furthermore, the structure of the optical switch of this invention has an electric field effect on the upper side of the lip-shaped leading waveguide! - Since the optical switch is characterized by having a transistor structure, the laminated N structure constituting this optical switch is not limited to the above-mentioned 1 and embodiments, and may include any other suitable structure according to the design. Even if it is, it is sufficient that it has a rib waveguide structure.

Set Meng”” [1st Corps” Next, one embodiment of the manufacturing method of the present invention will be described.

FIGS. 9(A) to 9(E) are process diagrams for explaining the manufacturing method of the optical switch shown in FIG. 1 is a schematic cross-sectional view showing the state.The same components as in FIG. 1(A) in the plane are indicated by the same reference numerals.

First, an o-GaAs substrate 301j5 is prepared, placed in a long furnace, and a conductivity type p of p-AβGaAsβGaAs in the lower Clara diagram is grown on this substrate 30 using a normal crystal growth technique. is denoted by P. ), 1-GaAs/
Aj7GaAs multiple quantum well (MQW) structured optical waveguide layer 340, n-AllGaAs upper cladding layer 360 (
In the figure, guide! The crystals of @gn and N' (indicated by F) are sequentially grown using ordinary techniques and under any suitable conditions according to the design (Fig. 9 (A)). In this case, the leading The semiconductor material of the waveguide layer 340 has a refractive index that is greater than the refractive index of the semiconductor materials of the upper, lower, and upper cladding layers.

Next, a suitable mask 52 such as a 5iiNn film, for example, is provided on the regions of the upper cladding layer 360 where the first and second optical waveguides are to be formed, using a conventional technique, and from the exposed surface of the upper cladding layer 360, At least lower cladding 83
Zn is diffused until it reaches the surface of Zn diffusion region 3.
8a, 38b, 38ct formed. These Zn diffusion regions i
! As already explained, J38a, 38b, and 38c are p-type regions.

Since the multi-quantum well structure is disordered due to ZnE, the refractive index of the disordered region becomes smaller than the refractive index of the non-disordered region of the multi-quantum well structure. Therefore, this Zn diffusion region 38a.

38b, 38c are from the optical waveguide layer 340 to the second optical waveguides 34a, 34b! Upper cladding layer regions 38a, 36b are also defined above each. In the case of this embodiment, the first optical waveguide 34a and the upper seven cladding layer region 36a are formed as a laminated structure, and the second optical waveguide 34b and the upper cladding layer region 36b are formed as a laminated structure, and furthermore, These laminated structures are formed as parallel flims that extend in stripes from the input end to the output end in the direction of the leading wave (Fig. 9 (B).
)) In this case, Zn diffusion may be performed using either the ion implantation method or the thermal diffusion method, and is naturally performed under conditions suitable for each layer to be diffused.

As described above, due to this 26 Zn diffusion, the lip-shaped first and second optical waveguides 34a
, 34b and the upper cladding layer regions 36a, 36b can be easily formed. Next, after removing the mask 52, the Zn
A 1-GaAs active layer 400 is crystal-grown over the diffusion regions 38a, 38b, 38c and the upper cladding layer regions 36a, 36b using a conventional technique and under any suitable conditions depending on the design (9th step). Figure (C)).

Subsequently, another mask 54 is provided on the surface of the active layer 400 outside the area where the ohmic area, which is the ohmic area and the second main electrode area, is to be formed. Type impurities are added to at least the lower upper cladding layer regions 36a, 36b and the Zn diffusion regions 38a, 38.
b, Introduced to a depth that reaches the surface of 38c to create an n-type ohmic! These ohmic 9I regions are used as first and second main electrode regions 42a and 42b. These main electrode 111 regions 42a and 42b are connected to the upper cladding layer region 36.
It is sufficient if it is provided so as to be electrically conductive with a and 38b.
The region 40c of the i-active layer 400 remaining between the first and second main electrode regions 42a and 42b becomes the gate channel region # region (FIG. 9(D)).

In this way, the first and second optical waveguides 3 can be formed with a small number of man-hours.
4a and 34b can be surrounded by a material having a refractive index smaller than that of the optical waveguide, except for the optical input end and the optical output end, and regions constituting a field effect transistor can be formed above the optical waveguides 34a and 34b. .

Next, after removing the mask 54, ohmic electrodes 44a and 44b as train and source electrodes are formed on the first and second main electrode regions 40a and 40b, and gate/Schottky electrodes 44c are formed on the gate channel region 42, respectively. An electrode 50 is deposited on the bottom surface of the substrate 30 as well as any suitable material. The method for forming these electrodes may be any suitable method (FIG. 9(E)'), and necessary treatments other than those described above may be performed at appropriate times as usual depending on the design.

The above-described process is merely an example, and the present invention is not limited to this method in any way. For example, in the case of an optical switch structure as shown in FIG. 8, the growth of the i-active layer 400 is The optical waveguide 34a is provided only over the layer regions 42a, 42b and the Zn diffusion region 38c therebetween.

first and second main electrode regions 4 extending the entire length of 34b;
0a, 40b and the gate channel region 42 are additionally etched so as to remain over a part of the length of the optical waveguide, and then the n◆-ohmic regions 42a, 42 are etched.
2b! or may be formed by any other suitable procedure, or by adding and/or incorporating any other desired steps depending on the layer structure, material used, conductivity type, etc. It may be formed by changing the shape or the like.

(Effects of the Invention) As can be understood from the above explanation, according to the distributed coupling optical switch of the present invention, the switching operation of the optical output is performed by the first optical waveguide provided above the first and second optical waveguides. Since the structure is controlled by a field effect transistor structure having a gate channel region and a second main electrode region, and a gate channel region therebetween, the drive voltage of the drive circuit is lower than that of the conventional method, and the switching of the optical switch is controlled. The voltage can be made small, and therefore the maximum switch voltage vS that can drive this optical switch can be made large.
Therefore, a short switch length Lc corresponding to this can be set.

Further, since the optical switch of the present invention has a structure that can be driven with a switching voltage of several volts, the output voltage of the drive circuit can be reduced during high frequency driving. It is highly suitable for use in forming high frequency drive circuits.

Further, according to the manufacturing method of the present invention, the rib-shaped first and second optical waveguides can be easily formed with a relatively small number of steps, and a semiconductor having a smaller refractive index than these optical waveguides can be formed. It is possible to surround these leading waveguides with a region, and it is possible to fabricate each region of a field effect transistor above these optical waveguides.

[Brief explanation of the drawing]

1A and 1B are schematic perspective views and sectional views showing an embodiment of the distributed coupling type optical switch of the present invention, and FIG. 2 is a T perspective view showing an example of the configuration of a conventional optical switch. , Fig. 3 to Fig. 5 are good switching characteristic curves as a conventional optical switch, Fig. 6 (A) to Fig. 6 (H) are operation explanatory diagrams of an embodiment of the distributed coupling type optical switch of the present invention, FIG. 7 is an operating characteristic curve diagram of the 1-transistor structure of the distributed coupling type optical switch of the present invention, FIG. 8 is a schematic perspective view showing another embodiment of the distributed coupling type optical switch of the present invention, and FIG. 9 FIG. 1 is a process diagram for explaining a method of manufacturing a distributed coupling type optical switch of the present invention. 30...p-substrate, 32--p-lower cladding layer 34a--first optical waveguide, 34b...-second optical waveguide 36a, 36b--n-upper cladding layer region 3
8a to 38C-Z n diffusion regions 40a to 40c - 1 - active layer region 42a - = first main electrode region, 42b - second main electrode region 44a, 44b - ohmic electrode 44cm... gate side key electrode 50...Electrode, 52.54...Mask 340-(multi-quantum well structure) optical waveguide layer 360...n-Upper cladding layer 400=j-Active layer Eo"" bias power supply, R... Resistor Ein...Input signal source. Patent applicant Oki Electric Industry Co., Ltd.-12: Configuration example of conventional optical switch 0, + 0.2 (L30.40.50.60.70.
80.91.0 (μm) Relationship between switching voltage V and guide layer thickness t Figure 5 Figure w (um) Relationship between switch length Lc and lip width W Figure 3 t (um) Switch length Lc and guide layer thickness t Fig. 4 Drain voltage (V) Drain current-voltage characteristics of FET section Fig. 7 I. GS Procedural Amendment 1 Case Indication 1988 Patent Application No. 176695 2
Name of the invention Distribution-coupled optical switch and its manufacturing method 3 Relationship with the amended case Patent applicant address (〒-105) 1-7-12 Toranomon, Minato-ku, Tokyo Name (029) Oki Electric Industry Co., Ltd. Representative: Komura Polarized Light 4 Agent: 170 fi (988) 5583 Address: 905 (1), Ikebukuro White House Building, 1-20-5 Higashiikebukuro, Toshima-ku, Tokyo, "In the row direction" on page 7, line 19 of the specification Correct 1 to r row speed. 2), same, page 26, line 17 to page 26, line 18, “
``This 3Zn diffusion'' is corrected to ``this Zn diffusion''. 6. Subject of correction

Claims (2)

[Claims] (1) First and second optical waveguides of p-, n-, or i-type multi-quantum well structure formed in stripes parallel to each other on a p-type lower cladding layer provided on the upper side of a p-type substrate; , an n-type upper cladding layer region provided directly above each of the first and second optical waveguides, and defining the n-type upper cladding layer region and disordering the multi-quantum well structure. and a Zn diffusion region defining a second optical waveguide, and n^+ type first and second main electrode regions provided on each corresponding upper cladding layer region; and a field effect transistor having an i-type gate channel region provided between two main electrode regions and above the Zn diffusion region. (2) A p-type lower cladding layer on the upper side of the p-type substrate, p, n
Alternatively, a step of sequentially growing crystals of an i-type multiple quantum well layer and an n-type upper cladding layer, and forming mutually parallel striped regions from the upper cladding layer to a depth reaching at least the surface of the lower cladding layer. forming a Zn diffusion region on the upper cladding layer region and the Zn diffusion region to define an upper cladding layer region and defining first and second optical waveguides of a multi-quantum well structure; a step of growing an i-type active layer; a step of forming n^+-type ohmic regions as first and second main electrode regions in regions above the upper cladding layer region of the i-type active layer; A distribution characterized in that it includes the step of providing respective electrodes on the upper surfaces of the first and second main electrode regions and the gate channel region which is the region of the i-type active layer between these electrodes, and on the lower surface of the substrate. A method for manufacturing a combined optical switch.