JPH02257497A - Integrated circuit - Google Patents

Abstract

PURPOSE:To prevent data, which are written to the cell of a PROM, from being erased even at a high temperature or after the lapse of a long period by once writing the data, which are read out of the cell of the PROM, to a register according to a signal to instruct rewriting and writing these data to the cell of the PROM again. CONSTITUTION:When rewriting is started, a refresh signal REF is set to '1'. At timing that the refresh signal is '1' and a read signal RD is '0', a register (REG) 109 latches a data signal from a nonvolatile memory (PROM) 103 and outputs a data signal IO. The data signal IO is inputted through a multiplexer (MPX) 110 to the PROM 103 and stored. Since an address signal at such a time is still an address signal when the data signal is read out of the PROM 103, the data written from the REG 109 are stored in an address same as that of a reading time and rewriting is completed concerning one address. Thus, the PROM data can be held even at the high temperature or after the lapse of a long period.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a programmable ROM device (hereinafter simply referred to as FROMM) that erases data by irradiating it with ultraviolet rays.
In particular, it relates to refresh circuits.

[Prior Art] As a memory element constituting a cell of a non-volatile memory (hereinafter referred to as PROM), which erases data by irradiating it with ultraviolet rays and stores data electrically, two layers of a floating gate and a control gate are used. There is a field effect transistor (hereinafter referred to as a memory transistor) having a gate structure.

FIG. 7(A) shows the structure of a memory transistor. A source 7 is formed on the P-type substrate 701 by N-type diffusion.
02 and a drain 703 are formed. source 7
02. A gate oxide film 704 is formed on the substrate 701 between the drains 703 . An insulated floating gate 705 is formed on the gate oxide film 704, and a control gate 706 is further formed above the floating gate 706.

GND is grounded, and source 702 and P-type substrate 701 are connected to G
Connected to ND. VG is a control gate voltage, and VD is a drain voltage.

FIG. 7(B) shows the relationship between the control gate voltage VC of the memory transistor and the drain current ID.

In this memory transistor, when the floating gate 705 is in an electrically neutral state (hereinafter referred to as a non-writing state),
As shown by a solid line 707, a conductive state is established at a low control gate voltage VG (for example, 2V), and a drain current flows.

When a high voltage (for example, 12.5 V) is added to the control gate voltage VG and drain voltage VD, electrons are injected into the floating gate 705, and the threshold voltage of the memory transistor as seen from the control gate 706 increases (hereinafter referred to as the write state). Therefore, as shown by a solid line 708, a conductive state cannot be achieved unless a high control gate voltage VG (for example, 7 V) is applied.

Therefore, if the control gate voltage VG is between the solid line 707 and the solid line 708 when reading data (for example, 5V
), the memory transistor in the non-writing state has conduction between the source and drain, and the memory transistor in the writing state has no conduction between the source and drain, so it is possible to distinguish whether data exists or not.

A conventional FROM is configured by arranging cells using these memory transistors, and further includes a sense array, a write/read control circuit, an address decoder, etc. (not shown).

FIG. 8 shows a block diagram of a conventional FROM.

The area inside the dotted line indicates the inside of the accumulation.

The address signal is input to an address terminal group 801, and is input to the FR0M 803 via an address buffer 802.

When read signal RD is active (“0″), FRO
This is a signal instructing data read for M, and is input to the PROM 803 via an external terminal 804.

When the write signal PROG is active (“0”), F
This signal instructs data writing to R0M803, and is input to PROM803 via external terminal 805.

Data signals are input and output from data terminal group 806.

The data output buffer 7807 is connected to the data terminal group 806, and outputs a data signal as an output buffer when the read signal RD is ti Ou, and when the write signal PROG is “0”.
” operates as an input buffer and inputs data signals.

Writing a data signal to the PROM 803 will be explained.

Address signals are input from the address terminal group 801. The address signal passes through the address buffer 802 and outputs 1” PRO.
M803CZ is input and specifies the address of PROM803.

When the write signal PROG is set to "0" and a data signal is input from the data terminal group 806, the data output cover rough 780
7. PROM803Ci: A data signal is input and the data signal can be written to a specified address.

To read data signals from the PROM 803, address signals are input from the address terminal group 801. The address signal passes through the address buffer 802 to the TPROM 803.
C: Input to specify PROM803(7) address.

When the read signal RD is set to "0", the data signal of the designated address is output from the PROM 803. The data signal is output from the data signal terminal group 806 through the data output buffer 7807.

[Problems to be Solved by the Invention] A memory transistor, which is a component of a FROM cell, stores electrons in a floating gate. This FR
When a PROM made up of OM cells is operated at a high temperature, the electrons accumulated in the floating gate are excited by thermal energy, enter a high energy state, and are dissipated outside the floating gate. Further, even if the temperature is not high, the accumulated electrons will be dissipated to the outside if a long period of time has passed after writing.

If electrons are lost in even one cell and data is erased, the data written in that FROM will become data with a different meaning, and if this data is a program instruction code, problems such as program runaway may occur. There is a high possibility that it will happen.

Therefore, under high temperatures or after a long time has passed after writing,
Since the data written in the ROM is lost, a problem arises in that the FROM cannot be used under certain conditions such as in automobile electrical equipment.

The present invention has been made in view of the above-mentioned conventional circumstances, and it is an object of the present invention to provide an integrated circuit that reasonably solves the above-mentioned problems.

[Differences between the invention and the prior art: While the conventional PROM described above did not take any measures against the dissipation of electrons accumulated in the floating gate, the first invention uses a signal instructing rewriting. PR by
The data read from the OM cell is written to the -H register, and the data in this register is written to the FROM cell again to rewrite the data. Even under high temperatures or after a long period of time, the data written to the FROM cell remains unchanged. Prevents erasure.

Furthermore, in the second invention, data read from the FROM cell is written to the -H register by a signal instructing rewriting, and when writing the data in this register to the FROM cell again, the Even if the data in the cell of the FROM read out is partially erased, the data is corrected by the error correction circuit and the correct data before being erased is written, so a highly reliable FROM can be constructed.

Note that when data is read out from the integrated circuit, it does not pass through an error correction circuit, so there is no signal delay and data can be read out at high speed.

[Means for Solving the Problems] An integrated circuit according to the first invention of the present application is an integrated circuit that includes a memory section consisting of non-volatile memory cells into which data can be electrically written, in which an address is set for writing or reading data. A specified address instruction circuit, a holding circuit that holds data read from the nonvolatile memory cell specified by the address instruction circuit, and a holding circuit that holds the data read from the nonvolatile memory cell specified by the address instruction circuit in response to a control signal. The present invention is characterized by comprising a switching circuit that supplies data held in the holding circuit or external data.

An integrated circuit according to a second invention of the present application is an integrated circuit including a memory section made of nonvolatile memory cells into which data can be electrically written, and an address instruction circuit that specifies an address for writing or reading data;
A test signal generation circuit generates test signal data for data correction from write data to a non-volatile memory cell and writes the data to the same non-volatile memory cell together with the write data, and a test signal generation circuit generates test signal data from the non-volatile memory cell specified by the address instruction circuit. A holding circuit that holds the read write data and test signal data; and a holding circuit that holds the read write data and test signal data; The present invention is characterized by comprising a correction circuit that performs correction, and a switching circuit that supplies output data from the correction circuit or external data to a nonvolatile memory cell designated by an address instruction circuit in response to a control signal.

[Embodiment] FIG. 1 shows a block diagram of a PROM according to a first embodiment of the first invention. The area inside the dotted line indicates the inside of the integrated circuit.

In this embodiment, the PROM 103 has a data width of 8 bits.

The address signal is input to the address terminal group 101, and is input to FROMI03 via the address buffer 102.

When the read signal RD is active (“0”), the PROM
This is a signal instructing data read to 103, and is input to FROMIO3 via external terminal 104.

When the write signal PROG is active (O'''), PR
A signal instructing data writing to OM103 is input to FROMI03 via external terminal 105.

Data signals are input and output from data terminal group 106.

The data output buffer 107 is connected to the data terminal group 106, and when the read signal RD is '0', it outputs a data signal as an output buffer, and when the write signal PROG is '0', it operates as an input buffer and inputs a data signal. do.

The refresh signal REF is a signal that instructs rewriting of FROM data, and when active (“1”) indicates rewriting, and is input from the external terminal 108.

The register (hereinafter referred to as REG) 109 uses the PROM data signal manually, and the refresh signal REF is "1".
latches the data signal when the read signal RD is “0”,
When the refresh signal REF is “1”, the write signal PROG
When is O'', a data signal is output.

A multiplexer (hereinafter referred to as MPX) 110 receives the output signals of the output buffer 107 and REG 109 as inputs, and when the signal REF is "0", the data input buffer 10
7 inputs and outputs the data signal of PROM 103, and the signal RE
When F is “1”, the output signal of REG109 is transferred to PROM1.
03 as a data signal.

Writing a data signal to PROM 103 will be explained. The refresh signal REF is set to "0" and an address signal is input from the address terminal group 101. The address signal is input to PROM 103 through address buffer 102 and specifies the address of FROMI03.

When the write signal PROG is set to "0" and a data signal is input from the data terminal group 106, the data output buffer 10
A data signal is input to the PROM 103 through the 79MPx 110, and the data signal can be written to a designated address.

Here, since the refresh signal REF of the multiplexer MPXIIO is "0", the data output buffer 107
The output is input to the PROM 103.

To read a data signal from the PROM 103, the refresh signal REF is set to "0" and an address signal is input from the address terminal group 101. The address signal is input to the PROM 103 through the address buffer 102.
Specify the address of 103.

When the read signal RD is set to "0", the data signal of the designated address is output from the PROM 103. The data signal is output from the data signal terminal group 106 through the MPXIIO and the data output buffer 107.

Here, MPXIIO has a refresh signal REF of “0”.
Therefore, the data signal output of the PROM 103 is supplied to the data output buffer 107.

Next, the case of rewriting data to FROM will be explained with reference to the timing diagram of FIG. 2.

The refresh signal REF becomes “1” when starting rewriting.
”.Since the refresh signal is “1”, MPXII
O inputs the output of REG109 as a data signal of PROM103.

Next, an address signal indicating an address at which data in the PROM 103 is to be rewritten is input to the address terminal group 101. In FIG. 2, it is indicated by AO. Further, when the read signal RD is set to "0", the PROM 103 outputs a data signal corresponding to the address signal AO.

The REG 109 latches the data signal from the PROM 103 at the timing when the refresh signal REF is "1" and the read signal RD is "0". The latched data signal is shown as "0" in FIG. 2. The read signal RD is "0". 1”
When this is done, reading the data signal from FROMIO3 is completed.

By setting the write signal PROG to “0”, REG109
outputs the data signal IO. Data signal IO is MPX
Human-powered FROMI 03 via IIO. PR
Since the write signal PROG is "0", the OM 103 stores the data signal IO.

The address signal at this time is the same as the address signal when the data signal was read from PROM103, so REG1
The data written from 09 is also stored at the same address as when read, and rewriting is completed for one address. Write signal PR when writing is completed
Set OG to “1”.

When rewriting the next address in the PROM 103, a similar signal may be manually input. In Figure 2, the next address signal is A1, and the REGI09 data signal is 1.
It is shown as 1.

FIG. 3 shows a block diagram of a microcomputer incorporating a PROM according to a second embodiment of the first invention. The area inside the dotted line indicates the inside of the integrated circuit.

The main difference from the embodiment shown in FIG. 1 is that the CPU generates address signals, refresh signals, read signals, and write signals.

This embodiment will be described below with reference to FIG. 3. In this embodiment, the data width of the PROM 302 is assumed to be 8 bits. The mode signal MODE is input to the external terminal 301, and when active (“1”), it instructs to read and write PROM302 data from outside the integrated circuit, and when inactive (“0”), it instructs to read and write PROM302 data from inside the integrated circuit. This is a signal that tells you to read or write.

The read signal RD is input from the external terminal 303, and when active (“0”), instructs data reading from the F_R0M302.

The read signal CRD is output from the CPU 304 and instructs to read data from the PROM 302 when active (“0”).

The selector 305 (hereinafter referred to as 5ELR) selects the read signal RD when the mode signal MODE is 1", selects the read signal CHD when the mode signal MODE is "0", and selects the read signal CHD when the mode signal MODE is "0".
Input to R0M302 as a read signal.

The write signal PROG is a signal that instructs the PROM 302 to read data and is input from the external terminal 306.

The write signal CPROG is output from the CPU 304 and P
This is a signal that instructs data reading from the ROM 302.

The selector 307 (hereinafter referred to as 5ELW) outputs the write signal PROG when the mode signal MODE is "1", and outputs the write signal CPROG when the mode signal MODE is "0"'.
is selected and input manually as a write signal to the PROM 302.

The refresh signal REF is input from the external terminal 308 and is a signal that instructs rewriting of data in the PROM 302. When active (“'1”), it indicates rewriting.
Instructs the PU 304 to rewrite data.

The CPU 304 refreshes the PROM 302 inside the integrated circuit by the refresh signal REF input from the external terminal 308.
A refresh signal CR instructs to rewrite the data of
Outputs EF (active (“1”)).

The address signal is input from the address terminal group 309 to the address buffer 310 . Address buffer 310 operates when mode signal MODE is "L".

The program counter 311 (hereinafter referred to as PC) is a CP
It is controlled by the PC control signal output from U304 and outputs an address signal.

The multiplexer 312 (hereinafter referred to as MPXA) uses the address buffer 31 when the mode signal MODE is "1".
When the mode signal MODE is “0”, the PC31 outputs 0.
1 is selected and input manually as the PROM 302 head address signal.

The data signal is transmitted from the data terminal group 313 to the data buffer 3.
14 is input. The data buffer 314 operates when the mode signal MODE is "1" and is connected to the data bus. The data bus is also connected to CPU 304.

Register 315 (hereinafter referred to as REG) is PROM30
2 data signal is input, the data signal is latched when the refresh signal REF is "1" and the read signal RD is "0", and the data signal is latched when the refresh signal REF is "1" and the write signal PROG is "0". Output.

A multiplexer 316 (hereinafter referred to as MPXD) inputs the data bus and the output signal of REG315, and when the refresh signal CREF is "0", PRO is sent to the data bus.
Input/output M302 data signal and refresh signal C
When REF is “1”, the output signal of REG315 is PROM
302 as a data signal.

Writing of data signals to PROM 302 from outside the integrated circuit will be described. Since this is a write operation from outside the integrated circuit, the mode signal MODE inputs "1" and the refresh signal REF inputs "0".

5ELW307 is the write signal P input from the external terminal.
Input ROG as a write signal to F R0M302.

Refresh signal CREF output from CPU 304
is “0”.

When the address signal is input to the address terminal group 309, the mode signal MODE is "1" and the address buffer 310
operates, and MPXA 312 inputs the address signal from address buffer 310 to PROM 302.

When a data signal is input to the data terminal group 313, the mode signal MODE is "1", the data buffer 314 operates, and the MPXD 316 inputs the data signal from the data buffer 314 to the PROM 302.

Here, when the write signal PROG is set to 0'', the data signal is stored in the PROM302.

The operation of reading data signals from outside the integrated circuit to the FR0M302 will be described. An external read operation is necessary to confirm whether the data stored in PROM 302 is correct.

Since this is a read operation from outside the integrated circuit, the mode signal M
ODE is manually set to "1", and refresh signal REF is set to "0".

5ELR305 is the read signal R input from the external terminal.
D is input to the PROM 302 as a read signal.

Refresh signal CREF output from CPU 304
is “0”. Address signal to address terminal group 309
When the mode signal MODE is "1'', the address buffer 310 operates, and the MPXA 312 transfers the address signal from the address buffer 310 to the PROM 302.
Enter.

Here, when the read signal RD is set to "'0", a data signal is output from the FR0M302. Mode signal MO
When DE is “1”, the data buffer 314 operates and MP
The XD 316 outputs the data signal from the PROM 302 to the data terminal group 313.

Next, the rewriting operation will be described.

The rewrite operation is started when the refresh signal REF becomes "O". At this time, since there is no need to input address signals, data signals, read signals, and write signals from outside the integrated circuit, the mode signal MODE is set to "0".

Since the mode signal MODE is '40', 5ELR305 uses read signal CRD as a read signal to PROM302, and 5ELW307 uses write signal CPROG as a read signal to PROM302.
02 as a write signal. Also, the address buffer 310. Data buffer 314 does not operate.

Since the refresh signal REF of the CPU 304 is "1", the CPU 304 varnishes the refresh signal CREF with "1". MPXD316 inputs the data signal output of PROM302 to REG315.

Next, CPU 304 activates the PC control signal.

The PC 311 sets and outputs the starting address of the PROM 302 using a PC control signal.

When the CPU 304 further sets the read signal CHD to "0", the FR0M 302 outputs a data signal corresponding to the address signal output from the PC 311.

REG315 is F R0M30 when the refresh signal CREF is “1” and the read signal 1cRD is “0”.
Latch the data signal from 2.

Here, the CPU 304 sets the read signal CHD to "1" and P
Reading of data signals from the ROM 302 ends.

Next, the CPU 304 sets the write signal CPROG to "O". REG 315 outputs the stored data progress.

Data signal is passed through MPXD316 to F R0M302
is input. PROM302 has a write signal CPROG
Since is "0", the data signal output from REG315 is written.

Since the address signal at this time is the same as the address when the data signal was read from PROM302, REG31
The data written from 5 is also stored at the same address as when read, and rewriting is completed for one address. When writing is completed, the CPU 304 sets the write signal CPROG to "1".

Thereafter, the PC 311 increments to indicate the next address until the rewriting of the entire PROM 302 is completed, and the CPU 304 repeatedly generates a signal similar to the rewriting operation described above, and the rewriting operation of the entire PROM 302 is completed.

When the CPU 304 reads data from the PROM 302, the mode signal MODE is set to “0” and the refresh signal RE is set to “0”.
Enter "0" for F. The CPU 304 sets the address to be read in the PC 311 and sets the read signal CHD to “0”.
”, the data signal from the PROM 302 is output onto the data bus, and the data signal is obtained from the data bus.

Although this embodiment is an example in which the refresh signal REF is manually generated from the outside, it is also possible to have a timer built into the integrated circuit and periodically generate the refresh signal REF internally. Effects can be obtained.

FIG. 4 shows a block diagram of a FROM according to an embodiment of the second invention. The area inside the dotted line indicates the inside of the integrated circuit.

This embodiment uses an error correction circuit 412 that can detect and correct the error when a 1-bit error occurs in the data signal read from the FROM. In order to correct an error, a signal for correcting the error is required in addition to the data signal.

In this embodiment, the data signal is 8 bits, and the error correction signal is 4 bits.

Therefore, the PROM 401 of this embodiment has a data width of 12 bits. The address signal is input to the address terminal group 402, and is passed through the address buffer 403 to the PROM 40.
1 is entered.

When the write signal PROG is active (“O”), P
A signal instructing data writing to the ROM 401 is inputted to the PROM 401 via an external terminal 404 .

When read signal RD is active (“0”), PRO
This signal instructs M401 to read data, and is input to PROM 401 via external terminal 405.

The refresh signal REF is a signal that instructs rewriting of data in the PROM 401, and when active (“1”) indicates rewriting, and is input from the external terminal 406.

The data signal is input/output from the data terminal group 407. In this embodiment, the bit width of the data signal is 8 bits.

The data output buffer 40°8 is connected to the data terminal group 407, and outputs a data signal as an output buffer when the read signal RD is "0", and the write signal PROG is "0".
It operates as a casting buffer and inputs data signals.

A multiplexer (hereinafter referred to as MPX) 409 inputs the output signals of the data output buffer 408 and the error correction circuit 412, and when the signal REF is "0"', the output signal of the output buffer 408 is input to the output signal of the output buffer 408 and the error correction circuit 412. When “1”,
The output signal of the error correction circuit 412 is output.

The test signal generation circuit 412 is necessary to correct the data signal when a 1-bit error occurs in the data signal (8-bit width) written in the PROM 401, and generates a 4-bit signal from the data signal for correction. This circuit generates a test signal (hereinafter referred to as a test signal), which receives a data signal (8 bits) as input and outputs a test signal (4 bits).

PROM401! The upper 8 bits of Z input the data signal output from the MPX 409, and the lower 4 bits input the test signal output from the test signal generation circuit 410.

The output signal of the upper 8 bits of PROM 401 is input to data output buffer 7408.

The register (hereinafter referred to as REG) 411 has a data width of 12 bits, receives the output signals of the upper 8 bits and lower 4 bits of the PROM 401, and receives the refresh signal REF.
is “L” and the read signal RD is “O”, FROM40
1 output signal is latched, and the refresh signal REF is “
1" and the latched signal is output when the write signal WR is "0".

The error correction circuit 412 receives the output of the REG 411 as an input, and when a 1-bit error occurs in the data written in the PROM 401, outputs a data signal in which the error is corrected using a check signal.

FIG. 5 is a detailed circuit diagram of the test signal generation circuit 410 shown in FIG. 4, which inputs data signals (8 bits) indicated by DO to D7 and outputs test signals indicated by CO to C3. do.

A logical formula for generating test signals C0-C5 from data signal Do-07 is shown. Here, "+" is mod 2 addition (that is, exclusive OR).

C0=DO+03+04 +D6+D7...φ...
・(1) C1=[lO+D1 +04+[1
5+()? C2= D1+D2 D4+0
5+D6C3= 02+D3 D5+
The X0R501, which is realized by XOR (exclusive OR game shown in 06+07th +03+07th 5504) and outputs the check signal CO, receives the data signals Do, D3 . D4. D6. D7 is used as input. The X0Rs 502 to 504 that output the test signals 01 to C3 each receive five data signals as shown in the figure.

FIG. 6 is a detailed circuit diagram of the error correction circuit 412 shown in FIG. If a 1-bit error occurs, it is corrected and DCO to DC? Outputs the corrected signal shown by . Of course, if no error has occurred, the data signals DO to D7 are the corrected signal DC.
It is output to O~DC7.

Exclusive OR gates XOR indicated by 601 to 604 output data signals DO to D according to equation (2) shown below.
7. Inspection signals CO to C3 are input.

These exclusive OR games (XORs 601 to 604) output a code indicating the bit of the data signal in which an error has occurred.

X0R801=[)O[)3+()4 D6+()
? +CO・・・(2)XOR602=DO+DI
D4+D5 D7+ClX0R60
3= D1+D2 D4+D5+D6
C2X0R604= 02+D3 +0
5+06+D7+C3 Table 1 shown below shows X0R601~
The output of X0R604 corresponds to data signals DO to D7,
This is a correspondence table showing which bit is incorrect.

(The following is a blank space) Table I X0R601 to X0R604 (7) Correspondence between output and error bit In FIG. . AND gate 605 to AND gate 612
correspond to error bits DO to D7, and when an error occurs, each AND gate corresponding to each error bit becomes active.

For example, when an error occurs in the DO bit, the outputs of the xOR bits 601 to 604 become "1100", and the AND gate 605 becomes active ("1"), indicating that an error has occurred in the DO bit.

By inverting the erroneous bits, a correct error-corrected signal can be obtained.

The XOR gate indicated by 613 in FIG. 6 receives the Do bit of the data signal and the output of the AND gate 605 as inputs. When an error occurs in the DO bit, the AND gate 605 becomes "1", the output of the XOR gate 613 becomes the inversion of the DO bit, and the DCO bit of the data signal with the error corrected is obtained.

Similar to the XOR gate 613, the XOR gates 614 to 620 are ANDed with bits D1 to D7 of the data signal.
It inputs the outputs of gates 607 to 612 and outputs error-corrected data signals DCI to DC7.

Next, writing of data signals into the PROM 401 will be explained with reference to FIG.

Set refresh signal REF to “0” and address terminal group 4
An address signal is input from 02. The address signal is input to PROM 401 through address buffer 403 and designates PROM 401(7)7 address.

Set the write signal PROG to “0” and set the data terminal group 407
When a data signal is input from the data signal output buffer 74
08, a data signal is input to the upper 8 bits of the PROM 401 through the MPX 409, and the data signal can be written to the specified address. The data signal is also input to the test signal generation circuit 410, and the test signal generation circuit 410 outputs the test signal. A test signal is input to the lower four bits of the PROM 401, and the test signal can be written to a designated address.

Here, the refresh signal REF of MPX409 is “0”
Therefore, the output of data person output buffer 7408 is transferred to PROM4.
01 and is input to the test signal generation circuit 410.

To read a data signal from the PROM 401, the refresh signal REF is set to "0" and an address signal is input from the address terminal group 402. The address signal is input to PROM 401 through address buffer 403 and PRO
Specify the address of M401.

When the read signal RD is set to "0", the data signal of the designated address is output from the upper 8 bits of the PROM 401.

The data signal is passed through the data output buffer 7408 to the data signal terminal group 40? It is output from

Next, FROM40! The case of rewriting data to the memory will be explained with reference to the timing diagram of FIG.

The refresh signal REF becomes “1” when starting rewriting.
”. Since the refresh signal REF is “1”, MP
X409 outputs the output of the error correction circuit 412 to the PROM40.
1 and as a data signal for the test signal generation circuit 410.

Next, an address signal indicating the address at which data in the PROM 401 is to be rewritten is inputted to the address terminal group 402. In FIG. 2, it is indicated by AO.

Furthermore, when the read signal RD is set to “0”, the PROM401
outputs a data signal and a test signal corresponding to the address signal AO.

The REG 411 latches the upper 8-bit data signal and the lower 4-bit test signal from the PROM 401 at the timing when the refresh signal REF is "1" and the read signal RD is "O". The latched data signal and test signal are indicated by ■0 in FIG.

When the read signal RD is set to "1", data reading from the PROM 401 is completed.

By setting the write signal PROG to “0”, the REG411
outputs a data signal and an inspection signal IO.

The data signal and the check signal are input to the error correction circuit 412, and if there is an error in the data signal, the corrected data signal is output, and if there is no error in the data signal, the data signal output from the PROM 401 is output as is.

PROM4 via corrected data signal MPX409
The upper 8 bits of 01 are input to the test signal generation circuit 410. The test signal generation circuit 410 outputs a test signal and P
It is input to the lower 4 bits of the ROM 401.

Since the write signal PROG is "O", the PROM 401 stores the data signal and the test signal IO.

Since the address signal at this time remains the same as the address signal used when the data signal was read from the PROM 401, the data written from the error correction circuit 412 is also stored at the same address as when read, and rewriting for one address is completed.

When writing is completed, set the write signal PROG to “L”
Make it.

When rewriting the next address in PROM 401, a similar signal may be input. In Figure 2,
The next address signal A1, data signal and test signal of REG411 are indicated by 1.

[Effects of the Invention] As explained above, conventionally, it is assumed that PROM data is not retained under high temperatures or after a long period of time, but according to the present invention, data in the PROM is not retained by a signal instructing rewriting. It is possible to rewrite the data written in the FROM cell, and it is also possible to change the period of the signal instructing rewriting, so it is possible to maintain the charge stored in the FROM cell above a certain amount. FROM
The environment in which it can be used can be expanded.

With a built-in error correction circuit, even if an error occurs in the data written in the PROM, the error correction circuit can correct it and rewrite the correct data, resulting in even higher reliability. can.

In addition, in microcomputers with built-in PROM, the CPU
The PROM data can be rewritten automatically under control. Therefore, a microcomputer with a built-in PROM can be more easily incorporated into a set that is to be used at high temperatures or after a long period of time.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a FROM according to a first embodiment corresponding to the first invention of the present application, FIG. 2 is an operation timing diagram of the FROM, and FIG. 3 is a block diagram of a FROM according to a first embodiment corresponding to the first invention of the present application. A block diagram of a microcomputer with a built-in PROM according to an example, FIG. 4 is a block diagram of a FROM with a built-in error correction circuit according to an embodiment corresponding to the second invention of the present application, and FIG. 5 is a circuit diagram of a test signal generation circuit. , Fig. 6 is a circuit diagram of the error correction circuit, Fig. 7 (A) is a cross-sectional view showing the configuration of the PROM memory transistor, and Fig. 7 (B) is the control gate voltage VG and drain current ID of the FROM memory transistor. FIG. 8 is a block diagram of a conventional PROM. 101.309,801...address terminal group, 10
2.310゜403.802・・・・・・Address buffer,
304...CPU, 103,302.
305.307-
------t! L, ctor (SELR. 401.803--------PROM,
5ELW), 10
4゜301゜308゜804゜105, 108゜303, 306゜402, 404~407゜805...External terminal, 314 410 No. 412 ◆ ・Program counter (PC),・Data buffer, ・Test signal generation circuit, ・Error correction circuit, 106.313゜408.806... Data terminal group, 10
7゜807...Data output buffer, 109.31
5゜411・・・・・・Register (REG), 1
10.312゜316.409...Multiplexer (MPX. MPXA, MPXD), 501~504゜601~604゜613~620...XOR circuit, 605~612
・ 701 ψ clarity ・ ・ ・ 702・ Dispute ・ ・ ・ 703 ・ ・ φ φ 704 ・ Sha φ Work ・ 705 ・ φ φ φ ・ ・AND gate, ・・P type substrate, ・ ・source, ・・drain,・・Gate oxide film, ・・・Floating gate, 706・・・・・・・Control gate, 707.708
... Characteristics of control gate voltage VG and drain current ID, RD, CRD... Read signal,
PROG, CPROG...Write signal, MODE
・・・・・・・・・Mode signal, REF, CREF
...Refresh signal.

Claims (2)

[Claims] (1) In an integrated circuit that includes a memory section consisting of nonvolatile memory cells into which data can be electrically written, an address instruction circuit that specifies an address for writing or reading data, and a nonvolatile memory specified by the address instruction circuit. A holding circuit that holds data read from a cell, and a switching circuit that supplies the data held in the holding circuit or external data to a nonvolatile memory cell specified by an address instruction circuit in response to a control signal. An integrated circuit characterized by: (2) In an integrated circuit that includes a memory section consisting of non-volatile memory cells into which data can be electrically written, an address instruction circuit that specifies an address for writing or reading data, and a data correction circuit from the data written to the non-volatile memory cells. A test signal generation circuit that generates test signal data for and writes it into the same nonvolatile memory cell together with the write data, and a test signal generation circuit that generates test signal data and writes the write data and test signal data read from the nonvolatile memory cell specified by the address instruction circuit. a holding circuit that holds the data; a correction circuit that corrects the write data held in the holding circuit based on test signal data when it is different from the data written to the nonvolatile memory cell; and a correction circuit that responds to the control signal. and a switching circuit that supplies output data from a correction circuit or external data to a nonvolatile memory cell designated by an address instruction circuit.