JPH02256314A - Pulse generator - Google Patents

Abstract

PURPOSE:To obtain a pulse width modulation signal by controlling a pulse width in response to a phase difference of the pulse generated from two pulse generating circuits. CONSTITUTION:When the UP mode is designated by a mode designation circuit MD, since a conversion circuit TR outputs a signal of level '1' a signal (a) is inputted to a counter CT2 via a gate circuit GT. The counter CT 2 outputs a signal (d) when the content is 'F' in a hexadecimal numbers to set a flip-flop FF. A counter CT 1 outputs a signal (e) when the content reaches 10 in a hexadecimal number to reset the flip-flop FF. Thus, the phase difference between the signals d, e is gradually increased. In the DOWN mode, since the conversion circuit TR outputs a signal of logical '0' by two pulses of the reference clock (a), the phase difference between the pulses from the counters CT1 and CT2 is gradually decreased. Since the signal (b) in the stop mode is zero by one pulse of the reference clock signal (a), the width of the pulse outputted from the flip-flop FF is unchanged.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is directed to PWM (pulse width modulation).
] The present invention relates to a pulse generator that generates a t i on) signal.

[Prior Art] A PWM signal has been conventionally used as a control signal for controlling the rotation of a motor, controlling the voltage increase of a switching regulator, and the like. That is, it receives signals from equipment such as motors and switching regulators and changes the pulse width of the PWM signal so that the operating state of the equipment is optimized.

In a conventional PWM signal generator, a desired pulse width is set by software using a microcomputer.

[Problem to be solved] When setting the pulse width of the PWM signal using software,
Since high-speed processing cannot be performed, P with a short pulse width
Difficult to obtain WM signal. Therefore, when a high-speed PWM signal is required, the conventional type cannot meet the demand.

An object of the present invention is to obtain a pulse generator that generates a high-speed PWM signal.

[Means for Solving the Problems] A pulse generator according to the present invention includes a first pulse generating circuit that generates pulses of a constant period, and a pulse generating circuit that generates pulses that have a phase different from the pulses generated by the first pulse generating circuit. a second pulse generation circuit; a control circuit that controls the phase of the pulse generated in the second pulse generation circuit; and a control circuit that controls the phase of the pulse generated in the first pulse generation circuit and the second pulse generation circuit. and a third pulse generation circuit that generates pulse width modulated pulses.

[Example] An embodiment of the present invention will be described below based on the drawings.

FIG. 1 shows the configuration of an embodiment.

MD is a mode designation circuit that receives signals from devices such as motors and switching regulators and designates each mode for controlling the pulse width of the PWM signal.

The CTI is a first pulse generating circuit and generates pulses with a constant period. In this embodiment, a hexadecimal counter is used as the first pulse generating circuit, and a reference clock signal (frequency fO) is counted to generate pulses of a constant period.

TR is a conversion circuit, which converts the signal from the first pulse generation circuit CT1 into a predetermined signal corresponding to each signal from the mode designation circuit MD.

GT is a gate circuit which inputs the reference clock signal and the output signal of the conversion circuit TR and outputs the logical product of both signals.

A control circuit CR is constituted by the conversion circuit TR and the gate circuit GT, and controls the phase of a pulse generated in a second pulse generation circuit, which will be described later.

GT2 is a second pulse generating circuit, which generates a pulse having a phase different from that generated by the first pulse generating circuit CTI. In this embodiment, a hexadecimal counter is used as the second pulse generating circuit CT2 to count the output signal of the gate circuit GT.

FF is a third pulse generating circuit, which includes the first pulse generating circuit CTI and the second pulse generating circuit CT2.
P is pulse width modulated according to the phase difference of the pulses generated in
It generates a WM signal. In this embodiment, an R3 type flip-flop is used as the third pulse generating circuit FF, the output signal of the first pulse generating circuit CTI is input to the set input "S", and the output signal of the first pulse generating circuit CTI is input to the reset input "Ro". The output signals of the generation circuit CT2 are respectively input.

Next, the operation of this embodiment will be explained with reference to the time chart shown in FIG. Note that a - f in Fig. 2 are
Each shows the signal waveform at point a%f in FIG. 1.

The mode designation circuit MD receives signals from devices such as motors and switching regulators, and outputs mode designation signals corresponding to each mode that control the pulse width of the PWM signal.

There are three types of modes designated by the mode designation circuit MD: an up mode in which the pulse width of the PWM signal is increased, a down mode in which the pulse width of the PWM signal is decreased, and a stop mode in which the pulse width of the PWM signal is maintained.

Below, the operations when the above three types of modes are specified will be explained respectively. Note that the time charts (A), (B), and (C) shown in FIG. 2 show the up mode, down mode, and stop mode, respectively.

(A) Up mode When the up mode is designated by the mode designation circuit MD, the signal shown in FIG. 2(A) is output from the conversion circuit TR and inputted to one input terminal of the gate circuit GT.

A reference clock signal a having a frequency fO is input to the other input terminal of the gate circuit GT. Since the signal outputted from the conversion circuit TR is always "1m," the reference clock signal a is directly input to the second pulse generation circuit CT2. A)
As shown in C, the count is incremented every time the output signal of the gate circuit GT is input.

When the counter value becomes “F” in hexadecimal,
) is output, and the third pulse generating circuit FF
is set, and its output Q becomes "1". On the other hand, the first pulse generating circuit CTI counts up each time the reference clock signal a is input. When the value of the counter becomes "10" in hexadecimal, the signal e shown in FIG. 2(A) is output, the third pulse generating circuit FF is reset, and its output Q becomes "0°."

With the above operation, from the third pulse generation circuit FF,
A signal f shown in FIG. 2(A) is output as a PWM signal.

In this way, in the up mode, the reference clock M a
A pulse is generated from the second pulse generating circuit CT2 every 16 pulses of the reference clock signal a (Fig. 2 (A) d), and a pulse is generated from the first pulse generating circuit CTI every 17 pulses of the reference clock signal a (Fig. 2 (A) d). Figure 2 (A) e). Therefore, the phase difference between both pulses gradually increases. Since the third pulse generating circuit FF is set and reset by both pulses, the pulse width of the PWM signal output from the third pulse generating circuit FF gradually increases.

(B) Down Mode When the down mode is designated by the mode designation circuit MD, the signal shown in FIG. 2(B) is outputted from the conversion circuit TR and inputted to one input terminal of the gate circuit CAT. A reference clock signal a having a frequency fO is input to the other input terminal of the gate circuit GT. The signal S output from the conversion circuit TR has a period of 0 degrees corresponding to two pulses of the reference clock signal a. Therefore, in the period of 0 degrees, the signal S output from the conversion circuit TR has a period of 2 pulses of the reference clock signal a. Generation circuit C
No clock pulse is input to T2. Therefore, in the second pulse generating circuit CT2, as shown in C of FIG. 2(B), the operation of counting the period corresponding to two pulses of the reference clock signal a is not performed. When the value of the counter becomes "F" in hexadecimal, the signal d shown in FIG. 2(B) is output, the third pulse generating circuit FF is set, and its output Q becomes "1". On the other hand, the first pulse generation circuit CT
1, the count is incremented every time the reference clock signal a is input. When the value of the counter reaches "10" in hexadecimal, the signal e shown in FIG.
"become.

With the above operation, from the third pulse generation circuit FF,
A signal f shown in FIG. 2(B) is output as a PWM signal.

In this way, in down mode, 2! Semi-click signal a
A pulse is generated from the second pulse generating circuit CT2 every 18 pulses of the reference clock signal a (Fig. 2 (B) d), and a pulse is generated from the first pulse generating circuit CTI every 17 pulses of the reference clock signal a (Fig. 2 (B) d). Figure 2 (B) e). Therefore, the phase difference between both pulses gradually decreases. Third pulse generation circuit F
Since F is set and reset by both pulses,
The pulse width of the PWM signal output from the third pulse generating circuit FF also gradually decreases.

(C) Stop Mode When the stop mode is designated by the mode designation circuit MD, the signal shown in FIG. 2(C) is outputted from the conversion circuit TR and inputted to one input terminal of the gate circuit GT. A reference clock signal a having a frequency fO is input to the other input terminal of the gate circuit GT. The signal S output from the conversion circuit TR is "0°" for a period corresponding to one pulse of the reference clock signal a.Therefore, in the period when the signal S output from the conversion circuit TR is "0", the second pulse Generation circuit C
At T2, no clock pulses are applied manually.

Therefore, in the second pulse generating circuit CT2, as shown in FIG.
), the counting operation is not performed for a period corresponding to one pulse of the reference clock signal a. When the value of the counter becomes "F" in hexadecimal, the signal d shown in FIG. 2(C) is output, the third pulse generating circuit FF is turned on, and its output Q becomes "1". On the other hand, the first pulse generating circuit CT1 counts up each time the reference clock signal a is input. The counter value is in hexadecimal “
When the signal reaches 10#, the signal e shown in FIG. 2(C) is output, the third pulse generating circuit FF is reset and sorted, and its output Q becomes 0''.

With the above operation, from the third pulse generation circuit FF,
A signal f shown in FIG. 2(C) is output as a PWM signal.

In this way, in the stop mode, the reference clock signal a
A pulse is generated from the second pulse generating circuit CT2 every 17 pulses of the reference clock signal a (Fig. 2 (C) d), and a pulse is generated from the first pulse generating circuit CTI every 17 pulses of the reference clock signal a (Fig. 2 (C) d). Figure 2(C)e). Therefore, the phase difference between both pulses does not change, and the pulse width of the PWM signal output from the third pulse generation circuit FF also does not change.

As mentioned above, the pulse width of the PWM signal corresponds to the up mode, down mode, and stop mode.
They are respectively increased, decreased and held to perform pulse width modulation of the PWM signal.

[Effect] In the present invention, since the pulse width of the PWM signal is controlled according to the phase difference between the pulses generated from the two pulse generation circuits,
A high-speed PWM signal can be generated with a simple circuit configuration.

[Brief explanation of drawings]

FIG. 1 is an electric circuit diagram showing an embodiment of the present invention, and FIG. 2 is a time chart showing the operation of FIG. 1. CTI...First pulse generation circuit CT2...Second pulse generation circuit CR...Control circuit FF...Third pulse generation circuit or higher

Claims (1)

[Scope of Claims] A first pulse generating circuit that generates pulses with a constant period; a second pulse generating circuit that generates pulses with a phase different from that of the pulses generated by the first pulse generating circuit; a control circuit that controls the phase of the pulse generated in the pulse generation circuit; and a third control circuit that generates a pulse width modulated according to the phase difference between the pulses generated in the first pulse generation circuit and the second pulse generation circuit. A pulse generator consisting of a pulse generating circuit of