JPH02255911A - Tablet unified with display - Google Patents

Abstract

PURPOSE:To obtain a tablet unified with a display which can be easily produced at a low cost and is advantageous in terms of space by producing a matrix panel having the row and column electrodes and using the panel for both display and detection of the coordinates. CONSTITUTION:A tablet consists of a thin film EL matrix panel 101 containing the row electrodes y1 - yn and column electrodes x1 - xn, a row electrode driver 102, a column electrode driver 103, an x-coordinate detecting part 108, a y-coordinate detecting part 107, and a pencil type conductor 105. In a display mode, the scan pulses are successively supplied to the row electrodes one by one from the driver 102. At the same time, the driver 103 supplies the voltage to the column electrodes in response to the display data for each supply of the scan pulse. In a row coordinate detection mode, the scan pulses are successively supplied to the row electrodes and a detecting scan pulse is supplied to the part 108 with connection of the electrostatic capacity when a contact is secured between the conductor 105 and an optional position of the panel 101. In the same way, the column coordinates are detected in a column coordinate detection mode. In such a constitution, the coincidence is secured between entire display and input screens with accuracy of a single display picture element. Thus a tablet unified with a display is easily obtained at a low cost.

Description

[Detailed description of the invention]

[Industrial Application Field] The present invention relates to a display-integrated tablet in which a tablet for inputting coordinates is integrated with a display. [Prior Art] Conventionally, as shown in FIG. 18, a display-integrated tablet is constructed by forming a display 51 and a tablet 52 separately and independently, and then bringing them into close contact with each other to form an integral unit. . Here, for example, an EL (electroluminescence) display element is used as the display 51, and a capacitive coupling type is used as the tablet 52. In addition, in FIG. 18, 53 is a pen for scanning pulse detection. [Problem B to be Solved by the Invention] According to the configuration as described above, in order to obtain position detection accuracy at the one-pixel level, the display surface of the display δ1 and the human-powered surface of the tablet 52 are divided into one display pixel. Manufacture was difficult because it was necessary to match the entire surface with precision. For example, in the case where an EL display element is used as the display 51 and a capacitive coupling type is used as the tablet 52, both the display δ1 and the tablet 52 are configured with electrodes arranged in a matrix. , each of which is equipped with a driver and the like having similar functions, which results in wasted circuits, resulting in increased costs and disadvantages in terms of space. Therefore, an object of the present invention is to provide a display-integrated tablet that can be manufactured easily at low cost and is advantageous in terms of space.

[Means for Solving the Problems] The present invention provides a matrix panel having row electrodes and column electrodes, a row electrode driver, a column electrode driver, a row coordinate detection section, a column coordinate detection section, and a detection conductor. In the display mode, scanning pulses are sequentially supplied to the row electrodes of the panel from the row electrode driver in one electrode pattern, and
Each time a scanning pulse is sequentially supplied to the row electrodes of the panel, a voltage corresponding to the display data is simultaneously supplied from the column electrode driver to the column electrodes of the panel, and in row coordinate detection mode, the row electrode driver sequentially supplies the voltage to the row electrodes of the panel. A scanning pulse is supplied, and the scanning pulse is detected by capacitive coupling by contacting a detection conductor with an arbitrary position on the panel.The scanning pulse is supplied to a row coordinate detection section, and the row coordinate of the detection conductor contact position is detected, In the column coordinate detection mode, scanning pulses are sequentially supplied to the column electrodes of the panel from the column electrode driver, and the scanning pulses are detected by capacitive coupling by contacting the detection conductor with any position on the panel. The column coordinates of the contact position of the detection conductor are detected. Further, in the present invention, the display mode period and the coordinate detection mode period are provided alternately in a time-division manner. [Function] In the above configuration, since the panel is used for both display and coordinate detection, the display surface of the display and the human input surface of the tablet are ensured to match across the entire surface with an accuracy of one display pixel. , manufacturing becomes easy. In addition, since the panel is used for both display mode and coordinate detection mode, and the row electrode driver and column electrode driver are commonly used, unnecessary circuits can be eliminated, making it possible to configure the structure at low cost, and taking up less space. It is also advantageous. In addition, by providing the display mode period and the coordinate detection mode period alternately in a time-sharing manner, scanning pulses can be detected without being affected by interference from various signals necessary for display drive during the coordinate detection mode period. This makes it possible to perform coordinate detection well. [Example 1] Hereinafter, an example of the present invention will be described with reference to FIG. 1. This example is an example in which a thin film EL matrix panel is used as the matrix panel. In the figure, 101 is a thin film EL matrix panel, Vl, V2. ...+Vn is the row electrode, xl
, x2. ..., XI are column electrodes. Further, 102 is a row electrode driver, and its plurality of output terminals are respectively connected to the row electrodes y1, 3/2.
...+ connected to yn. Further, 103 is a column electrode driver, and its plurality of output terminals are the column electrodes xi, ! of the panel 101, respectively. 2゜..., connected to X-. These row electrode drivers 102 and column electrode drivers 10
3 is controlled by a timing generation circuit 104. As shown in FIG. 2, in the display mode and the row (y) coordinate detection mode, the row electrodes yt, V2. ...Scanning pulse Py is sequentially supplied to yn in units of one electrode. At this time, column electrode driver 1
03 to column electrodes xI, x2. . . . A voltage VD corresponding to the display data SD is simultaneously supplied to xi for every l scanning line. In the column (X) coordinate detection mode, the column electrodes xl, x2 . ...
- A scanning pulse Px is sequentially supplied to xm. Therefore, the display mode and the row coordinate detection mode are in the same drive state, and the row coordinate detection mode is simultaneously set in the display mode. As shown in FIG. 2, for each frame, a period of display mode (row coordinate detection mode) and a period of row and seat ring detection mode are provided in a time-sharing manner. Note that the polarities of the scanning pulses Py and Px are respectively inverted every frame.
y2. ..., yn is ±190V, column electrode x1. x
2. ..., xm are selectively supplied with ±30v, respectively. And the EL emission threshold voltage is ±200V
On the other hand, ±220V is supplied to the light emitting pixel portion with the polarity alternately inverted. In the above configuration, in the display mode, the row electrode y1+
The scanning pulse py is sequentially supplied to the column electrodes xLx2 .
=..., the voltage VD is 1 in xm corresponding to the display data SD
Since the signals are supplied simultaneously for each scanning line, the display is driven by line sequential scanning, and an image corresponding to the display data SD is displayed. Further, 1015 is a pencil-shaped conductor (hereinafter referred to as "ben"), and by bringing this ben 105 into contact with an arbitrary position on the panel 101, a scanning pulse is detected by capacitive coupling. The scanning pulse detected by this sensor 105 is supplied via an amplifier 106 to a row coordinate detector 107 and a column coordinate detector 10 . In the second case, the row coordinate detection unit 107 is configured with a counter, for example, and is reset by being supplied with a reset signal from the timing generation circuit 104 before the clock is supplied, and the row coordinate detection unit 107 of the row electrode V1 of the panel 101. V2.・
A clock is supplied and counted at the timing when the scanning pulse PV is sequentially supplied to +yn, and the counting operation is stopped at the scanning pulse py detected by the ben 105. Therefore, the row coordinate detection unit 107
, a count value corresponding to an arbitrary position on the panel 101 touched by the ben 105 is obtained as a row coordinate output. The column side coordinate detection section 108 is also configured with a counter, for example, and is reset by being supplied with a reset signal from the timing generation circuit 104 before being supplied with a clock.・War φ6
．． A clock is supplied and counted at the timing when the sequential scanning pulse Px is supplied to Ben 10.
The counting operation is stopped at the scanning pulse Px detected at 5. Therefore, the count value corresponding to any position on the panel 101 touched by the ben 105 is obtained from the row/seat ring detection unit 108 as the row/seat type output. FIG. 3 is a diagram showing a specific configuration of the example in FIG. 1. In FIG. 3, parts corresponding to those in FIG. 1 are designated by the same reference numerals. In the figure, 121 is the row electrode 3'll of the panel 101.
M2. ..., a shift register having the number of stages corresponding to the number of electrodes yn; 122 a switch circuit having changeover switches 221 to 22n in a number corresponding to the number of electrodes; 123 a switch circuit having a number of N channels corresponding to the number of electrodes; FET23A1-23An and N-channel FET23
It is a gate circuit having B1 to B23Bn, and these shift register 121, switch circuit 122, gate circuit 1
23 constitutes a row electrode driver 102. That is, the n-stage output terminal of the shift register 121 is
Changeover switches 221 to 2 of the switch circuit 122, respectively
It is connected to the movable terminal of 2n, and this changeover switch 221~
The fixed terminals on the a side of 22n are connected to gate circuits 123, respectively.
are connected to the gates of N-channel FETs 23A1 to 23An, and their b-side fixed terminals are connected to gate circuits 12 and 12, respectively.
It is connected to the gates of N-channel FETs 23B1 to 23Bn of No. 3, and its a-side fixed terminal is electrically floating. Further, the drains of the N-channel FETs 23A1 to 23An are each connected to the voltage [Vy+ (+190 V), and the sources of the N-channel FETs 23B1 to 23Bn are respectively connected to the power source vy·(-190 V). The sources of the N-channel FETs 23A1-23An are connected to the drains of the N-channel FETs 23B1-23Bn, respectively, and the respective connection points are connected to the panel 1010 row electrodes y1. y2. ...Connected to yn. In this case, in display mode and line coordinate detection mode,
An enable signal (shown as y enable in FIG. 4C) supplied from the timing generation circuit 104 to the switch circuit 122 causes the changeover switch 22 to be activated every frame.
1 to 22n are connected to the a side or the b side. In addition, the timing generation circuit 104 supplies data for the scanning pulse Py (shown as y data in FIG. 4A) to the shift register 121, and the timing generation circuit 104 supplies the shift register 121 with clock pulse data (shown as y data in FIG. 4A). J
(shown as y clock). Therefore, in a certain frame, the changeover switches 22 through 22n of the switch circuit 122 are connected to the a side, and the N-channel FET is connected to the output terminal of the n stage of the shift register 121.
No. 18 is sequentially supplied to the gates of 23A1 to 23An and turned on, and the row electrodes y1. y2.
In the 0th-order frame in which the scanning pulse Py of 11ffVy+ is sequentially supplied to +Vn for each l electrode, the changeover switches 221 to 22n of the switch circuit 122
is connected to the b side, and signals are sequentially supplied from the n-stage output terminal of the shift register 121 to the gates of the N-channel FETs 23B1 to 23Bn to turn them on, and a scanning pulse is applied to the row electrodes yLy2+ ... + yn of the panel 101. Power supply Vy- is sequentially supplied to each electrode as Py. In the column coordinate detection mode, the enable signal (shown as y enable in FIG. 4C) supplied from the timing generation circuit 104 to the switch circuit 122 connects the changeover switches 22 to 22n to cal. Therefore, row electrode V1. of panel 101. yL・Url・Φ+
Power supplies Vy+ and Vy as scanning pulses PV are applied to yn.
− is not supplied. Further, 131 is a shift register having a number of stages corresponding to the number of electrodes of the column electrodes xl, x2゜..., XI of the panel 101, 132 is a latch circuit having a number of stages corresponding to the number of electrodes, and 133 is the number of electrodes. A switch circuit having a number of changeover switches 33+ to 33m corresponding to 134
is the number of N-channel FETs 34A corresponding to the number of electrodes.
1-34Am and N-channel FET34B1-348
m, and these shift registers 1
31, the column electrode driver 103 is composed of the opening circuit 132, the switch circuit 133, and the gate circuit 134. In other words, the output terminal of the shift register 1310m stages is
A switch circuit 133 via a latch circuit 132, respectively.
It is connected to the movable terminal of the changeover switch 331-33m,
The a-side fixed terminals of the changeover switches 33+ to 33g+ are connected to the N-channel FET 34 of the gate circuit 134, respectively.
It is connected to the gates of A1 to 34Am, and its fixed terminal on the b side is connected to the N-channel FET3 of the gate circuit 134, respectively.
Connected to the gates of 4BI to 34B-. In addition, the drains of N-channel FET34A1 to 34Am are each connected to the power supply VX+ (+30V), and the drains of N-channel FET34A
The sources for 4B1 to 34Bm are each from i! RVx-(-
30V). And N channel FET34
The sources of A1 to 34Am are each N-channel FET.
34B1 to 34Bo+, and each connection point is connected to the row electrodes x 1 + x 2 of the panel 101.
+..., connected to X+a. In this case, in display mode and line coordinate detection mode,
An enable signal (shown as X enable in FIG. 4G) supplied from the timing generation circuit 104 to the switch circuit 133 causes the changeover switch 33 to be activated every frame.
+ to 33 A are connected to the b side or the a side. Further, the timing generation circuit 104 supplies the display data SD (shown as X data in FIGS. 4E and K) to the shift register 131, and the timing generation circuit 104 supplies the shift register 131 with a clock (FIG. 4F and L). (shown as an X clock) is supplied to the clock. Then, m for one scanning line is stored in a register with 1310m stages of shift registers.
Each time display data SD is set, a load signal (shown as X load in FIGS. 4H and 4J) is supplied from the timing generation circuit 104 to the latch circuit 132. Therefore, in a certain frame, the changeover switches 33+ to 33m of the switch circuit 133 are connected to the b side, and the output terminals of the m stages of the shift register 131 select the predetermined N-channel FETs 34B1 to 34B+a corresponding to the display data SD.
A signal is simultaneously supplied to the gates of each scanning line to turn on the gates of the predetermined column electrodes XI! corresponding to the display data SD of the panel 101. At the same time, an electric current [V x- is supplied to X2+ . . . , xm as a voltage VD. In the next frame, the changeover switches 331 to 33m of the switch circuit 133
is connected to the a side, and a predetermined N channel F corresponding to the display data SD is connected from the m-stage output terminal of the shift register 131.
A signal is simultaneously supplied to the gates of E T 34A1 to 34Am for each scanning line to turn them on, and a predetermined column electrode xl*x2 corresponding to the display data SD of the panel 101 is turned on.
* ◆..., power supply Vx as voltage VD to xm at the same time
+ is supplied. In addition, in the column coordinate detection mode, the timing generation circuit 1
04 to the switch circuit 133 (shown as X enable in FIG. 4G), l
The changeover switches 33+ to 33m are connected to the a side or the b side for each frame. In addition, the timing generation circuit 10
4 supplies the data for the scanning pulse Px (shown as X data in FIG.
1 is supplied with a clock (shown as X clock in FIG. 4F). Note that as a result of the load signal (shown as X load in FIG. 4H) being continuously supplied from the timing generation circuit vli104 to the latch circuit 9132, a transparent operation is performed. Therefore, in a certain frame, the Swiss-Sochi circuit 133
The changeover switches 331 to 33m are connected to the b side, and the N channel FE is connected to the output terminal of the m stage of the shift register 131.
A signal is sequentially supplied to the gates of T34B1 to T34B1 to T34B348m to turn them on, and the column electrodes xi, x2 . The heavy RV is sequentially applied to the scanning pulse Φe, xm as the scanning pulse Px.
x- is supplied. In the next frame, switch circuit 1
The changeover switches 331 to 33m of 33 are connected to the a side,
Signals are sequentially supplied from the m-stage output terminals of the shift register 131 to the gates of the N-channel FETs 34A1 to 34Am to turn them on, and the row electrodes xl of the panel 101 are turned on. x2. . . , xm are sequentially supplied with the power supply Vx+ as the scanning pulse Px. Thus, in the display mode, the row electrodes y+, S'2
+... yn is sequentially supplied with a scanning pulse Py for each electrode, and the column electrodes xl, x2 . ...,
A voltage VD corresponding to the display data SD is simultaneously supplied to X- for each scanning line, and the display is driven by line sequential scanning.
An image corresponding to the display data SD is displayed. Furthermore, the scanning pulse detected by the pen 105 is transmitted to the amplifier 10.
6, a row coordinate detection unit 107 consisting of a counter
and is supplied to the column coordinate detection section 108 as a count stop signal. The row coordinate detection unit 107 receives the same clock as the clock supplied to the shift register 121 (shown as the X clock in FIG.
4, and a reset signal (y
It is in a reset state before entering the row coordinate detection mode when a signal (shown as a reset) is supplied. Therefore, when the row coordinate detection mode is entered, the clock starts counting and ends when the scanning pulse py is detected by the pen 105.
A count value corresponding to an arbitrary position on the panel 101 where 05 is touched is obtained as a row coordinate output. Further, the column coordinate detection unit 108 is supplied with the same clock as the clock supplied to the shift register 131 (shown as the X clock in FIG. 4F) from the timing generation circuit 104, and a reset signal (I It is in the reset state before entering the column coordinate detection mode by supplying X reset (shown as X reset) to the column coordinate detection mode. Therefore, when the column coordinate detection mode is entered, the clock starts counting operation, and when the scanning pulse Px is detected by the pen 105, the counting operation ends. A count value corresponding to an arbitrary position is obtained as a column type output. In addition, in FIG. 3, 104a is a RAM in which display data SD is written. As described above, according to this example, since the panel 101 is used for both display and coordinate detection, the display surface of the display and the human input surface of the tablet are reliably matched over the entire surface with an accuracy of one display pixel. , the process and labor of matching the display surface of the tablet with the input surface of the tablet is no longer required.
It can be easily manufactured. In addition, since the panel 101 is used for both the display mode and the coordinate detection mode, and the row electrode driver 102 and column electrode driver 103 are used in common, there is no need for unnecessary circuits, and the configuration can be made at low cost. It can also be advantageous. By the way, in the example in FIG. 1, when the row coordinate detection mode is entered, the display mode is simultaneously set, and when the pen 105 detects the scanning pulse py, various signals necessary for display drive in addition to the scanning pulse py may interfere. There is a possibility that the scanning pulse Py is detected as a signal and is buried in the interference signal, making it impossible to perform coordinate detection satisfactorily. In order to eliminate the influence of such interference signals, a configuration as shown in FIG. 5 can be considered. In FIG. 5, parts corresponding to those in FIG. 1 are designated by the same reference numerals, and detailed explanation thereof will be omitted. In this example, in addition to the pen 106 for detecting scanning pulses, a pen 111 for canceling interference signals is provided. pen 1
05 is touched at any position on the panel 111, and this pen 1
The output signal of 05 is supplied to the non-inverting input terminal of differential amplifier 113 via buffer 7 amplifier 112. Further, the pen 111 is brought into contact with the panel 101 at a position that does not affect the display, in the example shown, the bottom surface, and the output signal of this pen 111 is supplied to the inverting input terminal of the differential amplifier 113 via the buffer amplifier l'14. . The output signal of this differential amplifier 113 is transmitted to the row coordinate detection section 107 and the column coordinate detection section 10.
supplied on the day. In this case, in the row coordinate detection mode, the pen 105 detects interference signals caused by various signals necessary for display driving in addition to the scanning pulse PV, and the pen 111 detects interference signals caused by various signals necessary for display driving. is detected, the interference signal contained in the output signal of the differential amplifier 113 is reduced. The feedback resistor 113a of the differential amplifier 113 is connected to the pen 105.
and a variable resistor for adjusting the level of the interference signal detected by the pen 111 so that the level of the interference signal included in the output signal from the differential amplifier 113 is minimized. In this way, according to the example in FIG. 5, in the row coordinate detection mode, the interference signal contained in the output signal of the differential amplifier 113 is reduced, the scanning pulse py can be detected well, and the influence of the interference signal is almost eliminated. Coordinate detection can be performed satisfactorily without any interference. Note that, as shown in FIG. 6, the method of reducing interference signals caused by various signals necessary for display driving using the two pens 105 and 111 requires that the display 61 and tablet 52 be operated separately and independently. Of course, the present invention can also be applied to a structure that is formed in one piece by bringing them into close contact with each other. Next, another embodiment of the present invention will be described with reference to FIG. In this example, a thin film EL matrix panel is used as the matrix panel, and a display mode period and a coordinate detection mode period are provided alternately in a time-sharing manner. In the figure, 201 is a thin film EL matrix panel, which is SII* V2. ...+5'n are row electrodes, xl, x2 . ..., xra are column electrodes. Further, 202 is a row electrode driver, and its plurality of output terminals are connected to the row electrodes y1, V2, . −
... + Connected to yn. Further, 203 is a column electrode driver, and its plurality of output terminals are respectively connected to the column electrodes x1.203 of the panel 201. x2゜・φ dispute・, connected to XI. These row electrode drivers 202 and column electrode drivers 20
3 is controlled by a timing generation circuit 204. As shown in FIG. 7, in the display mode, the row electrode driver 202 connects the row electrodes 3'lt y2+ .
A scanning pulse py is sequentially supplied to the column electrodes X1, x2 . ...
A voltage vSO corresponding to the display data SD is simultaneously supplied to xII+ for each scanning line. In addition, in the row coordinate (X coordinate) detection mode, the row electrode driver 202 selects the row electrode yl+yL..."
A scanning pulse Py' is sequentially supplied to yn. In this case, the pulse width of the scanning pulse Py' is widened, and the scanning pulse Py' is simultaneously supplied to a plurality of adjacent electrodes, for example, 20 electrodes among the row electrodes 3/I, y2+..., yn. scanned sequentially. In addition, in the column coordinate (X coordinate) detection mode, the column electrode driver 203 detects the column electrode x l + x 2 + ・
...The scanning pulse Px' is sequentially supplied to the fist and xm. In this case, the pulse width of the scanning pulse Px' is also widened, and the column electrodes xI, x2 . . . . A plurality of adjacent electrodes, for example, 20 electrodes of the XtS are sequentially scanned with the scanning pulse Px' being simultaneously supplied. The display mode period, the row coordinate detection mode period, and the column coordinate detection mode period are provided in each frame in a time-sharing manner. Note that the order is not limited to the illustrated example and is arbitrary. Here, the polarity of the scanning pulse PV in the display mode is
It is inverted every frame. In addition, the scanning pulse Py'Px' in the coordinate detection mode
Although it is desirable that the polarity of the pulses be reversed every frame, it may also be a unipolar pulse to simplify the circuit. In this case, lower voltage is better, but
If the S/N is too low, the scanning pulses Py', Px'
becomes unable to be detected. For example, in display mode, the emission equivalent voltage is +2
00v, row electrode Vl+V2. ...yn
+215V or -165V as scanning pulse py
, column electrode xll X2. ...Voltage VS on skewer/rll
+50V or OV is selectively supplied as D, +215V to the light-emitting pixel part and +165V to the non-light-emitting pixel part.
are supplied with the polarity alternately inverted every frame. In addition, in the row coordinate detection mode, the row electrode 5'l
+ V2゜...+ yn scan pulse p y /
In the column coordinate detection mode, the column electrodes xl, x2 . ...e, xr
+25V is supplied to the scanning pulse PX'. In the above configuration, in the display mode, the row electrodes! 'l+
A scanning pulse py is sequentially supplied to y2+, yn, one electrode at a time, and the column electrode xl. x2. Since the voltage vSO corresponding to the display data SD is simultaneously supplied to the fist . In addition, 205 is a pencil-shaped conductor (hereinafter referred to as "pen")
By bringing this pen 205 into contact with an arbitrary position on the panel 201, a scanning pulse is detected by capacitive coupling. In this case, as mentioned above, in the coordinate detection mode,
A scanning pulse P ``j'+ is applied to multiple adjacent electrodes at the same time.
Since it is sequentially scanned while P x' is supplied,
The level of the detection signal of the pen 206 increases compared to when the scanning pulse PV'Px' is supplied to only one electrode. This will be explained in detail with reference to FIG. In the figure, 41 is a pencil-shaped conductor (hereinafter referred to as "pen"), and 42 is a glass plate of a thin 11 IEL matrix panel. 43 is a matrix electrode, which originally consists of 2N row electrodes and column electrodes, but to simplify the explanation, 1
Only layers are shown. 44 is a switching switch for scanning;
5 is a power supply for scanning pulses, and 46 is a human power impedance of an amplifier (amplifier 206 in FIG. 6) for detecting scanning pulses. As shown in the figure, a capacitor exists between the pen 41 and the electrode 43, and its capacitance is set to Ci corresponding to the electrode number.
In this case, it is assumed that it is grounded, and when l≦J≦1+3, it is connected to the electric fi 45. Note that the number of electrodes 43 is n, and ]≦
J≦n. FIG. 9 shows an equivalent circuit in this case. Here, CVS = Ci+ Ci+f+ Ci+2+ Ci+
3CGND= CII C2+・-+ Ci-1+ C
: +4+・-+ Cn, and the detection signal VS by the pen 41 is as follows if l ZinlP 1/(,1CGNO is selected. IZinl is the magnitude of the input impedance 46. Here, VS is the voltage value of the power supply 45, Co is the total capacitance formed between the pen 41 and the electrode 43, and CvS + CGND
It is. As is clear from equation (1), in the method of supplying the electric current 45 to the electrodes 43 one by one, when n is several hundred,
Since CVS<<Co, the detection signal VS is small, making it difficult to detect the scanning pulse. However, if the number of electrodes 43 to which power 45 is simultaneously supplied is increased as in this example, CvS increases accordingly, the detection signal VS increases, and scanning pulses can be easily detected. In this case, the capacitance Ci of the capacitor formed by the electrodes 43 becomes smaller as the distance from the pen 41 increases, as shown in FIG. 10. For example, the electrode pitch is 0.3 mm, the glass thickness is 2. In the case of 4 mm, the effect can be ignored in areas farther away than near the 10 left and right electrodes. However, the number of electrodes 43 to which the power source 45 is simultaneously supplied only needs to be 20, and even if the number is increased beyond that, the effect of increasing the level of the detection signal will not be obtained. In FIG. 6, the detection signal of this pen 205 is
The detection signal VS from this amplifier 206 is supplied to a comparator 207 and compared with a reference voltage Vr. Amplifier 20 of detection signal of pen 205
The output voltage VS of the pen 205 is as shown in FIG.
and decreases in approximately inverse proportion to the distance d between the glass plate and the glass plate. The reference voltage Vr is set equal to the level of the detection signal VS when the distance d is dO. As will be described later, the distance do is the position at which the coordinate detection operation begins, is determined in advance in consideration of operability, and is set to one layer, for example. The pen 205 is on glass (glass thickness = 2.4mm+), that is, d=2, 4+w
When @, the detection signal VS becomes 3V, and when d = 4n+m, the detection signal VS becomes IV. Therefore, in this case,
If Vr = 2V, do = 3.41, and the distance from the glass plate surface is 1 mn+. This comparator 207 outputs a high level "l" signal when the detection signal VS is greater than the reference voltage Vr, and outputs a low level "0" signal when the -force detection signal vs is less than the reference voltage Vr. . The output signal of this comparator 207 is then supplied to the AND circuit 20. Further, the detection signal VS from the amplifier 206 is supplied to the peak time detection circuit 209, and the detection signal VS from the amplifier 206 is supplied to the peak time detection circuit 209.
From 09 onwards, the high level "I" is set at the peak of the detection signal vs.
II signal is output, and at other times, a low level 110'' signal is output.Then, the output signal of this peak point detection circuit 209 is supplied to an AND circuit 208. Signal VS is reference voltage Vr
At the peak of the detection signal VS, a signal of high level "1" is output, and at other times, a signal of low level "'0" is output. This and times N2
The output signal of O3 is supplied to a row coordinate detection section 210 and a column coordinate detection section 211. In this case, the row coordinate detection unit 21
0 is configured by a counter, for example, and is reset by being supplied with a reset signal from the timing generation circuit 204 before entering the row coordinate detection mode, and the row electrode $1'll yL of the panel 201 y
A clock is supplied and counted at the timing when the scanning pulse Py' is sequentially supplied to n, and the counting operation is stopped at the timing when the output signal of the AND circuit 208 becomes high level "1". Therefore, from the row coordinate detection unit 210, the panel 205 that is touched by the pen 205
A count value corresponding to an arbitrary position of 1 is obtained as a row coordinate output. Further, the column coordinate detection section 211 is also configured as a counter, for example, and is reset by being supplied with a reset signal from the timing generation circuit 204 before entering the column coordinate detection mode, and the column electrodes xi, x2 .・
..., a clock is supplied and counted at the timing when the scanning pulse Px' is sequentially supplied to xm, and
The counting operation is stopped at the timing when the output signal of the AND circuit 208 becomes high level "1". Therefore, the column coordinate detection unit 211 obtains a count value corresponding to an arbitrary position on the panel 201 touched by the pen 205 as a column detection output. FIG. 12 is a diagram showing a specific configuration of the example shown in FIG. 1st
In FIG. 2, parts corresponding to those in FIG. 6 are designated by the same reference numerals. In the figure, 221 is the row electrode S/1. of the panel 201.
y2+..., a shift register having the number of stages corresponding to the number of electrodes yn, 222 is an AND circuit 2A1-2An corresponding to the number of electrodes, exclusive NOR circuit 2E1-2En% N-channel FET 2N1-2Nn
and a driver having P channel FETs 2PI to 2Pn, etc., 223 is a power supply Vw+ (+215V), a ground (OV
) and voltage [1/2 VD (+25V), 224 is a changeover switch for switching voltage [Vw-(-165V)
) and ground (Ov), and these shift register 221, driver 222,
Row electrode driver 2 by changeover switches 223 and 224
02 is configured. That is, the n-stage output terminal of the shift register 221 is
They are connected to the input sides of AND circuits 2A1 to 2An of the driver 222, respectively, and the output sides of these AND circuits 2A1 to 2An are connected to exclusive NOR circuits 2E1 to 2E, respectively.
n, and the output sides of these exclusive NOR circuits 2E1 to 2En are each N-channel FET.
It is connected to the gates of 2N1 to 2Nn, and also to the gates of P channel FETs 2PI to 2Pn. Further, the sources of the P-channel FETs 2PI to 2Pn are each connected to a movable terminal of a changeover switch 223, a fixed terminal on the a side of this changeover switch 223 is connected to the voltage Rv+, and a fixed terminal on the b side is grounded. The fixed terminal on the C side is connected to the power supply 1/2VD. The switching of this changeover switch 223 is controlled by the timing generation circuit 204. Further, the sources of the N-channel FETs 2N1 to 2Nn are each connected to a movable terminal of the changeover switch 224. The fixed terminal on the a side of this changeover switch 224 is connected to the electric power RV w-, and the fixed terminal on the b side is grounded. The switching of this changeover switch 224 is controlled by the timing generation circuit 204. The drains of the N-channel FETs 2N1 to 2Nn are connected to the drains of the P-channel FETs 2P1 to 2Pn, respectively, and the respective connection points are connected to the row electrodes 5'L y2. of the panel 201. ” ” ” ”t Connected to Vn. Note that a diode is connected between the drain and source of each of the N-channel FETs 2N1 to 2Nn and the P-channel FETs 2PI to 2Pn. In this case, in the display mode, the timing generation circuit 204
The enable signal (first
(shown as y enable in Figures C and Q) is supplied. In a certain frame, the changeover switch 223 is connected to the a side and the voltage RV w+ is supplied to the sources of the P channel FETs 2PI to 2Pn (as shown in FIG. 13E), and the changeover switch 224 is connected to the b side and Channel FET
The sources of 2NI to 2Nn are grounded (shown in Figure 13F), and the inversion/non-inversion control 11p (?
(shown as inverted/non-inverted) is set to low level "0". On the other hand, in the next frame, the changeover switch 223 is connected to bm, and the sources of P-channel FETs 2P1 to 2Pn are grounded (as shown in FIG. 13E), and the changeover switch 224 is connected to the a side, and the sources of P-channel FETs 2P1 to 2Pn are connected to A power supply Vv- is connected to the source of (as shown in FIG. 13F)
, inversion/non-inversion control (No. 8 is set to high level "1". In addition, the timing generation circuit 204 controls the shift register 2
21 is supplied with data for the scanning pulse Py (shown as y data in FIG. 13A), and the clock (13th
A clock (shown as a y clock) is supplied to Figures B and N. The data for this scanning pulse y includes the row electrode yl,
V2. ..., yn are sequentially scanned one by one, so that the high level "l" continues for l clocks. Therefore, in a certain frame, P channel FET2P
A low level II O" signal is sequentially supplied to the gates of 1 to 2Pn, turning them on, and the power output 8iiiy1 of the panel 201 is turned on.
．． y2. . In the next frame, high-level "1" signals are sequentially supplied to the gates of N-channel FETs 2N1 to 2Nn to turn them on, and the row electrodes V1. y2+ φ...+
Vn, heavy RV is sequentially applied to each electrode as a scanning pulse Py.
w- is supplied. In addition, in the row coordinate detection mode, the timing generation circuit 2
04 to the AND circuits 2AI to 2An.
(shown as yenable in FIG. 13C) is provided. Then, the changeover switch 223 is connected to the C side and supplies power to the sources of the P channel FETs 2PI to 2Pn! /2VD is supplied (as shown in FIG. 13E), and the selector switch 224
is connected to the b side, and the sources of N-channel FETs 2N1 to 2Nn are grounded (shown in FIG. 13F), and the external
The inversion/non-inversion control signal (shown as inversion/non-inversion in the 13th diagram) supplied to the SIBNOOR circuits #J2El to #2En is set to a low level "O". Also, the timing occurrence #! Data for the scan pulse PV' (shown as y data in FIG. 13A) is supplied from I204 to the shift register 221, as well as a clock (shown as y clock in FIG. 13B). The data for this scanning pulse Py' is for row electrodes yl, y2 .
Since a plurality of adjacent electrodes, for example, 20 electrodes out of +3'n are simultaneously scanned, the high level "'l" continues for 20 clocks. Therefore, a low level "0" signal is simultaneously supplied to the adjacent 20 gates of the P-channel FETs 2Pl to 2Pn, turning them on, and the row electrode yl of the panel 2010 is turned on.
+ V2* ” ” ” ”* At the same time, f is applied to 20 adjacent electrodes of yn as scanning pulse Py′.
ill/2VD is supplied, and sequential scanning is performed in this state. In addition, in the column coordinate detection mode, the timing generation circuit 2
04 to the AND circuits 2A1 to 2An (the enable signal shown as y enable in FIG. 13C is set to low level "'O".
is connected to bm, and the sources of P-channel FETs 2PI to 2Pn are grounded (as shown in FIG. 13E), and the selector switch 224 is connected to the b side, and
The source of Nn is grounded (illustrated in Figure 13F) and inverted/
The non-inverted control signal is set to a low level 110I+. Therefore, a high level "1" signal is supplied to the gates of the N-channel FETs 2N1 to 2Nn to turn them on, and the row electrodes yl, V2°.--+Vn of the panel 201 are all grounded. Further, 231 is the column electrode xl, x2, . . . of the panel 201.
...l A shift register having a number of stages corresponding to the number of electrodes of X1m, 212 a latch circuit having a number of stages corresponding to the number of electrodes, 233 a NAND circuit 3A1 to 3Am corresponding to the number of electrodes, and N channel FETs 3N1 to 3N+w
234 is a variable power supply circuit, and the shift register 231, latch circuit 232, driver 233, and variable power supply circuit 234 constitute the column electrode driver 203. That is, the m-stage output terminal of the shift register 231 is
These are connected to the input sides of NAND circuits 3A1 to 3An+ of the driver 233 via latch circuits 232, respectively, and the output sides of these NAND circuits 3A1 to 3AFa are connected to the gates of N channel FETs 3N1 to 3Nm, respectively.
Connected to the gates of P-channel FETs 3P1 to 3Pm. Further, the sources of the P-channel FETs 3Pl to 3Ps+ are connected to the output side of the variable power supply circuit 234, and the power supply 1/2VD is connected to the input terminal of the variable power supply circuit 2340. This variable power supply circuit 234 is controlled by the timing generation circuit 204, outputs vO in the display mode, and outputs 1/2vD in the coordinate detection mode (shown in FIG. 13K). The 3Nm sources are each grounded. The drains of P-channel FETs 3Pl to 3PIg are respectively N-channel FETs 3N! ~3Ntm drain, and each connection point is connected to the column electrode x1. x2. ..., connected to xm. In addition,
A diode is connected to the drain and source of each of the N-channel FETs 3N1-3 N rg + P-channel FETs 3P1-3Pm. In this case, in the display mode, the timing generation circuit 204 sends an enable signal (J,
Q (shown as X enable) is provided. Also, the timing generation circuit 204 outputs the shift register 2.
Data in 31 (illustrated as X data in Figure 13 H and O)
is supplied to the shift register 31, and a clock (
Figure 13 1. (shown as an X clock) is supplied to P. In this case, the row electrodes yl, y2. ...+
In a certain frame in which the voltage RV w+ is supplied to yn as the scanning pulse py, inverted data of the display data SD is supplied, while the voltage Vw- is supplied as the scanning pulse Py.
In the next frame in which the display data SD is supplied, the display data SD is supplied as is. Then, each time data is sequentially supplied to the shift register 231 and m pieces of data for one scanning line are set, the timing generation circuit 204 sends a load signal to the latch circuit 232 (Fig. 13, shown as ) is supplied to the latch circuit 232, and the m pieces of data for one scanning line are supplied to the latch circuit 232.
The data is latched at , and held for the next one scanning line period in which m pieces of data are sequentially supplied to the shift register 231 . This provides a sufficient period for the EL to emit light, e.g. 40 μs.
approximately c is ensured. Therefore, row electrode yt, 5/2. ...,
In a certain frame where the voltage Rvw÷ is supplied to yn as the scanning pulse py, ! 3 N-channel FETs per scan line
A high level "1" signal is supplied to the gate of N1 to 3Ng+ that corresponds to the display pixel area and is turned on, and a low level signal is supplied to the gate of the P channel FET 3P1 to 3Pa+ that corresponds to the non-display pixel area. The "O" signal is supplied and turned on, and the panel 2010 column electrode x1.
x2. . . xll, the electrode corresponding to the display pixel portion is grounded, and the voltage VD is supplied to the electrode corresponding to the non-display pixel portion. On the other hand, in the next frame where the electric current tri V w is supplied as the scanning pulse PV, the P channel FE is
A low-level "0" signal is supplied to the gate of T3P1 to 3Pm corresponding to the display pixel portion to turn it on, and a high level signal is supplied to the gate of N-channel FET3N1 to 3Nm corresponding to the non-display pixel portion. The signal of VELPA 1" is supplied and turned on, and the column electrode x 1 of the panel 201
+ x 2 + ... I XTla, the voltage VD is supplied to the electrode corresponding to the display pixel section, and the electrode corresponding to the non-display pixel section is grounded. In addition, in the row coordinate detection mode, the timing generation circuit 2
The enable signal (shown as X enable in FIG. 13J) supplied from 04 to the NAND circuits 3A1 to 3Am is set to a low level "0P".
A high level "1" signal is supplied to the gates of 3N1 to 3Nm to turn them on, and all column electrodes of the panel 201 are grounded. In addition, in the column coordinate detection mode, the timing generation circuit 2
04 supplies an enable signal (shown as X enable in FIG. 13J) to the NAND circuits 3A1 to 3An+. Then, data for the scanning pulse Px' (shown as X data in FIG. 13H) is supplied from the timing generation circuit 204 to the shift register 231, and the clock (
Figure 13! (shown as an X clock) is supplied to the clock. The data for this scanning pulse Px' is for column electrodes x1. x
Since a plurality of adjacent electrodes, for example, 20 electrodes of 2°...t xll+ are simultaneously scanned, the high level "1" continues for 20 clocks. Note that the timing generation circuit 204 continues to supply the latch circuit N232 with a load signal (shown as X load in Figure 13), and the latch circuit 232 is placed in the through mode. Therefore, a low level "0" signal is simultaneously supplied to the adjacent gates of 20 of the P-channel FETs 3PI to 3Pm to turn them on, and the column electrodes xl of the panel 201,
x2. ..., a voltage 1/2 VD is simultaneously supplied as a scanning pulse Px' to 20 adjacent electrodes of the X electrode, and scanning is performed sequentially in this state. In this way, in the display mode, the row electrode yL y2+
. . +3'n is sequentially supplied with scanning pulses Py for each electrode, and the column electrodes xi, x2 . . . . A voltage corresponding to the display data SD is simultaneously supplied to xm for each scanning line, the display is driven by line sequential scanning, and an image corresponding to the display data SD is displayed. Further, the detection signal of the pen 205 is supplied to an amplifier 206, the detection signal VS from this amplifier 206 is supplied to a comparator 207 and a peak time detection circuit 209, and the respective output signals are supplied to an AND circuit 20B. The AND circuit 208 outputs a signal of high level "1" when the detection signal VS is higher than the reference voltage Vr and at the peak of the detection signal VS, and a signal of low level "0" at other times. is output. The output signal of this AND circuit on the 20th is supplied as a count stop signal to the row coordinate detection section 210 and column coordinate detection g211, which are constituted by a counter. The row coordinate detection unit 210 includes a shift register 22.
1, a clock (shown as an X clock in FIG. 13B) is supplied by the timing generation circuit 204, and a reset signal (shown as an X counter reset in FIG. 13G) is supplied. It is reset before entering row coordinate detection mode. Therefore, when the row coordinate detection mode is entered, the clock starts counting, and the counting operation ends when the detection signal VS is greater than the reference voltage V' and at the peak of the detection signal VS, and the row coordinate detection unit 210 detects the pen. A count value corresponding to an arbitrary position on the panel 201 where the touch panel 205 is touched is obtained as a row coordinate output.
(X in Figure 13 I)
A clock (shown as a clock) is supplied from the timing generation circuit 204, and a reset signal (shown as an X counter reset in FIG. 13M) is supplied to reset the X counter before entering the column coordinate detection mode. Therefore, when the column coordinate detection mode is entered, the clock starts counting, and ends when the detection signal vsblK is higher than the quasi-voltage Vr and the detection signal VS is at its peak, and the column coordinate detection unit 211 detects the pen 205. A count value corresponding to an arbitrary position of the panel 201 that is touched is obtained as a row-seat bare output. In addition, in FIG. 12, 204a is a RAM in which display data SD is written. According to this example, since the panel 201 is used for both display and coordinate detection, it is possible to ensure that the display surface of the display and the input surface of the tablet match over the entire surface with an accuracy of one display pixel. , can be easily manufactured. Furthermore, since the panel 201 is used in both the display mode and the coordinate detection mode, and the row IF pole driver 202 and column electrode driver 203 are commonly used, unnecessary circuits can be omitted and the configuration can be made at low cost. It can also be advantageous in terms of space. Furthermore, since the display mode period and the coordinate detection mode period are provided alternately in a time-sharing manner, the scanning pulse Py′ is not affected by interference signals caused by various signals necessary for display driving during the coordinate detection mode period. Px' can now be detected, and coordinates can be detected satisfactorily. Furthermore, in the coordinate detection mode, scanning is performed sequentially with scanning pulses Py'Px' being simultaneously supplied to a plurality of adjacent electrodes, for example, 20 electrodes, so the level of the detection signal of the pen 205 increases, and the scanning The pulses Py' and Px' can be easily detected, and coordinates can be detected satisfactorily. Also, when the pen (pencil-shaped conductor) 2o5 is brought close to the glass surface of the panel 201, the output signal of the comparator 207 becomes high level 111 II, and the AND circuit 208 causes the row coordinate detection unit 210 and the column coordinate detection unit 211 to stop counting. Since the signal is supplied and the coordinate detection operation is automatically started, the operation is less cumbersome compared to the conventional method, which turns on a mechanical switch built into the pen by pressing the pen tip against the display and starts the coordinate detection operation. Without searching,
Furthermore, the pen 205 can be constructed at low cost with a small number of parts, and since there are no moving parts, there is no need to worry about the pen 205 breaking down. Incidentally, in the above embodiment, a thin film EL matrix panel is used as the matrix panel, but next, an example using an AC type plasma display will be described. As shown in FIGS. 14 and 15, the thin film EL matrix panel and the AC type plasma display have almost the same AC voltage brightness characteristics and emission time change characteristics (V th is around 200 to 300 V). Therefore, a device using an AC type plasma display as a matrix panel can be realized as a configuration in which, for example, an AC type plasma display is arranged in place of the thin film EL matrix panel 201 in the example shown in FIG. 12. In this case, the light emitting time τ is about 100 μsec for a thin film EL matrix panel, whereas it is short, about 1 μsec for an AC plasma display.
When the frequencies of the C voltages are the same, it becomes an F4MJNEL matrix matrix panel. As a countermeasure against this problem, the frequency of the AC voltage may be increased. That is, instead of simply applying a constant voltage to selected points of the matrix electrode during the display mode as in the case of using the thin film EL matrix panel 201, a faster burst-like pulse may be applied. This can be realized by carving the x and y enable signals in the example in Fig. 12 with finer lock signals (see Fig. 13).
(Illustrated in Figures C', J'Q'). Although detailed explanation will be omitted, for example, the thin film EL matrix panel 1 in the example in FIG. 3 instead of the example in FIG. 12
It is also possible to realize a configuration in which an AC type plasma display is arranged instead of 01. Next, an example in which a TPT liquid crystal matrix panel is used as the matrix panel will be described with reference to FIG. In FIG. 16, parts corresponding to those in FIG. 12 are designated by the same reference numerals, and detailed explanation thereof will be omitted. In the figure, 201' is a TPT liquid crystal matrix panel. This TFTf night crystal matrix panel 201
' is different from thin-film EL matrix panels and plasma displays in that liquid crystal pixels are not directly connected to matrix electrodes, but row electrodes ylxyn and column electrodes x1.
A TPT corresponding to a pixel is selected at ~X1ll, and display is performed by applying a voltage that is inverted every frame only to a predetermined pixel. That is, row electrode y1. y2. ..., yn is...
TFTII~TFTI..., TPT21~TPT, respectively
2+w, a banksha+ connected to the sources of TFTnl to TFTnm, and connected to the column electrodes x1. x2.・
... xm is TFTII ~ TFTnl, T
PT+2~TFTn2. − − *, TFTl
Connected to the gates of m to TFTnm. Also, T F
The drains of T 11 to T F Trv are respectively connected to each pixel electrode of the liquid crystal. In addition, N-channel FET2N1 to 2Nn, P-channel FET
A diode between the drain and source of each of ET2PI to 2Pn becomes unnecessary. Further, the fixed terminal on the C side of the changeover switch 223 is connected to the power source 7 + (for example, +15V). Also, t RV
v+ and Vc are, for example, +5V and -5V, respectively.
It is considered to be V. In this case, in the display mode, the timing generation circuit 204
The enable signal (first
7C9P) is supplied. In a certain frame, the changeover switch 223 is connected to the a side and the power supply Vw+ is supplied to the sources of the P channel FETs 2P1 to 2Pn (as shown in FIG. 17E), and the changeover switch 224 is connected to the b side and the N channel FET2N
The sources of 1-2Nn are grounded (as shown in Figure 17F);
The inverting/non-inverting control signal (shown as y inverting/non-inverting in Figure 17) supplied to the exclusive NOR circuits 2EI to 2En is set to a low level j7□'', while in the next frame, the changeover switch 223 is connected to the b side, and the sources of P channel FETs 2Pl to 2Pn are grounded (
(Illustrated in FIG. 17E), the changeover switch 224 is connected to the a side, and the sources of the N-channel FETs 2N1 to 2Nn are
A power supply Vw- is connected (as shown in FIG. 17F), and the inversion/non-inversion control signal is set to a high level "11". Also, the timing generation circuit 204 outputs the shift register 2.
21 is supplied with data for the scanning pulse y (shown as y data in FIG. 17A), and a clock (the 17th
(shown as y clock in Figures B and M). As data for this scanning pulse y, row electrode 5/I
, V2. ...+S'n is sequentially scanned one by one, so that the high level "l" continues for one clock. Therefore, in a certain frame, P channel FET2P
A high level "O" signal is sequentially supplied to the gates of ports 1 and 2P, turning them on, and the row electrode yl+ of the panel 201'
yL...1 as scanning pulse PV to ts'n
In the 0th frame in which heavy FGV signals are sequentially supplied at the electrode level, a high level "I11" signal is sequentially supplied to the gates of N-channel FETs 2N1 to 2Nn and turned on.
Row electrode yI+5'2 of panel 201'. ...+3'
n, the power supply Vb is sequentially applied at one electrode amount as a scanning pulse py.
t- is supplied. In addition, in the row coordinate detection mode, the timing generation circuit 2
04 supplies the AND circuits 2A1 to 2An with an enable signal (shown as y enable in FIG. 17C). The changeover switch 223 is connected to the C side, and the power supply ■0+ is supplied to the sources of the P channel FETs 2PI to 2Pn (as shown in FIG. 17E), and the changeover switch 224 is connected to the B side.
The sources of the N-channel FETs 2N1 to 2Nn are connected to the ground (as shown in FIG. 17F), and the inverted/non-inverted control signals (shown in FIG. ) is set to low level "011". Also, the timing generation circuit 204 outputs the shift register 2
21 is supplied with data for the scanning pulse Py' (shown as y data in FIG. 17A), and also supplied with a clock (shown as y clock in FIG. 17B).This scanning pulse PV' The data for row electrode yL 5'2
+..., multiple adjacent lines of yn, e.g. 2
Since zero electrodes are scanned at the same time, the high level "1" continues for 20 clocks. Therefore, a low level "0" signal is simultaneously supplied to the adjacent 20 gates of the P-channel FETs 2PI to 2Pn, turning them on, and the row electrodes y of the panel 201' are turned on.
The power supply ■0+ is simultaneously supplied as a scanning pulse Py' to 20 adjacent electrodes of l+ y2+ """' and yn, and scanning is performed sequentially in this state. In addition, in the column coordinate detection mode, timing generation circuit 2
The enable signal (shown as y enable in FIG. 17C) supplied from 04 to the AND circuits 2A1 to 2An is set to a low level "O", and the changeover switch 223 is connected to the b side and the P channel FETs 2Pl to The source of 2Pn is grounded (as shown in Figure 17E), and the selector switch 2
24 is connected to the b side and is an N channel FET 2N1~2N
The source of n is grounded (as shown in FIG. 17F), and the inverting/non-inverting control signal is set to a low level "0". therefore,
A high level "ll' signal is supplied to the gates of the N-channel FETs 2N1 to 2Nn, which turn them on, and the panel 201
The row electrodes yll y2゜◆..., yn of ' are all grounded. In addition, the P-channel FET 3P constituting the driver 233
The sources of 1 to 3Pw are connected to the power supply ■0+,
The source of N-channel FET3N1~3N is the voltage [VD-
(for example, -15■). In addition, N channel F
ET3N1~3N warm, P channel FET3P1~3Pm
No diode is required between the drain and source of each. In this case, in the display mode, the timing generation circuit 204
An enable signal (shown as X enable in FIGS. 17J and 17P) is supplied to the NAND circuits 3A1 to 3Ai+. In addition, the timing generation circuit 204 supplies the display data SD (shown as X data to the 171st! IH, N) to the shift register 231, and the shift register 231
31 is supplied with a clock (shown as X clock in FIG. 17, 1.0). Then, each time the display data SD is sequentially supplied to the shift register 231 and m pieces of data for l scanning lines are set, the timing generation circuit 204 sends the display data SD to the latch circuit 231.
A load signal (the 171st!! IK. shown as an X load on M) is supplied to
data is latched by the latch circuit 232, and
The data of m1li is sequentially supplied to the shift register 231 and is held for the next l scanning line period. Therefore, in each frame in which the row electrodes yt, yL...+Vn are supplied with the voltage aVQ+ or the voltage Vw- as the scanning pulse PV, one of the P-channel FETs 3P1 to 3Pm corresponding to the display pixel portion is selected for every l scanning line. A low-level “0” signal is supplied to the gate of the N-channel FET 3N1 to 3N to turn it on.
A high level "l" signal is supplied to the gate of the pixel portion corresponding to the non-display pixel portion of m, and the panel 201 is turned on.
' column electrodes X1, x2. ..., X1ll
Voltage vO+ is supplied to the electrode corresponding to the display pixel part, and voltage ■ is supplied to the electrode corresponding to the non-display pixel part.
is supplied. In addition, in the row coordinate detection mode, the timing generation circuit 2
04 to the NAND circuits 3A1 to 3Al (shown as X enable in FIG.
A high level "1°" signal is supplied to the gates of T3N1 to 3Nm to turn them on, and voltage VD- is supplied to all column electrodes xl, x2, . . . , xlI of panel 201'. , in the column coordinate detection mode, the timing generation circuit 2
From 04, an enable signal (
(shown as X enable in FIG. 17J) is provided. Then, data for the scanning pulse Px' (H!1 in FIG. 17) is sent from the timing generation circuit 204 to the shift register 231.
:X data (shown as X data) is supplied, as well as a clock (shown as X clock in FIG. 17I). The data for this scanning pulse Px' is the column electrode xL x
2゜..., multiple adjacent pieces of Xll, e.g. 2
Since zero electrodes are scanned at the same time, the high level "1" continues for 2.0 clocks. Note that the timing generation circuit 204 continues to supply the latch circuit 232 with a load signal (shown as X load in FIG. 17K).
This latch circuit 232 is set in through mode. Therefore, a low level "0" signal is simultaneously supplied to the gates of 20 adjacent P-channel FETs 3P1 to 3Pm, turning them on, and the column electrode X1 of the panel 201'
．． ! 2. = In contrast, a voltage VD÷ is simultaneously supplied to 20 adjacent electrodes of xm as a scanning pulse PX',
In this state, sequential scanning is performed. In this way, in the display mode, the scanning pulse Py is sequentially supplied to the row electrodes yl, y2°, . . . . A voltage corresponding to the display data SD is simultaneously supplied to XS for each scanning line, TFTII to TFTnm are driven for display in line sequential scanning, and an image corresponding to the display data SD is displayed. Further, the detection signal of the pen 205 is supplied to an amplifier 206, the detection signal VS from this amplifier 206 is supplied to a comparator 207 and a peak time detection circuit 209, and the respective output signals are supplied to an AND circuit 20. The AND circuit 20B outputs a signal in which the detection signal VS is greater than the reference voltage V and is at a high level "1°" at the peak of the detection signal VS, and at other times it is at a low level nOII. The output signal of the AND circuit 208 is supplied as a count stop signal to the row coordinate detection section 210 and the column coordinate detection section 211, which are composed of counters. shift register 22
1 (shown as the X clock in FIG. 17B) is supplied from the timing generation circuit 204, and a reset signal (shown as the X counter reset in FIG. 17G) is supplied. Reset before entering coordinate detection mode. Therefore, when the row coordinate detection mode is entered, the clock starts counting, and the counting operation ends when the detection signal VS is greater than the reference voltage V' and at the peak of the detection signal VS, and the row coordinate detection unit 210 detects the pen. A count value corresponding to an arbitrary position on the panel 201' where the panel 205 is touched is obtained as a row coordinate output.
(X in Figure 17 I)
A clock (shown as a clock) is supplied from the timing generation circuit 204, and a reset signal (shown as an X counter reset in Figure 17) is supplied to reset the X counter before entering the column coordinate detection mode. Therefore, when the column coordinate detection mode is entered, the clock starts counting, and the counting operation ends when the detection signal VS is larger than the reference voltage VS and at the peak of the detection signal VS. A count value corresponding to an arbitrary position on the panel 201' where the panel 205 is touched is obtained as a column coordinate output.The above example corresponds to the example in FIG.
A structure in which a TFTM crystal matrix panel 201' is arranged instead of the thin film EL matrix panel 101 in the illustrated example can also be realized in the same manner. In addition, in the above, the matrix panel includes a thin film EL matrix panel, an AC type plasma display, and a TP
Although an example using a T-liquid crystal matrix panel has been described, the present invention is not limited thereto, and can be applied to, for example, a simple matrix type liquid crystal display element, a DC type plasma display, etc. using other types of matrix panels. Of course, it can also be applied in the same way. [Effects of the Invention] As explained above, according to the present invention, since the panel is used for both display and coordinate detection, the display surface of the display and the human input surface of the tablet can be covered over the entire surface with an accuracy of one display pixel. Since they match reliably over the entire area, it is possible to omit a half-opening for matching, and it is possible to manufacture easily. In addition, since the panel is used for both display mode and coordinate detection mode, and the row electrode driver and column electrode driver are used in common, there is no need to provide unnecessary circuitry, and the configuration can be made at low cost. It can also be advantageous. In addition, since the display mode period and the coordinate detection mode period are provided alternately in a time-sharing manner, the coordinate detection mode can be opened and opened using scanning pulses without being affected by interference signals caused by various signals necessary for display drive. can now be detected, and coordinate detection can be performed satisfactorily.

[Brief explanation of drawings]

11th! 1 is a configuration diagram showing an embodiment of the present invention, FIG. 2 is a diagram for explaining its operation, FIG. 3 is a concrete configuration diagram of the example in FIG. 1, and FIG. 4 is a diagram for explaining its operation. FIG. 5 is a block diagram showing another embodiment of the invention, FIG. 6 is a block diagram showing still another embodiment of the invention, FIGS. 7 to 11 are diagrams for explaining its operation, and FIG. 12 is a specific configuration diagram of the example shown in FIG. 6, FIG. 13 is a diagram for explaining its operation, FIGS. 14 and 15 are diagrams for explaining an AC type plasma display, and FIG. 16 is a diagram for explaining the example of this invention. A specific configuration diagram of another embodiment, FIG. 17 is a diagram for explaining its operation, and FIG. 18 is a configuration diagram of a conventional example. 107.2 10B, 2 207 ・ ・ ・ Row coordinate detection unit・Column coordinate detection unit - Converter ・Peak point detection circuit 101, 201 ・Thin film EL matrix panel 201′ ・Vintage・TPT liquid crystal matrix panel 102.202 ・・・Row electrode driver 103.203 ・Column electrode driver 104.204 ・-Conflict timing generation circuit IQ5,205 ・Conflict φ pencil conductor patent applicant Sharp Co., Ltd. agent Patent attorney Yamaguchi Japanese embodiment Figure 1 shows the drive timing of the panel. Figure 2 shows the drive timing of the panel.

Claims (2)

[Claims] (1) Comprising a matrix panel having row electrodes and column electrodes, a row electrode driver, a column electrode driver, a row coordinate detection section, a column coordinate detection section, and a detection conductor, and in the display mode, the above-mentioned The row electrode driver sequentially supplies scanning pulses to the row electrodes of the panel one electrode at a time, and each time a scanning pulse is sequentially supplied to the row electrodes of the panel, the column electrode driver supplies display data to the column electrodes of the panel. In the row coordinate detection mode, scanning pulses are sequentially supplied from the row electrode driver to the row electrodes of the panel, and by bringing the detection conductor into contact with any position on the panel, electrostatic The scanning pulse detected by capacitive coupling is supplied to the row coordinate detection unit to detect the row coordinate of the detection conductor contact position, and in the column coordinate detection mode, the scanning pulse is sequentially applied to the column electrode of the panel from the column electrode driver. A scanning pulse is supplied and detected by capacitance coupling by bringing the detection conductor into contact with an arbitrary position on the panel.The scanning pulse is supplied to the column coordinate detection section to detect the column of the detection conductor contact position. A display-integrated tablet characterized by coordinate detection. (2) The display-integrated tablet according to claim 1, wherein the period of the display mode and the period of the coordinate detection mode are provided alternately in a time-sharing manner.