JPH02253377A - Picture editing device - Google Patents

Abstract

PURPOSE:To simply set an area and furthermore the area of a complicated form by using a marker to designate a working area of an original. CONSTITUTION:A data processing control part 6 detects a mark written into an original in a prescribed density range or an area enclosed by the mark and then applying the trimming and the masking to the original based on the mark or the area enclosed by the mark. A memory control part 7 contains plural sheets of memories and synthesizes these memories. Then the part 7 designates different areas among different originals and stores the processes picture information in the frame memories according to the designation of areas. These stored picture information are read out and outputted after synthesization. Thus the pictures can be synthesized among different originals where the areas are designated by marks respectively.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an image editing device, which is capable of specifying an arbitrary area on a document, extracting the arbitrary area, processing such as erasing, black and white inversion, and memory composition. The present invention relates to an image editing device.

[Conventional technology]

With digital copy machines, manual scanners, facsimile machines, etc., if there is a part of the information on the document that does not need to be copied, the relevant part of the document must be cut out before making a copy, or the relevant part of the document must be copied. The necessary parts were copied by covering them with white paper and making copies.

However, with this conventional method, the original must be processed, which may damage the original, and in addition to being time-consuming, it is necessary to obtain multiple copies with unnecessary parts removed. In some cases, for example, the white paper covering unnecessary parts may shift, making it impossible to obtain identical copies.

In order to solve this problem, a color felt-tip pen or the like is used to surround an arbitrary area on the document with a mark, and the area for processing and memory composition is specified by reading the mark specified area.

[Problem to be solved by the invention]

However, in the above-mentioned conventional technology, when specifying an area of a document using a mark area, image synthesis is performed on one document, and a method for setting each area using a compositing device between documents that have been edited in multiple areas is not recommended. Although it is possible to manually specify X and Y coordinates, it is difficult to specify complex areas by inputting XY coordinates.

The present invention has been made in view of the above-mentioned problems of the prior art and has been made to solve this problem.The purpose of the present invention is to specify areas of a document for area processing (for example, area extraction, erasure, black and white inversion, etc.) with marks, and to An object of the present invention is to provide an image editing device capable of performing image synthesis between documents to which area processing is desired.

[Means to solve the problem]

In order to achieve the above object, the present invention includes a reading means for reading an original image and generating image information, a specifying means for specifying a desired area of the original by a mark, and a method for specifying the desired area according to the area specification by the specifying means. a processing means for processing image information generated by the reading means in accordance with the area signal generated from the generation means; and a plurality of storage means capable of storing a plurality of pieces of image information. and a control means for controlling writing and reading of the plurality of storage means, and a means for synthesizing image information read from the plurality of storage means, reads a plurality of original images, and writes each of the plurality of originals to the plurality of originals. A desired area is specified by the specifying means, the image information generated by the area signal obtained by the area generating means is processed by the processing means, the processed image information is stored in the plurality of storage means, The image processing apparatus has a structure in which the processed image information is read out from the storage means and is synthesized and outputted by the synthesizing means.

[Effect]

The means specifies different areas between different originals, stores image information processed in accordance with the area designations in a plurality of storage means, reads out the stored image information, and synthesizes and outputs the image information by the synthesizing means.

This makes it possible to perform image synthesis between different documents whose areas are designated by marks.

〔Example〕

Embodiments of the present invention will be described below based on the drawings.

FIG. 1 shows a block diagram of the configuration of an image processing apparatus that is an embodiment of the present invention. 4 is a scanner section, and this scanner section 4
As shown in FIG. 2, an image of the reading line l of the original 1 is focused on the CCD line sensor 3 via the coupling lens 2, and the relative position between the original 1 and the CCD line sensor 3 in the Y direction is While updating the read line by mechanically shifting the position (sub-scanning), scan each line 40 times from left to right in the X direction.
Read at a density of 0 dpi (#16 pixels/tm) (main scan). The read signal becomes an analog signal having an amplitude corresponding to the density of each pixel. 5 is a video processing circuit;
A circuit that A/D converts the read signal a and performs background removal processing, shading correction processing, MTF correction processing, etc. on it to generate 6-bit (64 gradations) image data 6 (the higher the value, the higher the density). It is. 6 is a data processing control unit, and this data processing control unit 6 reads the data and sets black pixels to “1”=H level and white pixels to “0”.
: Binarize as L level, and extract specified area (
trimming), erasing (masking), etc., to generate write data d. Also, write data d
As will be described later, is a mark area signal. Reference numeral 7 denotes a memory control unit, which stores the write data d in a memory, and the memory in the memory control unit 7 has a plurality of frame memories, and also performs compositing between the memories. and the signal e
This outputs the following. 8 is a laser printer that performs AO modulation (1: recording, 0: non-recording) of a laser beam and prints out on recording paper.

In the above-mentioned image processing device, the control device that controls each of these components, the scanner section 4, the video processing circuit 5, and the laser printer 8 are well-known technologies and do not directly relate to the features of the present invention, so a detailed explanation will be given. Omitted.

The data processing control unit 6 detects a mark in a predetermined density range written on the original 1 or an area surrounded by the mark, and performs trimming and masking on the original based on this.

In this embodiment, a mark using a color felt pen (hereinafter referred to as a color mark) is used as a mark for a predetermined density range.
Assume that This is because color felt-tip pens are already available in various densities, which makes marking in a predetermined density range easier and is advantageous in practice.

FIG. 11 is a block diagram showing the configuration of the density determination circuit and the one-pixel noise removal circuit. 34° and 35 are comparators, and these two comparators 34.3
5 constitutes a density determination circuit and detects halftone read data A. That is, by comparing read data A and two threshold levels St+ and B, 2 (By+>Byz), B7. >A signals f1 and B,! <A signal ft
get. Here, the threshold level BT+ is set to the same level as the threshold level for simple binarization. As a result, in simple binarization, a so-called faint mark is detected in a range that is not determined to be black. Further, the threshold level BT2 is set to an appropriate level for stains on the background of the document, density unevenness, and the like. 36 is a flip-flop, 37.degree. 38 is an OR gate, 39.40 is an AND gate, and constitutes an l pixel noise removal circuit.

FIG. 12 is a time chart for explaining 1-pixel noise removal.

As an example, assume a signal f as shown in FIG.

Note that the numbers in the time chart indicate the main scanning addresses of the read pixels. The signal f here is the main scanning address 5
The place where noise is added and f, = ``1'' becomes f, = ''
The color mark is detected between main scanning addresses 1 to 4 and 6 to 8, and f = "1". The clock CK has one period corresponding to one main scanning pixel. f3 is a signal that is latched for one period of signal f and fc using flip-flop 36, and by passing signal f2 and signal f3 through OR gate 37, signal f4 from which noise has been removed is obtained. .

Since the signal f4 is longer than the signal f1 before noise removal by one period, the signal f4 is latched for one period using the flip-flop 36 to obtain the signal f, and the signal f4 and the signal f , through the AND gate 39, noise is removed and a signal f having the same length as the signal f1 is obtained.
, get . Signal f! Regarding flip-flop 36,
A similar operation is performed using an OR gate 38 and an AND gate 40 to obtain a signal f.

get. Finally, by passing the signal f and the signal f through the AND gate 41, a signal f indicating the mark density range is generated.
You can get 7.

In this example, the removal of one pixel noise has been described, but by changing the system, it is possible to remove noise of 2 pixels, 3 pixels, . . . , 9 pixels. Also, threshold levels BTI and B7□
can be varied.

FIG. 13 is a block diagram of the mark area detection circuit. For example, even if a halftone is detected in a minute area of one to several pixels due to dirt on the background, etc., it is not detected as a mark area. That is, over a certain area, only in the case of an intermediate tone, a certain area including that area is set as a mark area.

The basic unit of this mark area is 12 in this example.
The unit is X12 pixels, but this can be changed by changing the system. A signal f8 indicating the mark density range is input to the first sub-scanning mark detection section 42 and the second sub-scanning mark detection section 43.

FIG. 14(a) shows the function of the first sub-scanning mark detection section 42. In this first sub-scanning mark detection section 42, 12
The basic unit of area of ×12 pixels is scanned in the sub-scanning direction, and when the signal f = “1” in all 12 pixel blocks, that block is considered “OK” (=1), and even if only one pixel has the signal f, = “0”, the block is “NG” (=0
). And when 12 block scanning is completed,
When all the blocks are "OK", the first main scanning mark detection unit 44 identifies this basic unit of 12 x 12 pixels as a mark area, outputs the signal f="1", and outputs the signal GATE= Let it be “l”.

FIG. 14) shows the function of the second sub-scanning mark detection section 43. In this second sub-scanning mark detection section 43, 12
Within a block of pixels, a certain probability (2/3 in this example)
In the above, when the signal r,'="1", the block is "
OK” (=1), and when the signal f=“1” is less than that probability, the block is determined to be “NG” (=0).

Then, when the scanning of 12 blocks is completed, the second main scanning mark detection unit 43 detects 12 X if the block is "OK" with a certain probability (2/3 in this embodiment) or more.
A basic unit of 12 pixels is identified as a mark area, and a signal. ="l" is output. When the mark area has already been detected by the first sub-scanning mark detection unit 42 and the first main-scanning detection unit 44, the signal GATE="1" is passed through the AND gate 47 and the signal "fll"
“1” is output. The signal f and the signal f pass through an OR gate 46 and are finally converted to a signal r indicating whether the area is marked or not.
+z is output.

Then, even if the area identified as the mark area is interrupted in the middle and divided by white, or if a minute area within the mark is white or black, the mark is continued without regard to this. In order to detect the mark area as if it were there, the main scanning mark width extension section 48 extends the main scanning direction, and the sub scanning mark extension section 49 extends the marking area in the sub scanning direction, and outputs a signal f13 indicating the mark area.

In this embodiment, the expansion is performed by 8 pixels in the main scanning direction and 6 pixels in the sub-scanning direction as shown in FIG. 15, but this can also be changed by changing the system.

Furthermore, when marking the black print with a color felt-tip pen, the black print part is still black and has a high density. In this way, if the halftone area is divided by black, the halftone area is expanded to include the black part for detection. This is called Kurotogire.

Fig. 16 is a block diagram of the black blur prevention circuit, and Fig. 17 shows a state in which a black line enters a mark and the mark is interrupted, with the horizontal axis in the main scanning direction, and the corresponding signals. This is a diagram showing the following.

Signal f1 with marks extended in the main scanning direction and sub-scanning direction
3 through the inverter gate 50 and inverted as the signal f
Let it be ls. The signal f14 is a signal indicating a black area, and the signal f,4=“1” in the black area.

Signal f16 is obtained by passing signal rts and signal rts through NAND gate 51. The signal fl'& is latched by the shift register 52 and the signal f1. ? get. In this example, 16 pixels (approximately 1 crane) are latched, and including the previously expanded 8 pixels in the main scanning direction and 6 pixels in the sub-scanning direction, 24 pixels in the main scanning direction (approximately 1.5 m), and 22 pixels in the open scanning direction. Pixel (
(approximately 1.4 m) to compensate for equinox toggle.

This can be changed by changing the system.

Signal fl? By passing the signal fls and the signal fls through the NAND gate 53, a signal fil free of black toggles is obtained.

Then, by passing the signal f+++ through the inverter gate 54, a signal f,9 indicating a mark compensated for black toggle is obtained. Similar operations are performed in the sub-scanning direction as well.

Next, detection of an area surrounded by marks will be explained.

FIG. 18 shows a block diagram of the mark area detection section, and FIG. 19 shows an example of marks used for explanation.

FIGS. 20 and 21 are time charts corresponding to the signals shown in FIG. 18, and ``■'' to ``■'' in the figures represent mark signals or mark area signals at points ``■'' to ``■'' in FIG. 19.

When detecting the mark area at the point ■, in FIG. 20, the signal f19 indicating the mark at the point ■ and the signal f2° indicating the mark area at the point ■ stored in the memory 55 in FIG. 18 are used. The signal f0 is obtained by passing through the OR gate 57 in FIG. Then, at the first rising edge of the signal f+9, the set signal generating section 56 in FIG. 18 generates the set signal fzi, and at the falling edge of the signal f2°, the reset signal generating section 58 in FIG. 18 generates the reset signal f23. . Signal f! l signal f2. .

The signal f0 is passed through a three-man-powered AND gate 59 in FIG. 18 to obtain a signal f24. And signal rza and signal fyo,
are passed through the OR gate 60 in FIG. 18 to obtain a signal rzs indicating the mark area.

When detecting the mark area at point (3), the same operation is performed to obtain the mark area signal ft4.As shown in Fig. 21, the actual mark area signal is equal to f19 in this case, so there will be an error. , this is not a problem because the points ■ and ■ are actually very close at about 0.0611. This error occurs because the reset signal f23 is set at the falling edge of the mark area signal f2° of the previous line. This problem will not occur if you set the reset signal at the falling edge of the mark signal f19 at the point where you want to detect the mark area signal, for example point ■, but if there are multiple marks, it is difficult to determine the last falling edge. Therefore, we are using this method.

Here, the relationship between the image data and the mark area detection signal will be explained.

The image output from the video processing circuit 5 is (image data b
) enters the mark area detection unit 9 of the data processing control unit 6, and generates the mark area signal rzs by the mark area detection processing described above. Since the mark area signal f's is delayed in the main scanning and sub-scanning directions, the image data delay circuit 10 adjusts the delay state between the mark signal f's and the mark signal f's so as to match the delay with the image data b. It is consistent. The delay circuit 10 latches in the main scanning direction.
It is delayed by memory in the sub-scanning direction. CPU1
2 is an input from the operation board, and outputs data such as a binarization threshold level, mark area trimming, masking, black and white inversion, etc. to the image data binarization and editing circuit 11.

FIG. 22 shows a detailed block diagram of the binarization and editing circuit 11 of FIG. Further, FIG. 24 shows the relationship between the edited data from the CPU 12 and the output data d corresponding to M1-M3.

First, a method of binarizing input data g will be explained.

In the case of character output, the comparator 61 compares the binary level H from the CPU 12 with the input data g, and outputs the binary signal I. Further, by using the dither method, the dither ROM 25 and the input data are compared in a comparator 62 as pseudo halftone output, and dither data (halftone data) J
output, and if the operation board is in character mode, C
The data K from the PU 12 becomes 0, and the selector 63 outputs ■ as an L output.

In the case of the halftone (photograph) mode, the data from the CPU 12 is L, and the selector 63 outputs J to L.

At this time, data M of the CPU 12 corresponding to the selector 72
1 to M3 become 0 and correspond to input A of the selector 72. A signal will be output.

In addition, in marker editing mode, the marker supports halftone density, so the input document is basically a character document with a clear white/black ratio, that is, the background is whiter than the lower limit level of the marker, and the characters are It is assumed that the data is blacker than the marker upper limit level. Therefore, if document information that falls within the density level range of the marker falls within a range that is greater than or equal to the marker detection block, erroneous detection may occur. This occurs when there is a color document, a document with a photographic area, or light text information, and is also a drawback in marker detection.

Returning to the explanation of marker editing, as explained above, since a character manuscript is targeted, K is 0 during marker editing. A marker detection area (if it is determined to be a marker area, it becomes an H:1 signal) signal comes in from f's, and the following processes can be performed.

(1) Masking: In other words, when erasing information in the mark area, the AND gate 67 uses the mark area signal r
The signal obtained by inverting ts by the inverter 66 and the binary image signal are ANDed, the information in the mark area is erased, the information is input to the B input of the selector 72, and the commands M1 to M3 of the CPU 12 M1; 1, M2. By setting M3i0, a masking detector is output to the d output.

(2) Trimming: In other words, when extracting only the information within the mark area, the AND gate 68 performs the AND of the mark area signal ft% and the binary image signal, and extracts only the information within the mark area. input to the C input of the selector 72, and use commands M1 to M3 of the CPU 12 to set M2: l, M.
By setting l, M3:O, masking data is output to the d output.

(3) Black and white reversal inside the marker Image data outside the marker 2 In other words, only the information inside the marker in the image data is inverted in black and white, and the image data outside the marker is output as is.
Input marker signal f of select signal of selector 64
Image data and inverted data are selected by □, and when a mark area signal is generated, inverted data is selected and output. Also, the commands M1 to M3 of the CPU 12 are Ml, M2:1. M3:0.

(4) Outside marker black and white inverted image data inside marker: This is
(3) The signal obtained from the black-and-white inversion inside the marker image data outside the marker is inverted by the inverter 69, and the CP
Commands M1 to M3 of U12 are MISM2:0. M3:
It is 1.

(5) Black and white inversion within trimming marker: This is done in the same way as the trimming process in (2) for the image of only the marked area.
The D gate 71 outputs the mark signal and the inverted signal of the image data, and the CPU 1
2 command Ml-M3 is Ml, M3:1. M2:0
It is.

(6) Masking marker outside black and white inversion: This is an AND operation similar to the masking process in (1) for the image outside the marked area.
The gate 70 outputs the mark signal by the inverter 66 and the inverted signal of the image data.
Commands M1 to M3 of the CPU 12 are Ml:0. M2. M
The ratio is 3:1.

(The η mark area signal is transferred to cpuxt commands M1 and M
2. The output is set to d by M3:1.

Next, the memory control section 7 will be explained.

As mentioned above, in the data processing control section 6,
It is possible to edit the mark area, such as extraction, deletion, and inversion of white/black within the mark area.

In addition, the signals output from the data processing control unit to the memory control unit are (11) normal binarized images (including dithered images) (
2) Output of mark area signal (3) There are three outputs of the mark-edited image, each of which is selected and output to the memory control unit 7, or three outputs are output to the memory control unit 7 in parallel. It's okay. However, in this example, the above output is selected for each different document (mode),
It is output to the memory control section.

The memory that stores images is divided into multiple blocks, and each block is independently controlled.

Examples of this memory are shown in FIGS. 4 to 8 and 23.
In this embodiment shown in the figure, it is assumed that there are two memory blocks. First, in the image storage memories 13 and 16,
Memory for the reading area of the scanner unit 4 is secured 0 For example, if the reading density is 400 dpi in the A3 reading area
In the case of (297■+25.4 x 400)
420tm÷25.4X400): 4M BYTE
of memory is required.

This memory configuration is shown in FIG.

The 4PIBYTE memory mentioned above is IMD-RAM22
32 are arranged in parallel. That is, image data (IN DATA) is converted by 32-bit serial/parallel converters 20 and 21, and the data is input into each of 32 memories (RAM 22). Therefore, signals 1/32WCLK and 1/32RCLK are created by dividing the read/write clock WCLK and RCLK by 32. These 1/32W CL K and 1/32 RCL K are synchronized with WLGATE and RLGATE. Therefore,
As mentioned above, all areas of A3 can be read.

23 and 24 are parallel/serial converters. Also,
The memory address is controlled by address counters 14 and 17, as shown in FIG.
41 and 17 are the aforementioned 1/32 CL K (1/32 W CL K for writing, 1/32 for reading
RCLK) and LGATE (WLG for write)
ATE (in case of read, RLGATE) is counted up by a clock signal generated by passing the AND gates 15 and 18. In addition, as a clear signal for the counter, FGATE (in case of blank, W
It is controlled by FGATE (for read, RFGATE). As mentioned above, it is necessary to switch the clock, LGATE, etc. when reading/writing the memory.

FIG. 6 shows signals switched by memory read/write. The selection signal is a read/write controlled by the CPU 12, which determines whether data is written to or read from memory. This lead/
The signal that is switched by the light is 1/32W CL K (
A clock (WC
LK) signal divided by 32) and 1/32RCL K
(a signal obtained by dividing the frequency of the clock (RCL K) that outputs image data to the laser printer 8 by 32) to 1/3
2 CL K, and similarly, the main scanning direction synchronization signal, write signal WLSYNC, read signal RLS
Write signal WLGA with YNC and main scanning effective area signal
Write signal WFGATE read signal RF GAT
E is switched between read and write.

In addition, in FIG. 8, in order to count the sub-scanning effective area, WLSYNC is divided by n by a frequency divider 29, and is input to the CPU 31 through the I10 controller 30.
31 and detects the length of the sub-scanning, and when reading, RLSYNC is divided by n by a frequency divider 33 in the same way as dividing when writing.
Enter the WLSY of WFGATE mentioned above into P U31.
Output the NC portion FGATE and use it as RFGATE. Furthermore, since a D-RAM is used, a refresh circuit is required, but the refresh circuit uses a known technology and will not be described here. Note that 5-RAM may be used instead of D-RAM. Note that 19 is an output control section.

FIG. 23 shows a timing chart corresponding to each signal in the main scanning and sub-scanning directions for the original.

Since the maximum document size is A3, the A3 width in the main scanning direction becomes valid data, and becomes LC;ATE. Also, FGATE may be the maximum width of the original, or if the original is smaller than the maximum width, FGATE may be determined by only the original width or in relation to the transfer width.
The FGATE width may also be determined. Also, F shown in FIG.
GATE, LSYNC, LGATE when writing memory,
WFGATE.

WLSYNC, WLGATE and when reading memory,
RFGATE, RLSYNC, LGATE.

FIG. 7 is a block diagram of the synthesis output section. In FIG. 7, 26 is an OR gate, 27 is an exclusive OR gate, and 28 is a selector.

If the output from the first memory is DOOTl and the output from the second memory is DOOT2, then DOOTl and DOOT
2 are combined by an OR gate 26 and selectively output by a selector 28. Further, DoOTl and DOOT2 can be combined and outputted by the exclusive OR gate 52. In other words, DOOTl and DOOT2 output a mode in which black data overlaps even in areas where they overlap (
(using OR gate 26) and a mode in which the overlapping part is made white data (using exclusive OR gate 27)
You can choose. Further, the selector 28 selects which of the above modes to select using selection signals Nl and N2 output from the cPU. Further, since image information is not copied and output after being stored in the first memory, unnecessary copies can be reduced.

The operation of the embodiment configured as described above will be explained based on the flowchart of FIG.

In FIG. 9, first, a marker mode is specified from an operation section (not shown) for specifying a marker mode, and 1. Marker editing (trimming, masking, black and white inversion, etc.) and 2. Marker composition are selected (9-1).

First, a desired area of the document is specified using a marker (9-2), and a W collection mode, for example, a trimming mode is selected. The document on which the markers have been written is read by the reading means (9-3), the marker editing (data processing control section) described above is performed (9-4), the markers are trimmed, and the trimmed image information is transferred to the first (9-5), but no copy output is performed. After the storage is completed (9-6), an area is specified again using a marker on a document different from the previous document (9-7), and the document is read again by the reading means (9-8). Also, at this time, the editing mode can be reset, for example, by selecting masking mode. After storing this image information in the second memory (9-11
), read out the edited image information from the first and second memories 9-12), and output the combined information by the combining means.
(9-13.9-14), this is illustrated in the first part.
This is figure 0.

In FIG. 10, marks are applied to originals 1a and lb, and trimming or masking processing is performed, respectively, and "C" and "B" are synthesized and output.

Figure 7 shows the synthesis circuit, and shows trimming and masking as a mark editing image, and as described later, black and white inside the marker, image data outside the marker, black and white outside the marker, image data inside the marker, black and white inside the trimming marker , black and white inversion of the outside of the masking marker is also realized using a similar circuit.

The above-described embodiment configured as described above has the following effects.

(1) Since the processing area of the document is specified by a marker, it is possible to easily set the area, and moreover, it is possible to set an area with a complex shape.

(2) Wasteful copies are reduced.

(3) It is possible to combine manuscripts that have been edited in multiple areas.

In the above embodiment, processing such as trimming is performed within the area surrounded by the mark, but it is also possible to perform processing on the area filled in with the mark. In this case, the mark area All you have to do is switch the mode to process the inside or the area filled in with the mark.Also, enter each mode such as masking, white/black inversion in each specifying means,
This mark information may be input to each writing means and combined.

〔Effect of the invention〕

As described above, according to the present invention, areas of a document for region processing (for example, region extraction, erasure, black-and-white inversion, etc.) are designated by marks, and images are synthesized between documents on which multiple region processing is desired. be able to. Therefore, it is possible to easily set an area, and moreover, it is possible to set an area with a complicated shape, and it is possible to reduce unnecessary copies.

[Brief explanation of drawings]

The drawings all show embodiments of the present invention, and Fig. 1 is a block diagram of an image editing device according to the invention, Fig. 2 is a perspective view illustrating reading of a document by a scanner, and Fig. 3 is a diagram illustrating image data and image editing. The mark area detection signal diagram is a block diagram of two image storage memories, FIG. 5 is a block diagram showing the configuration of the image storage memory, FIG. 6 is an explanatory diagram showing signals switched by reading/writing to the memory, and FIG. 7 8 is a block diagram showing the compositing circuit, FIG. 8 is a block diagram for counting the effective sub-scanning area, FIG. 9 is a flowchart showing image editing control, FIG. 10 is an explanatory diagram explaining the image editing process, and FIG. The figure is a block diagram showing the density determination circuit and the 1-pixel noise removal circuit, Figure 12 is a time chart for explaining 1-pixel noise removal, Figure 13 is the block diagram of the mark area detection circuit, and Figure 14 (a). , (b) is the first and second
An explanatory diagram explaining the function of sub-scanning mark detection, Fig. 15 is an explanatory diagram showing the expansion of the mark area, Fig. 16 is a block diagram of the black toggle prevention circuit, and Fig. 17 is a mark with a black line inside the mark. FIG. 18 is a block diagram of a mark area detection unit; FIG. 19 is a plan view showing an example of a marked document;
Figures 20 and 21 are time charts showing each signal when detecting the original in Figure 19, and Figure 22 is the 2 in Figure 3.
A detailed block diagram of value conversion and editing, Fig. 23 is a timing chart corresponding to each signal in the main scanning and sub-scanning directions for the original, and Fig. 24 is a diagram showing the relationship between output data corresponding to editing data from the CPU. be. l...Original, 4...Scanner section, 5.
...Video processing circuit, 6...Data processing control unit, 7...Memory control unit, 9...Mark area detection unit, 10...
・Delay circuit, 11... Binarization and editing circuit, 1
2...CPU, 13.16...Image storage memory, 26...OR gate, 27...
...Excle Sheep OR Gate, 28...Selector. Figure 2 Figure 3 Figure 5 Figure 6 Figure 8 Figure 7 Figure 1 o Figure S and! ``IJ 151 Figure 16 Figure 18! St; Figure 19 Figure 17 Figure 20 Figure 21 Figure 111'''r=o ridge-111 Figure 22 Figure 24

Claims (1)

[Claims] reading means for reading a document image and generating image information; specifying means for specifying a desired area of the document by a mark; generating means for generating an area signal indicating the desired area in accordance with the area specification by the specifying means; processing means for processing the image information generated by the reading means in accordance with the area signal generated from the generation means; a plurality of storage means capable of storing a plurality of pieces of image information; writing in the plurality of storage means; comprising a control means for controlling reading and a means for synthesizing image information read from the plurality of storage means,
A plurality of original images are read, a desired area is specified on each of the plurality of originals by the specifying means, and image information generated by the area signal obtained by the area generating means is processed by the processing means. . An image editing apparatus characterized in that processed image information is stored in the plurality of storage means, the plurality of processed image information is read from the storage means storing the plurality of processed image information, and the synthesized image information is synthesized and outputted by the synthesis means.