JPH0349367A - Mark area detector - Google Patents

Abstract

PURPOSE:To correctly detect a mark area even at the time of detecting plural mark areas by inputting a mark read signal generated, by scanning and generating the signal of the position of the rear end based on position information of the rear end of an already scanned line and generating a mark area signal by a third signal generating means. CONSTITUTION:The picture (picture data (b)) outputted from a video processing circuit 5 is inputted to a mark area detecting part 9 of a data processing control part 6, and a mark area signal f25 is generated by the mark area detection processing. Since the mark area signal f25 is delayed by main scanning and subscanning, the delay state of picture data (b) is matched to that of the mark area signal f25 by a picture data delay circuit 10. This delay circuit 10 delays data by a latch in the main scanning direction and delays it by a memory in the subscanning direction. A CPU 12 outputs the binarizing threshold level and data of trimming, masking, white/black inversion, or the like of the mark area to a binarizing and editing circuit 11 of picture data by the input from an operation board.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a mark area detection device, which specifies an arbitrary area on a document, extracts the arbitrary area, erases it, performs processing such as black and white inversion, and memory composition. The present invention relates to a mark area detection device that performs.

[Conventional technology]

With digital copy machines, manual scanners, facsimile machines, etc., if there is a part of the information on the document that does not need to be copied, the relevant part of the document must be cut out before making a copy, or the relevant part of the document must be copied. The necessary parts were copied by covering them with white paper and making copies.

However, with this conventional method, the original must be processed, which may damage the original, and in addition to being time-consuming, it is necessary to obtain multiple copies with unnecessary parts removed. In some cases, for example, the white paper covering unnecessary parts may shift, making it impossible to obtain identical copies.

In order to solve this problem, a color felt marker or the like is used to mark an arbitrary area on the document, and by reading the mark designated area, the area for processing and memory composition is designated.

For example, as shown in FIG. 17, area processing when there are a plurality of mark areas in the main scanning direction will now be described.

FIG. 16 is a block diagram of a conventional mark area detection unit, and FIG. 17 is an explanatory diagram showing the mark area when two marks are written in parallel in the main scanning direction to explain the block diagram of FIG. 16. 18 and 19 are the timing chart of FIG. 16 and the timing chart of FIG. 17 showing the mark area.

First, when two marks are lined up in parallel as shown in FIG. 17, a mark detection signal f19 is input to the mark area detection section of FIG. 16. Sector circuit 108
Then, the signal is set by the first mark signal. Furthermore, the signal ft1 from the reset block is reset by the last mark signal in the main scanning direction.

Next, detection of the tip when there are two marks will be explained.

fi+ is a set signal, f2. This is the signal from the beam set block, and f2° is the signal from detecting the previous line in the mark area, and f20 and f! ++' 23 is AND game) The signal obtained by ANDing 109 becomes f24. Here, the reset signal r! , the last mark signal end of the previous line becomes the reset edge, so the first mark area of rza is the same as the current line, but the rear end of the next mark becomes the mark area of the previous line. In order to prevent this, the mark area f of the current line is further ORed with the mark of the current line using the OR gate 110.
z5 is realized.

Next, a case where the mark narrows in the sub-scanning direction will be described.

The current line ■ shown in FIG. 19 is input to fo in FIG. 16, and f! l+'! 3+'Ill. AND with fffi4 and the current line fl'l
If you take the error detection area C12 as shown in FIG.
An error area with respect to the previous line will occur at the rear end of the second mark area. As mentioned above, this error area with the previous line is because the signal f0 from the reset block is at the edge of the mark area of the previous line, so the OR gate 110
This error occurs because f19 is narrower even when ORed with f19. However, since the reading density in the sub-scanning direction is 1/16 m, this error does not cause any problem in the mark area detection accuracy, but the detection area C is
This error occurs because the area sandwiched between two marks from the point where the mark area has widened to its maximum cannot be detected by this circuit, and the mark area does not become narrower.
As shown in FIG. 7, the detection area C appears, and this portion is also identified as a mark area, resulting in extremely poor accuracy as a mark area.

Next, the reset block will be explained. FIG. 20 is a timing chart of the reset block, and FIG. 22 is an explanatory diagram of each signal. Here, FGATE is an effective reading area in the sub-scanning direction, LGATE is an effective reading area in the main-scanning direction, and LSYNC is a timing signal in the main-scanning direction.

The counter 113 counts up during the valid period of LGATE, and the counter value is shown in FIG. Here, when the mark signal f19 is input, f
The counter 113 is latched by the F/F 115 with the signal of the inverter 114 which inverts the counter 113.

This latch output is further connected to LGA using F/F 116.
It is latched by a signal from an inverter 117 that inverts TE. At this time, the F/F 115 is cleared once by LSYNC, and also latches the counter value when a mark comes. The output of the F/F 116 and the counter value of the counter 113 are then compared by the comparator 112. The output of the F/F 116 becomes the address of the previous mark area, and the value of the counter 113 becomes the address of the current line. Therefore, the output of the comparator 112 becomes the mark area signal of the previous line, and the reset signal f
23 is output. Moreover, when LGATE becomes L here, the counter value is cleared, so the rts reset signal becomes H.

rProblems to be Solved by the Invention] As mentioned above, in conventional mark area detection, when a plurality of marks are arranged in parallel in the main scanning direction and the mark area narrows in the sub-scanning direction, the area surrounded by the marks and the area In between, even though the mark area was narrowed, the detection area did not become narrower, and an erroneous detection area C occurred as shown in FIG. Therefore, when writing a mark, it is necessary to make the shape of the mark rectangular, to consider the arrangement of the mark, and to take into account the reading direction (main and sub-scanning directions) of the marker document.

Further, in conventional mark area detection, only the area outside the mark is detected, so when trimming (extracting an image inside the marker) is performed, for example, the mark itself may be output in the image. In addition, in order to prevent the mark itself from being output, the binarization threshold level was set to a density at which the mark would not appear, so if the text was too light, the text would not appear or would be blurred.

The present invention has been made in view of the above-mentioned problems of the prior art and has been made to solve this problem.The present invention has an object to be able to correctly detect a mark area even when a plurality of mark areas are to be detected; An object of the present invention is to provide a marked area detection device capable of detecting an outer area and an inner area in area detection.

[Means to solve the problem]

In order to achieve the above object, the present invention provides a means for scanning and reading a document image to generate image information, a specifying means for specifying a desired area of the document by a mark, and a means for generating a reading signal for the specified mark. a first signal generating means for detecting positional information of the rear end of the mark in the main scanning direction based on the mark reading signal; a second signal generating means for generating a signal of the mark area; a third signal generating means for generating a mark area signal based on the mark reading signal and the position signal; the mark area signal and the mark reading signal; a signal for the position of the rear end based on the position information of the rear end of the already scanned line by inputting the mark reading signal generated by the scanning; The mark area signal is generated by the signal generating means.

[Operation] The above means generates a position signal based on position information at the rear end of the mark on the previous line. Therefore, the rear end of each mark can be identified and the mark area of each mark can be generated.

〔Example〕

Embodiments of the present invention will be described below based on the drawings.

FIG. 1 shows a block diagram of the configuration of an image processing apparatus that is an embodiment of the present invention. 4 is a scanner section, and this scanner section 4
As shown in FIG. 2, the image of the reading line l of the original l is focused on the CCD line sensor 3 via the coupling lens 2, and the relative relationship between the original 1 and the CCD line sensor 3 in the Y direction is While updating the read line by mechanically shifting the position (sub-scanning), scan each line 40 times from left to right in the X direction.
Read at a density of 0 dpi (ζ16 pixels/tsuru) (main scan)
. The read signal becomes an analog signal having an amplitude corresponding to the density of each pixel. 5 is a video processing circuit which A/D converts the read signal a, performs background removal processing, shading correction processing, MTF correction processing, etc. on it, and generates 6-bit (64 gradation) image data 6 (the higher the value, the more This is a circuit that generates high-density). Reference numeral 6 denotes a data processing control unit. This data processing control unit 6 binarizes the read data by setting black pixels to “L”: H level and white pixels to “0”: L level, and performs extraction (trimming) of specified areas. ), erasure (masking), etc., to generate write data d. 8 AO the laser beam
This is a laser printer that modulates (1: recording, 0: non-recording) and prints out on recording paper.

In the above-mentioned image processing device, the control device that controls each of these components, the scanner section 4, the video processing circuit 5, and the laser printer 8 are well-known technologies and do not directly relate to the features of the present invention, so a detailed explanation will be given. Omitted.

The data processing control unit 6 detects a mark in a predetermined density range written on the original 1 or an area surrounded by the mark, and performs trimming and masking on the original based on this.

In this embodiment, a mark using a color felt pen (hereinafter referred to as a color mark) is used as a mark for a predetermined density range.
Assume that This is because colored felt markers are already available in various densities, which facilitates marking in a predetermined density range and is advantageous in practice.

FIG. 4 is a block diagram showing the configuration of the density determination circuit and l-vixel noise removal circuit. 34 and 35 are comparators, and these two comparators 34 and 35
constitutes a density determination circuit, and detects halftone read data A. In other words, by comparing read data A and two threshold levels Bl and BTt (B tI>B y's), a signal f1 becomes B□>A and a signal f becomes BTt<A.
, get . Here, threshold level B? l is set to the same level as the threshold level for simple binarization. As a result, in simple binarization, a so-called faint mark is detected in a range that is not determined to be black. Further, the threshold level BT'l is set to an appropriate level for stains on the background of the original, density unevenness, and the like. 36 is a flip-flop, 37°38 is O
The R gate, 39.40, is an AND gate, which constitutes an l-vixel noise removal circuit.

FIG. 5 is a time chart for explaining l-pixel noise removal.

As an example, assume a signal t as shown in FIG.

Note that the numbers in the time chart indicate the main scanning addresses of the read pixels. The signal f here is the main scanning address 5
The place where noise is added and f,="l" becomes f,=@
The color mark is detected between main scanning addresses 1 to 4 and 6 to 8, and f+='l'. The clock CK is a clock signal whose period corresponds to one pixel during main scan scanning. f is a signal obtained by latching one cycle of signal r using flip-flop 36, and by passing signal f2 and signal f3 through OR gate 37, a signal f4 from which noise has been removed is obtained.

Since the signal f4 is longer than the signal f before noise removal by one period, the signal f4 is latched for one period using the flip-flop 36 to obtain the signal f4 and the signal f4. 5 is passed through the AND gate 39, noise is removed and the signal f has the same length as the signal f.
get s. Also for the signal f3, the flip-flop 36,
A similar operation is performed using an OR gate 38 and an AND gate 40 to obtain a signal f.

get. Finally, by passing the signal f6 and the signal f through the AND gate 41, a signal f indicating the mark density range is generated.
, can be obtained.

In this example, the removal of 1-pixel noise has been described, but by changing the system, it is possible to remove 2-pixel, 3-pixel, old, n-pixel noise. Further, threshold levels BTI and BTt can be varied.

FIG. 6 is a block diagram of the mark area detection circuit.

For example, even if a halftone is detected in a minute area of one to several pixels due to dirt on the background, etc., it is not detected as a mark area. That is, over a certain area, only in the case of an intermediate tone, a certain area including that area is set as a mark area.

The basic unit of this mark area is 12 in this example.
The unit is X 12 pixels, but this can be changed by changing the system. A signal fll indicating the mark density range is input to the first sub-scanning mark detection section 42 and the second sub-scanning mark detection section 43.

FIG. 14 (al indicates the function of the first sub-scanning mark detection section 42. In this first sub-scanning mark detection section 42, 12
The basic unit of area of ×12 pixels is scanned in the sub-scanning direction, and when the signal f1 = “1” in all 12 pixel blocks, that block is set to “0” (=1), and even if only one pixel has the signal f, = “0”, the block is “NG” (=0
). And when 12 block scanning is completed,
When all the blocks are "OK", the first main scanning mark detection unit 44 identifies this basic unit of 12 x 12 pixels as a mark area, outputs the signal f, -"1", and outputs the signal GATE. ="1".

FIG. 7(b) shows the function of the second sub-scanning mark detection section 43. In this second sub-scanning mark detection section 43, 12
Within a block of pixels, a certain probability (2/3 in this example)
In the above, when the signal f = “1”, the block is “O”.
K" (=1), and when the signal f is less than "1", the block is determined to be "NG" (=0).

When the scanning of 12 blocks is completed, the second main scanning mark detection unit 43 determines that if the block is "OK" with a certain probability (2/3 in this embodiment) or more, 12 blocks are scanned.
Identify the basic unit of X 12 pixels as the mark area,
signal,. ="1" is output. When the mark area has already been detected by the first sub-scanning mark detection section 42 and the first main-scanning detection section 44, the signal GA is output.

Since TE="l", the signal fil""1" is output through the AND gate 47.The signal f and the signal f
ll is a signal fI! that finally indicates whether or not it is a marked area through an OR gate 46. is output. Even if the area identified as the mark area is interrupted in the middle and divided by white, or if a small area within the mark is white or black, it is ignored and the mark is continuous. In order to detect
The main scanning direction is expanded through the sub-scanning mark expansion section 49, and the sub-scanning direction is expanded through the sub-scanning mark expansion section 49, and a signal f1 indicating the mark area is output.

In this embodiment, as shown in FIG. 8, the expansion is performed by 8 pixels in the main scanning direction and 6 pixels in the sub-scanning direction, but this can also be changed by changing the system.

Furthermore, when marking the black print with a color felt-tip pen, the black print part is still black and has a high density. In this way, if the halftone area is divided by black, the halftone area is expanded to include the black part for detection. This is called Kurotogire.

Fig. 9 is a block diagram of the black mark prevention circuit, and Fig. 1O shows a state in which a black line enters a mark and the mark is interrupted, with the horizontal axis in the main scanning direction, and the corresponding signals. This is a diagram showing the following.

Signal fl with marks extended in the main scanning direction and sub-scanning direction
The signal obtained by inverting l through the inverter gate 50 is converted to the signal f.
Let it be lS. The signal f,+4 is a signal indicating a black area, and the signal f,4="1" in the black area.

Signal folk is obtained by passing signal fls and signal f14 through NAND gate 51. The signal rt& is latched by the shift register 52 to obtain the signal fl'l. In this example, 16 pixels (approximately 1 fl) are latched, and including the previously expanded 8 pixels in the main scanning direction and 6 pixels in the sub-scanning direction, 24 pixels in the main scanning direction (approximately 1.5 m) and 22 pixels in the divided scanning direction (
(approximately 1.4n) to compensate for equinox toggle.

This can be changed by changing the system.

By passing the signal fl'l and the signal r+s through the NAND gate 53, a signal fl'+ with no black toggle is obtained.

Then, by passing the signal r+s through the inverter gate 54, a signal rtq indicating a mark compensated for black toggle is obtained. Similar operations are performed in the sub-scanning direction as well.

FIG. 11 is a circuit block diagram of the present invention, FIG.
FIG. 3 is a timing chart for detecting the upper and lower portions of marks.

First, the case of detecting the upper part of a mark will be explained.

Input the mark area of the line ■ as [19] shown in FIG. At this time, the memory 55 outputs the mark area of the previous line ■. The mark area output from this memory 55 becomes the read clock of the memory 56, and the rear end address (22
0), the rear end address (420) of the second mark B is output. In other words, the memory 56 is a memory that stores the mark generation address. The first . The rear end address of the second marks A and B is the front end of the mark on the previous line ■ (for mark A, the address (,120)
, mark B, an address is generated at address (320)), and the address is compared with the counter 57 of the current line by a comparator 58, and this comparator 58 outputs a signal when they match. The output of this comparator 58 and L
GATE and is ANDed by an AND gate 59, and this output is input to the reset of the D flip-flop 60. Here, the set signal of the D flip-flop 60 is the marker area of the previous line. This is because the signal stored in the memory 61 serves as a set signal for the marker on the previous line. Here, this reset signal is never outside the mark area at the rear end of the current line (2). In other words, the previous line ■ and the current line ■ are necessarily connected by the width of the mark because the mark has a thickness. Therefore, this line before “1.
The mark area is detected by the mark set signal of and the reset signal of the previous line ■. Furthermore, OR gate 6
A mark area is created in step 2. Here, the F/F 63 latches the trailing end address of the mark on the current line 2 of the counter 57 using an inverted signal obtained by inverting the mark area signal outputted from the OR gate 62 by the inverter 56 . This F/F
The latch signal of 63 is written to the memory 56. This latch timing is a signal obtained by inverting the mark area signal from the OR gate 62 by an inverter 64 and shifting it by several pixels by a shift 65. In other words, the rear end address of the first mark is stored in the memory. , the rear end of the mark on the previous line ■ is output from the memory to the front end of the mark on the previous line ■. Therefore, as described above, the output of the comparator 58 is always output to the rear end of the previous line (2). In this way, in this embodiment, when the marker widens at the top of the mark, the signal is the same as the conventional mark area detection signal, but when the marker narrows, the conventional problem is solved.

Next, detection when the mark becomes narrower will be explained.

The current line 0 is input to the circuit of FIG. 11 as fl. Similarly, the memory 55 outputs the OR between the mark of the previous line (3) and the mark area of the line [phase] before the previous one.

An address is generated from the memory 56 from the tip of the mark area (first mark A, second mark B) of the previous line (2) (address (240) for mark A, address (440) for mark B). Here, the value of the counter 57 and the address of the count value memory 56 is determined by the comparator 58.
When the signals match, a signal is issued from the comparator 58.

The tip of '7-ka f19 of the front line ■ and comparator 5
The mark area of the front line ■ is generated from the rear end signal of the marker of the front line ■ obtained from the D flip-flop 6o. At this time, the count value of the counter 57 mentioned above (
The marker address value) is latched by the flip-flop 63 at the rear end of the mark of the current line @, and the address value obtained by this latch is combined with the mark of the current line @ obtained by the OR gate 62 and the mark area of the previous line 0. Store the address value at the end of the .

Therefore, even if a plurality of marks are arranged in parallel in the main scanning direction and the mark area is narrow in the sub-scanning direction, the detection area does not occur as in the conventional case, and the mark area can be obtained. However, since the mark area to be output is the mark area of the previous line ■ which is l line behind the current line @, a delay of 1547 minutes is required to obtain a suitable image.

Further, 67 in FIG. 11 is an exOR gate. rzs
The output of is the area outside the mark, and by taking the exOR of fo and the mark width at the exOR gate 67,
The area inside the mark is output as f□'. This is because if only the outside of the mark is output as a mark signal to the next stage of mark editing, for example, if you want to output only the inside of the mark area, the mark itself may appear in the image because the outside of the mark is the mark. , signal rzs outside the mark, signal f2 . This is to switch . still,
Another reason why the mark itself appears in the image is that the mark density is medium density, so if there is a darkened part due to double writing of the mark, or if you want the output image to be less dark, you may need to binarize the image. It may appear when changing the level.

As described above, according to the embodiment, it is possible to detect a halftone and a portion surrounded by halftones, and the shape thereof is not limited to a rectangle but can be various. Further, the number of portions surrounded by halftones in one document is not limited. Moreover, since the detection is performed in parallel with the original reading operation, there is no need to perform area detection in advance by, for example, pre-scanning.

That is, for example, it is possible to extract a designated area and simultaneously copy the image of that area. Also,
In this embodiment, a mark made by colored felt Ben is targeted, but this mark has no relation to anything else as long as it has a density within a specific density range, and furthermore, it does not require a special sensor, light source, etc. for detection. Furthermore, since the mark is extended to detect the halftone area, even if the mark is divided by white or black, the area can be detected effectively.

Here, the relationship between the image data and the mark area detection signal will be explained.

The image output from the video processing circuit 5 is (image data b
) enters the mark area detection unit 9 of the data processing control unit 6, and generates the mark area signal ft5 by the mark area detection processing described above. Since the mark area signal fts is delayed in the main scanning and sub-scanning directions, the image data delay circuit 10 matches the delay state with the mark area signal rzs so as to match the delay with the image data b. . The delay circuit IO uses a latch in the main scanning direction and a memory in the sub-scanning direction. C.P.
U12 outputs data such as a binarization threshold level, mark area trimming, masking, black and white inversion, etc. to the image data binarization and editing circuit 11 based on input from the operation board.

FIG. 14 shows a detailed block diagram of the binarization and editing circuit 11 of FIG. 3. Furthermore, FIG. 15 shows the relationship between the editing data from the CPU 12 and the output data d corresponding to M1-M3.

In Fig. 14, 95.96 is a comparator, 97°98, 106 is a selector, 99.100, 103 is an inverter, and 101, 102, 104, 105 are A
ND gate 107 is a dither ROM.

First, a method of binarizing input data g will be explained.

In the case of character output, the comparator 95 compares the binary level H from the CPU 12 with the input data g, and outputs the binary signal I. Furthermore, using the dither method, the dither ROM 107 and the input data are compared in a comparator 96 as pseudo halftone output, and dither data (halftone data) is generated.
Output J, and if the operation board is in character mode,
Data K from CPLJ12 becomes 0, and selector 97 outputs I to L.

In the case of halftone (photo) mode, the data from the CPU 12 becomes 1, and the selector 97 outputs J to L.

At this time, data M1 to M3 of the CPU 12 corresponding to the selector 106 becomes O, and a signal corresponding to the input A of the selector 106 is output.

In addition, in marker editing mode, the marker supports halftone density, so the input document is basically a character document with a clear white/black ratio, that is, the background is whiter than the lower limit level of the marker, and the characters are It is assumed that the data is blacker than the marker upper limit level.

As explained above, since the target is a character manuscript, K becomes O when editing markers. rzs, f! The marker detection area (if determined to be a marker area, it becomes an H:1 signal) signal from No. 5 comes in, and the following processes can be performed.

(11 Masking: In other words, when erasing information in the mark area, an AND gate 101 performs the logical product of the signal obtained by inverting the mark area signal rzs by the inverter 100 and the binary image signal is input to the B input of the selector 106, and the information of the CPU 12 is erased.
With the commands M1 to M3, Ml:1, M2. By setting M3;O, masking data is output to the d output.

(2) Trimming: In other words, when extracting only the information within the mark area, the AND game) At 102, the mark area signal ft%' and the binary image signal are ANDed and only the information within the mark area is extracted. Then manually enter C input of selector 106, and input M2 with commands M1 to M3 of CPU 12.
:1, Ml, M3i0, the d output has the following:
Masking data is output.

(3) Black and white reversal inside the marker Image data outside the marker 2 In other words, only the information inside the marker in the image data is inverted in black and white, and the image data outside the marker is output as is.
Input mark area signal f of select signal of selector 98
0 selects image data and inverted data, and when a mark area signal is generated, inverted data is selected and output. Also, the commands M1 to M3 of the CPU 12 are Ml, M2:1. M3:0.

(4) Outside marker black and white inverted image data inside marker: This is
(3) The signal obtained from the inverted black-and-white inside marker image data outside the marker is inverted by the inverter 103, and C
The commands M1 to M3 of the PU12 are Ml, M2:0. M3
:1.

(5) Black and white inversion within trimming marker: This is done in the same way as the trimming process in (2) for the image of only the marked area.
By game D 05, mark area signal f! 5' and the inverted signal of the image data, and the commands M1-M3 of the CPU 12 are
M3:1. M2:0.

(6) Masking marker outside black and white inversion: This is an AND operation similar to the masking process in (1) for the image outside the marked area.
The gate 104 outputs the inverter 100 of the mark area signal f□ and the inverted signal of the image data, and the commands M1 to M3 of the CPU 12 are
l: O, M2. M3:l.

〔Effect of the invention〕

As described above, according to the present invention, multiple mark areas can be detected correctly.

As a result, the shape of the mark area can be made into a shape other than a rectangle, increasing the degree of freedom in specifying the area, and there is no need to consider the arrangement of marks and the reading direction of the marker document, improving operability.

Furthermore, the mark area can be detected outside or inside the mark. As a result, the mark itself is not output on the image, and the binarization level can be freely varied, making it possible to output even thin characters.

[Brief explanation of drawings]

1 to 15 show embodiments of the present invention. FIG. 1 is a block diagram of an image editing apparatus according to the present invention, FIG. 2 is a perspective view illustrating reading of a document by a scanner, and FIG.
FIG. 4 is an explanatory diagram showing the relationship between image data and mark area detection signals, FIG. 4 is a block diagram showing the density determination circuit and l pixel noise removal circuit, and FIG. 5 is a time chart for explaining l pixel noise removal. Figure 6 is a block diagram of the mark area detection circuit, Figures 7(a) and (b) are explanatory diagrams explaining the function of first and second sub-scanning mark detection, and Figure 8 shows expansion of the mark area. Explanatory drawings, Fig. 9 is a block diagram of the black toggle prevention circuit, Fig. 1θ is an explanatory drawing showing a state where a black line enters the mark and the mark is interrupted, and each signal corresponding to this, Fig. 11 is a block diagram of the black line prevention circuit. A block diagram of the area detection section, FIGS. 12 and 13 are time charts showing each signal when detecting the upper or lower part of the mark,
Figure 14 is a block diagram showing the synthesis circuit, Figure 15 is the CP
16 to 22 are diagrams showing the relationship between output data corresponding to editing data from U, and are for explaining a conventional mark area detection device, and FIG. 16 is a block diagram of a mark area detection unit, Fig. 17 is an explanatory diagram showing an example of marking a document, Figs. 18 and 19 are timing charts showing each signal when detecting the upper or lower part of the mark, and Figs. 20 to 22 are each 5 is a timing chart showing the relationship between signals. 1...Original, 4...Scanner section, 5.
. . . Video processing circuit, 6 . . . Data processing control section, 9 . . . Mark area detection section,
10... Delay circuit, 11... Binarization and editing circuit, 12... CPU, 13.16...
...Image storage memory. 11 5F! Figure Figure Figure 3 Figure 8 Figure 9 Figure 17

Claims (1)

[Claims] means for scanning and reading an original image to generate image information; specifying means for specifying a desired area of the original by a mark; first signal generating means for generating a reading signal for the specified mark; a detection means for detecting positional information of a trailing edge of the mark in the main scanning direction from the mark reading signal; and a second signal generator for generating a signal of the position of the trailing edge of the mark in the main scanning direction in response to the positional information. means, third signal generating means for generating a mark area signal based on the mark reading signal and the position signal, the mark area signal;
and a synthesizing means for synthesizing the mark reading signals,
A mark reading signal generated by the scanning is input, a signal indicating the position of the rear end is generated based on the position information of the rear end of the already scanned line, and a mark area signal is generated by the third signal generating means. A mark area detection device characterized by a mark area detection device.