JPH02250510A - Operational amplifier - Google Patents

Abstract

PURPOSE:To simplify the constitution of a bias circuit together with reduction of the power consumption for an operational amplifier by setting the levels of the bias power supplies applied to the gates of the cascaded transistors at the potential of a non-inverted input terminal. CONSTITUTION:The gates of N channel depletion type MOS transistors TR M11 and M12 are set at a 3rd constant potential source ACM. Thus it is possible to prevent the influence of the parasitic capacity produced between an inverted input terminal and the drain of a TR M1 and therefore to need no bias circuit which produces the bias power supplies to be applied to the gates of both TR M11 and M12. Thus the constitution of a bias circuit is simplified and the power consumption is reduced for an operational amplifier.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an operational amplifier, and particularly to an operational amplifier that is used in a switched capacitor circuit and whose first stage has a cascade structure.

[Conventional technology]

Conventionally, operational amplifiers used in switched capacitor filters are designed to prevent the effects of parasitic capacitance that occurs between the gate and source and between the gate and drain of the input transistor.
As shown in FIG. 3, the first stage 1 has a cascade structure. The first stage differential amplifier circuit l includes differential transistors M31 and M3 that commonly receive a constant current from a current source transistor M35.
2, transistors M41 and M42 for preventing the influence of parasitic capacitance generated between the inverting input terminal VIN- and the drain of the transistor M31, and their active load transistors M33 and M34.

The second stage amplifier circuit 2 includes a current source transistor M36, an output transistor M37 that receives a signal from the first stage differential amplifier circuit 1, a phase compensation transistor M30, and a capacitor C1. Further, the bias circuit 3 includes a current source transistor M38 and a current source transistor M38.
5. A bias voltage VBI is applied to M36, and the bias circuit 4 includes a current source and a transistor M39. M40
and transistor M41. Bias voltage VB to M42
It is giving 2. VDD is the first constant potential source, GND is the second
A constant potential source ACM is a third constant potential source which is a reference level of a signal of the differential amplifier, and VOUT is an output terminal. Also, M
31. M32. M35゜M2O, M2S, M39. M2
O, M41. M42 is an N-channel type MOS) transistor, M2O, M33, M34 . M37 is an N-channel type MOS transistor.

In the conventional operational amplifier, the bias power supply VB2 is provided by the bias circuit 4, which has the disadvantage that the bias circuit becomes complicated and the power consumption increases.

[Problem to be solved by the invention]

The conventional operational amplifier mentioned above has a complex bias circuit,
It had the disadvantage of high power consumption.

An object of the present invention is to simplify the bias circuit and provide an operational amplifier with low power consumption.

[Means to solve the problem]

According to the present invention, a constant current source, first and second field effect transistors each receiving a constant current from the constant current source at their respective sources, and a first field effect transistor whose source is connected to the drain of the first field effect transistor. first and second load circuits each including a No. 3 field effect transistor and a fourth and a fifth field effect transistor serving as loads connected to respective drains of the second and third field effect transistors; An input terminal connected to the gate of the first field effect transistor, a constant potential source connected to each gate of the second and third field effect transistors, and connected to the drain of the fourth or fifth field effect transistor. An operational amplifier is obtained having an output terminal.

As described above, according to the present invention, the gates of the second and third field effect transistors are connected to a common constant potential source, so the number of constant potential sources is small, and the bias circuit is simple. Power consumption can also be reduced.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 shows a circuit diagram of an embodiment of the present invention. In the figure, 1 is a first-stage differential amplifier circuit, 2 is a second-stage amplifier circuit, 3 is a bias circuit, VIN- is an inverting input terminal, and VOUT is an output terminal. Further, VDD is a first power source, GND is a second constant potential source, ACM is a third constant potential source, and VB is a bias power source. In addition, Ml and M2 are N-channel first-stage differential pMO8
) transistor, M3. M4 is a P-channel load MO8) transistor, M5. Me is an N-channel constant current source MOS transistor, M7 is a drive stage P-channel MOS transistor, M8 is an N-channel MOS transistor of the bias circuit that creates the bias power supply VB, Ml 1 and Ml 2 are reference levels of the operational amplifier, and M2 This is an N-channel desorption type MOS transistor biased by a third constant potential source ACM having a gate potential of . Further, C1 is a phase compensation capacitor, and a feedback loop formed by a series connection of a capacitor CI and an on-resistance of a P-channel transistor MO constitutes a phase compensation and zero compensation circuit. In addition, the electric current source is a current source.

N-channel depletion type MO8) transistor Ml
1. By using the third constant potential source ACM for the gate of Ml2, it is possible to prevent the influence of parasitic capacitance that occurs between the inverting input terminal and the drain of the transistor M1, and the bias applied to the gates of the transistors Mll and M12 can be prevented. A bias circuit to create a power supply becomes unnecessary. Therefore,
Since the bias circuit is no longer necessary, power consumption is reduced and the IC chip area is also reduced.

Here, transistor Ml 1. Although Ml 2 is a depletion type MOS transistor, it is clear that a non-doped transistor may also be used.

Next, another embodiment of the present invention is shown in FIG.

All symbols in FIG. 2 are the same as those in FIG. In this embodiment, the cascade is connected only to the drain side of the first stage inverting input transistor M1, but in this case also, the gate of the cascade transistor Mll is connected to the third constant potential source ACM which is the potential of the non-inverting input terminal. By doing so, it is possible to prevent the influence of parasitic capacitance that occurs between the inverting input terminal and the drain of transistor M1, and a bias circuit that creates a bias power supply to be applied to the gate of transistor Mll is unnecessary, so the power is small. Therefore, the chip area of the IC becomes smaller.

Further, it is clear that the transistor Mll may be a non-doped transistor.

〔Effect of the invention〕

As explained above, the present invention is an operational amplifier with a cascade structure used in a switched capacitor circuit, etc.
By using the potential of the operational amplifier's non-inverting input terminal as the bias power supply applied to the gate of the cascade transistor, a bias circuit becomes unnecessary, reducing power consumption and reducing the IC chip area. effective.

1...First-stage differential amplifier circuit, 2...Second stage
Stage amplifier circuit, 3, 4... bias circuit, VIN
-...Inverting input terminal, VOUT...Output terminal, VDD...First constant potential source, GND...
...Second constant potential source, ACM...Third constant potential source, I, 1. , It... Current source, VB, V
BI, VB2...Bias power supply, MO~M12
．． M30~M42...MOS) transistor, C
1...Capacity.

Agent Patent Attorney Susumu Uchihara

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing one embodiment of the present invention, FIG. 2 is a circuit diagram showing another embodiment of the invention, and FIG. 3 is a circuit diagram showing an example of a conventional operational amplifier. I; # stage differential 4-width circuit 2: 2nd Pi low voltage circuit 3: High-ass cleavage 4 VxN-1 inverting input terminal and 1st figure GA/ρ: 2nd current source ACM: 3rd constant potential drift echo 'EItyA voltage Vδ: Bias power supply r: MJ stage combined action booster 2: @2p9 1st circuit 3: Bias circuit VxN-: Source GND: ￥Jzge source Acs: ￥Jzge source ACs: ￥ｲｽ罎I; yL source v8: No.

Claims (1)

[Claims] In an operational amplifier including an input differential transistor and a common gate transistor cascaded to at least one of the input differential transistors, the gate of the common gate transistor is
An operational amplifier, characterized in that the operational amplifier is connected to one gate of the input differential transistor.