JPH02250371A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce noises outside an LSI for preventing malfunction by adding an inductance component and a resistance component for increasing voltage drop to the LSI. CONSTITUTION:An inductance component 5 and a resistance component 5R are added to an LSI 1 for increasing voltage drop inside the LSI 1. Therefore since the voltage drop inside the LSI increases, the voltage drop outside the LSI is relatively decreased. Thus the noise level outside the LSI can be reduced for preventing malfunction without reduction in electrostatic withstand voltage and operation speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a technique that is effective when applied to semiconductor devices, for example, a technique that is effective when applied to semiconductor devices that increase speed and performance. It is related to.

[Prior Art] Recently, noise has been generated outside of LSIs, for example, in peripheral buffer circuits, and this noise has become a problem because it causes malfunctions of semiconductor devices.

The principle of this noise generation will be explained with reference to FIG.

FIG. 6 is a circuit diagram showing a conventional semiconductor device.

In the figure, a dotted line 1 indicates the inside of the chip. A power supply wiring 8b is arranged inside the chip 1, and a large number of bonding pads 2.2a, 2b, 2c connected to the power supply wiring 8b are formed on the chip. The above bonding pad 2 has an output terminal (
An external circuit 9 is connected via a low level output pin (3a). High for pounding pads 2b and 2c.
Output terminals 6 and 7 that change from h to low level are connected to each other, and external load capacitances 6c and 7c are connected between them.
are in a state where they are each interposed. A Vss (ground) terminal 4' is connected to the bonding pad 2a, and an inductance 4L' and a resistor 4R' are connected between them.
are in a state where they are each interposed. The inductance 4L' and the resistance 4R' are constructed from bonding wires outside the LSI, package leads, and the like.

Since the conventional semiconductor device is configured in this way, when the output terminals 6 and 7 change from Hil<h to Low level, the charges stored in the external load capacitors 6c and 7c, respectively, become steep currents. Power supply wiring 8b inside chip 1
flows into. Then, the inductance 4L outside the LSI
A noise voltage proportional to the steep rate of change of the current is generated in the power supply wiring 8b by the resistor 4R', and this noise voltage is transmitted to the external circuit via the output terminal 3a which outputs another low level. 9, causing the semiconductor device to malfunction.

FIG. 7 is a diagram showing the state of the noise voltage at the output terminal 3a, and as shown in the figure, the noise voltage is very large, indicating that non-ignorable noise is occurring. . Specifically, the values of inductance and resistance outside the LSI are as follows. 4L' =
10.24nH, 4R' = 0.135Ω.

Moreover, this noise is a problem because it tends to become even larger due to an increase in the amount of current that is required in recent years as the speed of semiconductor devices has been increased and the performance has been improved due to an increase in bus width (increase in the number of bits).

Therefore, in recent years, for example, the power supply wiring that supplies the address bus, data bus, etc. is separated so that even if noise occurs on one side, noise does not occur on the other side, and a pre-buffer is installed before the buffer. The noise has been reduced by reducing the gate width and reducing the amount of current.

[Problems to be Solved by the Invention] However, the above noise countermeasures have the following problems.

That is, in the method of separating power supply wiring, there is a problem in that a potential difference is likely to occur and the electrostatic withstand voltage is reduced.

In addition, in the method of inserting a pre-buffer before the buffer or reducing the gate width to reduce the amount of current, there is a problem that the current driving ability decreases and the operating speed of the semiconductor device decreases. .

The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device that can reduce noise outside the LSI and prevent malfunctions without reducing electrostatic withstand voltage and operation speed.

[Means for Solving the Problems] Representative inventions disclosed in this application will be summarized as follows.

That is, an inductance component and a resistance component are added to the inside of the LSI to increase the voltage drop inside the LSI.

[Function] According to the above-described means, since an inductance component and a resistance component are added inside the LSI, the voltage drop inside the LSI becomes large, and the voltage drop outside the LSI becomes relatively small. , L.S.
The noise voltage outside the LSI is reduced, and the above object of reducing noise outside the LSI and preventing malfunctions is achieved without reducing electrostatic withstand voltage and operation speed.

[Example] Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a circuit diagram of an embodiment of a semiconductor device according to the present invention. The outline is as follows.

In the figure, a dotted line 1 indicates the inside of the chip. Inside the chip 1, a power supply wiring 8 and a power supply wiring 8a connected to the power supply wiring 8 are arranged.
A large number of bonding pads 2.2a, 2b, 2c are formed on the chip to be connected to the power supply wiring IIa 8.8a. The above-mentioned bonding pads 2 and 2a are connected to the power wiring 8, while the bonding pads 2b and 2c are connected to the power wiring 8a.
are connected to each. Pounding pad 2 above
An external circuit 9 is connected through an output terminal (Low level output pin) 3. Ponding pad 2b
, 2c are connected to output terminals 6 and 7 that change from High to Low level, respectively, and external load capacitances 6c and 7c are interposed between them, respectively. A Vss (ground) terminal 4 is connected to the bonding pad 2a, and an inductance 4L is connected between them.
, 4R are interposed respectively.

The inductance 4L and resistance 4R are constructed from bonding wires outside the LSI, package leads, and the like. Between the power supply wirings 8 and 8a, that is, in the power supply wiring part connecting the output terminals 61 and 7 and the Vss (ground) terminal 4, there is a noise canceller 5 for increasing the voltage drop inside the LSI 1, which is a feature of the present invention. It has been intervened. This noise canceler 5 has an inductance of 5L.
, a resistor 5R, and in this embodiment, the noise canceller 5 is configured with a resistor 5R as shown in FIG.
It is constructed by routing a power supply wiring 1IA10 (first metal layer) in the SI interior 1 so as to have a routing portion 11 shown by hatching.

This routing portion 11 is formed by extending and wiring the power supply wiring inside the LSI 1 until it has inductance and resistance components that are independent of the width and length necessary for electrical connection (details will be described later). It is formed in the same layer as the power supply wiring 1o.

With this configuration, the output terminal 6°7 is set to Hi.
When changing from gh to Low level, external load capacity jt
The charges stored in each of 6cy7c become a steep current and flow into the power supply wiring 8a inside the chip 1. Here, in this embodiment, the noise canceller 5 is interposed and the voltage is dropped in the noise canceler 5, so that the current change rate in the power supply wiring 8 becomes lower than before the noise canceler 5 is interposed. A noise voltage proportional to the rate of change of current, which is lower than before, is generated in the power supply wiring 8 by the inductance 4L and resistance 4R outside the LSI, and this noise voltage is transmitted through the output terminal 3 that outputs another low level. Since the noise is propagated to the external circuit 9, the noise in the external circuit 9 is significantly reduced compared to the conventional one.

FIG. 5 shows the state of the noise voltage at the output terminal 3, and as shown in the figure, the noise voltage is much smaller than that of the prior art shown in FIG. , it is shown that noise has been significantly reduced. Incidentally, the values of inductance and resistance inside and outside the LSI are as follows. 5L=11.84
nH, 5R=8.560, 4L=5.07nH, 4R=
0.082Ω.

In addition, compared to before the intervention of Noise Canceller 5, 0°4ns
Although a delay was observed, it does not have a major effect on operation, so it is not a problem.

According to the semiconductor device configured in this way, the following effects can be obtained.

That is, since the noise canceller (inductance component 5L and resistance component 5R) 5 is added to the LSI interior 1, the voltage drop inside the LSI 1 becomes large, and the voltage drop outside the LSI becomes relatively small. , noise voltage outside the LSI is reduced, making it possible to prevent malfunctions of the semiconductor device. Moreover, in the above configuration, the electrostatic withstand voltage and operation speed are not reduced.

Here, the values of the inductance component 5L and the resistance component 5R required for the routing portion 11 are determined to be values that reduce the voltage inside the LSI 1 to such an extent that noise in the external circuit 9 does not become a problem. Needless to say.

Note that if the values of the inductance 4L and resistance 4R outside the LSI are made relatively smaller, the external circuit 9
It is possible to further reduce the noise in .

FIGS. 3 and 4 show other embodiments of the power wiring arrangement, respectively.

The semiconductor devices of these embodiments differ from those of the previous embodiments in that the power supply wiring is routed in a layer other than the wiring layer in which the power supply wiring is formed. That is, in FIG. 3, the contact hole 13 is brought into contact with the power supply wiring 12 in the first metal layer, and the routing portion 14 of the power supply wiring 12 is formed in the second metal layer where other wiring is formed. In FIG. 4, a contact hole 13 is brought into contact with the power supply wiring 12 in the first metal layer, and a layer dedicated to routing where no other wiring is formed is provided.
is formed.

As in the previous embodiment, these routing portions 14 and 15 are formed by extending and wiring the power supply wiring inside the LSI 1 until it has inductance and resistance components that are independent of the width and length necessary for electrical connection. It is formed.

Even with this configuration, the noise canceller 5 can be formed in the same manner as in the previous embodiment, and the same effects as in the previous embodiment can be obtained, that is, LSI integration can be achieved without reducing the electrostatic withstand voltage and operation speed.
Of course, it is possible to reduce external noise and prevent malfunctions.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor.

For example, in the above embodiment, the noise canceller 5 is L
Although it is constructed by routing the power supply wiring inside the SI, it is also possible to simply add a coil inside the LSI.

Furthermore, this embodiment can also be applied to individual modules of a semiconductor device comprising a large number of modules, and a similar noise reduction effect can be expected even when applied to such a large-scale semiconductor device. Needless to say.

Note that the present invention improves speed, increases bus width (increases number of bits)
It is particularly effective when applied to semiconductor devices whose performance is improved by

[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.

That is, since an inductance component and a resistance component are added inside the LSI, the voltage drop inside the LSI becomes large, and the voltage drop outside the LSI becomes relatively small. As a result, it becomes possible to reduce the noise voltage outside the LSI without reducing the electrostatic withstand voltage and operation speed, and malfunctions can be prevented.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an embodiment of a semiconductor device according to the present invention. FIG. 2 is a diagram showing how the power wiring is routed in the same embodiment as above, FIGS. 3 and 4 are diagrams showing how other power supply wiring is routed in the semiconductor device according to the present invention, and FIG. A noise waveform diagram at the output terminal (Low level output bin) in Figure 1, Figure 6 is a circuit diagram of a semiconductor device according to the prior art, and Figure 7 is a diagram at the output terminal (Low level output pin) in Figure 6. It is a noise waveform diagram. 1... LSI inside, 5, 11, 14, 15...
Inductance component and resistance component. Figure 84 - Darkness (S)

Claims (1)

[Claims] 1. A semiconductor device characterized in that an inductance component and a resistance component are added inside an LSI to increase the voltage drop inside the LSI. 2. The semiconductor device according to claim 1, wherein the inductance component and the resistance component are constructed by routing power supply wiring inside the LSI. 3. The semiconductor device according to claim 2, wherein the power wiring is routed in a layer other than the wiring layer in which the power wiring is formed.