JPH02249392A - Clock generator - Google Patents

Abstract

PURPOSE:To stabilize a synchronizing signal and to attain high picture quality of a video signal by giving a line lock clock to a synchronizing signal generating circuit, a burst lock clock or a line lock clock to a signal processing circuit when a video signal is the standard signal and giving a line lock clock when the video signal is the nonstandard signal. CONSTITUTION:A detection means 6 detects a video signal and in the case of the standard signal only, a phase control means 7 apply phase synchronization of a line lock clock 3 to a burst lock clock 5. When the nonstandard signal is inputted to a signal processing circuit 10, the line lock clock 3 is given and when the standard signal is inputted, the burst lock clock 5 or the line lock clock 3 synchronized with the burst lock clock 5 is given. Moreover, when the nonstandard signal is inputted to a synchronizing signal generating circuit 9, the line lock clock 3 is given and when the standard signal is inputted, the line lock clock 3 synchronized with the burst lock clock 5 is given. Thus, high picture quality and the stable production of synchronizing signal are attained.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to digital television receivers and the like, and particularly relates to a clock generation device that generates clocks used in synchronization signal generation circuits and signal processing circuits. be.

[Conventional technology]

FIGS. 6(a) and 6(b) are block diagrams showing conventional clock generators, respectively.

In FIGS. 6(a) and (b), 1 is a video signal input terminal, 2 is a line lock clock generation circuit, 3 is a line lock clock, 4 is a burst lock clock generation circuit, and 5
is a burst lock clock, 9 is a synchronization signal generation circuit, 1
0 is a signal processing circuit, 11 is a synchronization signal output terminal, and 12 is a video signal output terminal.

First, the circuit shown in FIG. 6(a) will be explained.

The burst lock clock generation circuit 4 uses a crystal oscillator (not shown) to generate a stable burst lock clock 5 synchronized with the color burst signal included in the video signal inputted from the video signal input terminal 1. Here, the input video signal is a signal that complies with the standard television broadcasting system (hereinafter referred to as the standard signal), and the frequency (fsc) of the color burst signal and the frequency of the horizontal synchronization signal included in this standard signal. The relationship with (fu) is as follows.

Next, the synchronization signal generation circuit 9 inputs the burst lock clock 5 from the burst lock clock generation circuit 4, and
A synchronization signal is generated using the relationship in equation (1).

The signal processing circuit 10 also processes a video signal input from the video signal input terminal 1 and a burst lock clock generation circuit 4.
The burst lock clock 5 from the input terminal is input, and signal processing is performed on the video signal using the relationship of equation (1) to improve the image quality of the video signal. Incidentally, as an example of a conventional circuit for improving the image quality of such a video signal, for example,
1-15635 is mentioned.

Next, the circuit shown in FIG. 6(b) will be explained.

A line lock clock generating circuit 2 generates a line lock clock 3 synchronized with a horizontal synchronizing signal included in a video signal inputted from a video signal input terminal 1.

Next, the synchronization signal generation circuit 9 receives the line lock clock 3 from the line lock clock generation circuit 2 and generates a synchronization signal.

Further, the signal processing circuit 10 receives a video signal input from the video signal input terminal 1 and a line lock clock 3 from the line lock clock generation circuit 2, and performs signal processing on the video signal.

An example of a circuit as shown in FIG. 6(b) is disclosed in Japanese Patent Application Laid-Open No. 193783/1983.

[Problem to be solved by the invention]

In the above conventional technology, first, in the circuit shown in FIG. 6(a), when the video signal input to the video signal input terminal l is a standard signal, a very stable synchronization signal can be generated, and the video signal High image quality can be achieved.

However, signals that do not strictly comply with the standard television broadcasting system (hereinafter abbreviated as non-standard signals), such as video signals reproduced from a VTR (video tape recorder), etc., that is, (1) Signals that do not maintain the relationship of the formula are not taken into consideration, so if such non-standard signals are input, not only will it be impossible to improve the image quality, but synchronization may not be possible. There was a problem.

On the other hand, in the circuit shown in Fig. 6(b), since the horizontal synchronization signal is used as the reference, it is possible to achieve sufficient synchronization even when a non-standard signal is input. It is possible to respond to signals.

Regarding improvement of image quality, when a non-standard signal is input, as mentioned above, the relationship of equation (1) is not maintained for non-standard signals, so it is possible to improve image quality as long as this relationship is not used. It is.

However, when a standard signal is input, the standard signal is (1)
Although the relationship in the equation is maintained, in the circuit of Fig. 6(b),
The Q value of the oscillator (not shown) included in the line lock clock generation circuit 2 is not as high as that of the crystal oscillator (not shown) included in the burst lock clock generation circuit 4 in the circuit of FIG. 6(a). The stability of the generated clock is also low, so
(1) When attempting to improve the image quality by utilizing the relationship in (2), the improvement effect was also low.

The purpose of the present invention is to solve the problems of the prior art described above,
For signal processing circuits, high image quality is achieved whether standard signals or non-standard signals are input.
It is possible to provide an optimal lock that can improve image quality, and for the synchronization signal generation circuit, it is possible to provide a standard lock that can synchronize even when any non-standard signal is input. It is an object of the present invention to provide a clock generation device capable of providing an optimum lock so that a very stable synchronization signal can be generated when a signal is input.

[Means for Solving the Problems] In order to achieve the above-mentioned object, the present invention provides a first clock generating means for generating a burst droplet clock synchronized with a color burst signal included in a video signal; a second clock generating means for generating a line lock clock synchronized with a horizontal synchronization signal included in the signal; ); and phase control means for phase-synchronizing the line lock clock with the burst lock clock when the video signal is detected as a standard signal as a result of the detection by the detection means; The synchronizing signal generating circuit is provided with the line lock clock, and the signal processing circuit is provided with the line lock clock when the video signal is detected as a standard signal as a result of detection by the detecting means. A burst lock clock or a line lock clock is provided, and when a non-standard signal is detected, the line lock clock is provided.

[Effect]

In the present invention, the detection means detects whether the video signal is a standard signal or a non-standard signal, and only when the video signal is detected to be a standard signal, the phase control means detects whether the video signal is a standard signal or a non-standard signal. The line lock clock is synchronized in phase with the burst lock clock.

The signal processing circuit receives a line lock clock when a non-standard signal is input, and a burst lock clock or a line lock clock synchronized with the burst lock clock when a standard signal is input. , respectively, so that the signal processing circuit can achieve high image quality, that is, improve image quality, regardless of whether a standard signal is input or a non-standard signal is input.

In addition, for the synchronization signal generation circuit, when a non-standard signal is input, a line lock clock with a wide pull-in range is used, and when a standard signal is input, a line lock clock synchronized with the burst lock clock is used. Since a lock clock is provided for each, the synchronization signal generation circuit can synchronize even if any non-standard signals are input from various devices with different pull-in ranges.
Furthermore, when a standard signal is input, a very stable synchronization signal can be generated.

(Example) A first embodiment of the present invention will be described below with reference to FIG.

In FIG. 1, 1 is a video signal input terminal, 2 is a line lock clock generation circuit, 3 is a line lock clock, and 4 is a line lock clock generation circuit.
1 is a burst lock clock generation circuit, 5 is a burst lock clock, 6 is a standard/non-standard signal detection circuit, 7 is a phase comparator, 8a and 8b are switches, 9 is a synchronization signal generation circuit, 10 is a signal processing circuit, 11 1 is a synchronization signal output terminal, 12 is a video signal output terminal, 1 is a synchronous separation/phase comparison circuit, 19 is a voltage controlled oscillator, and 20 is an adder.

Now, the operation of this embodiment will be explained.

A video signal input from the video signal input terminal 1 is input to a line clock generation circuit 2, a burst lock clock generation circuit 4, and a standard/non-standard signal detection circuit 6.

The line lock clock generation circuit 2 separates the horizontal synchronization signal included in the video signal, and connects the line lock clock 3 with a frequency 1820 times the frequency fH of the horizontal synchronization signal to the synchronization separation/phase comparison circuit 1B, Adder 20. It is generated by a phase locked loop (PLL) circuit composed of a voltage controlled oscillator 19.

Furthermore, the burst lock clock generation circuit 4 extracts the color burst signal included in the video signal and generates a burst lock clock 5 having a frequency eight times the frequency fsc using a crystal oscillator (not shown). It is occurring. In this way, the burst lock clock 5 is generated by the crystal oscillator, so it is very stable and locked.

Next, the synchronization signal generation circuit 9 always manually generates the line lock clock 3, divides the frequency of this clock 3, obtains a synchronization signal synchronized with the horizontal synchronization signal of the input video signal, and outputs the synchronization signal. It is output from terminal 11.

In addition, the standard/non-standard signal detection circuit 6 detects whether or not there is a relationship according to the above-mentioned equation (1) between the frequency fH of the horizontal synchronizing signal of the input video signal and the frequency fsc of the color burst signal. If it is detected that there is a relationship, it is determined that the input video signal is a standard signal, and if it is detected that there is no relationship, it is determined that it is a standard signal, and the determination result is detected. Output as a signal. A known example of such a standard/non-standard signal detection circuit is, for example, Japanese Patent Laid-Open No. 184082/1982.

Next, the switch 8a inputs the detection signal from the standard/non-standard signal detection circuit 6, and when the manually input video signal is a non-standard signal, it is sent to the line lock Crotter side, and when it is a standard signal, it is sent to the line lock Crotsuter side. It closes to the lock clock side and outputs each clock to the signal processing circuit 10. The signal processing circuit 10 receives a video signal from the video signal input terminal 1 and performs digital signal processing using the clock supplied from the switch 8a, thereby achieving high image quality.

Then, the processed video signal is sent to the video signal output terminal 1.
Output from 2.

Next, the operation of clock phase control will be explained.

The phase comparator 7 inputs the line lock clock 3 and the burst lock clock 5, compares their phases, and outputs a signal corresponding to the phase difference to the switch 8b.

The switch 8b, like the switch 8a, is controlled by a detection signal from a standard/non-standard signal detection circuit, and closes when the manually input video signal is a standard signal.
Open the switch when it is a non-standard signal. Therefore, the switch 8a inputs the output signal of the phase comparator 7 to the line lock clock generation circuit 2 only when it is a standard signal.

When the line lock clock generation circuit 2 receives the output signal from the phase comparator 7, it operates to match the phase of the output line lock clock 3 with the phase of the burst lock clock 5 based on the signal. do.

Here, the operation of the line lock clock generation circuit 2 will be explained in more detail.

The synchronization separation/phase comparison circuit 18 separates the horizontal synchronization signal included in the video signal input from the video signal input terminal l, and combines the separated horizontal synchronization signal with the line lock clock 3 output from the voltage controlled oscillator 19. The phases are compared, and a voltage corresponding to the phase difference is manually supplied to the voltage controlled oscillator 19 via an adder 20 as a control voltage. The voltage controlled oscillator 19 oscillates at a frequency according to the input control voltage, and outputs the oscillation output as the line lock clock 3. Therefore, when the output signal from the phase comparator 7 is not input, that is, when clock phase control is not performed, the line lock clock 3 becomes a clock synchronized with the horizontal synchronization signal.

On the other hand, when the output signal from the phase comparator 7 is input, that is, when clock phase control is performed, the control voltage output from the synchronous separation/phase comparison circuit 18 is inputted as a signal by the phase comparator 7. Comparison voltages corresponding to the phase difference between the input burst lock clock 5 and line lock clock 3 are added in the adder 20 and input to the voltage controlled oscillator 19, and as a result, the line lock clock 3 becomes the burst clock 3. The clock is in phase with clock 5.

Next, a second embodiment of the present invention will be described with reference to FIG.

In FIG. 2, the same components as in FIG. 1 are given the same reference numerals.

The configuration of this embodiment differs from the embodiment shown in FIG. The input point and
The switch 8b is removed and the output signal of the phase comparator 7 is directly input to the adder 20 of the line lock clock generation circuit 2.

Therefore, when the video signal input to the video signal input terminal 1 is a standard signal, the phases of the burst lock clock 5 and the line lock clock 3 are compared in the phase comparator 7, and the phase of the line lock clock 3 is changed to It is controlled to be synchronized with the phase of the ivy clock 5. on the other hand,
When the signal is a non-standard signal, the clock is switched by the switch 8a and both inputs of the phase comparator 7 become the line lock clock 3. Therefore, there is no phase difference (the clock is switched to the adder 20 of the line lock clock generation circuit 2). No signal is output.Therefore, the phase of the line lock clock 3 is controlled to be synchronized with the phase of the burst rotor clock 5 only when the signal is a standard signal.

Next, a third embodiment of the present invention will be described with reference to FIG.

In FIG. 3, the same components as in FIG. 1 are given the same reference numerals. Additionally, 2° is a line lock clock generation circuit consisting of a synchronous separation/phase comparison circuit 18 and a voltage controlled oscillator 19, and 17 is a variable delay circuit.

The configuration of this embodiment differs from the embodiment shown in FIG.
The two points are that a line lock clock generating circuit 2' with zeros deleted is used, and a variable delay circuit 17 is provided, and the output of the switch 8b is inputted to the variable delay circuit 17.

In this embodiment, the line lock clock generation circuit 2"
is a line lock clock synchronized with the horizontal synchronization signal included in the video signal input from the video signal input terminal l,
It is generated by a PLL circuit composed of a synchronous separation/phase comparison circuit 18 and a voltage controlled oscillator 19.

Similarly to the embodiment shown in FIG. 1, the switch 8b closes the switch when the video signal input from the video signal input terminal 1 is a standard signal, and transfers the signal output from the phase comparator 7 to the variable delay circuit. 17, and when the signal is a non-standard signal, the switch is opened and no signal is input to the variable delay circuit 17.

On the other hand 1. When a voltage is input as a signal from the switch 8b, the variable delay circuit 17 delays the line lock clock manually input from the line lock clock generation circuit 2' by a delay amount corresponding to the voltage, and outputs the line lock clock from the line lock clock generation circuit 2'.
When no voltage is input from the input line lock clock, the input line lock clock is output as is without delay.

That is, in this embodiment, when the input video signal is a standard signal, the frequency of the line lock clock output from the line lock clock generation circuit 2' and the frequency output from the burst lock clock generation circuit 4 are determined. Noting that the frequencies of the burst lock clock 5 are equal, if the standard signal The line lock clock from the line lock clock generation circuit 2 is delayed by the variable delay circuit 17 using a voltage corresponding to the phase difference between
Only the phase thereof is adjusted to synchronize the phases of the line lock clock and the burst lock clock 5.

Next, a fourth embodiment of the present invention will be described with reference to FIG.

In FIG. 4, the same components as in FIG. 1 are given the same reference numerals. In addition, 2' is a synchronous separation/phase comparison circuit 18, a voltage controlled oscillator 19, and a capacitor 21.
This is a line lock clock generation circuit consisting of:

The configuration of this embodiment differs from the embodiment shown in FIG. 1 in that a line-lock clock generation circuit 2' is used instead of the line-lock clock generation circuit 2, and the output of the switch 8b is manually input to the capacitor 21. Remove phase comparator 7 and generate burst lock clock /l! :The burst lock clock 5 from the circuit 4 is directly input to the switch 8b.

First, when the video signal input from the video signal input terminal 1 is a standard signal, the switch 8b closes the switch as in the embodiment shown in FIG. Clock 5 is input to voltage controlled oscillator 19 via capacitor 21, and when it is a non-standard signal, the switch is opened and no signal is output.

Next, in the line lock clock generation circuit 2'', the synchronization separation/phase comparison circuit 1 separates the horizontal synchronization signal included in the video signal input manually from the video signal input terminal 1,
The phase of the separated horizontal synchronization signal and the line lock clock 3 outputted from the voltage controlled oscillator 19 is compared, and the voltage according to the phase difference is used as the control voltage to generate the voltage controlled oscillator 19.
is being input. The voltage controlled oscillation a19 oscillates at a frequency according to the input control voltage, and outputs the oscillation output as the line lock clock 3. Therefore, when the burst lock clock 5 from the burst lock clock generation circuit 4 is not inputted from the switch 8b via the capacitor 21, the line lock clock 3 becomes a clock synchronized with the horizontal synchronization signal.

On the other hand, when the burst lock clock 5 from the burst lock clock generating circuit 4 is input through the capacitor 21, the burst lock clock 5 is superimposed on the control voltage output from the synchronous separation/phase comparison circuit 18. Thereby, the line lock clock 3 which is the output of the voltage controlled oscillator 19 is synchronized with the burst lock clock 5. Regarding this kind of circuit operation, please refer to Masamichi Shimura's ``
Please refer to "Nonlinear Circuit Theory" (Electronic Circuits Course 3), pages 69-74.

Finally, a fifth embodiment of the present invention will be explained with reference to FIG.

In FIG. 5, the same components as in FIG. 1 are given the same reference numerals. Additionally, 8c is a switch.

The difference in the operation of this embodiment from the embodiment shown in FIG. It is in.

Now, its operation will be explained.

First, when the video signal input to the video signal input terminal 1 is a non-standard signal, the switch 8c is opened and the burst lock clock 5 from the burst lock clock generation circuit 4 is not input to the phase comparator 7, and the clock phase There is no control.

However, when the signal is a standard signal, the switch 8c is closed.
Burst lock clock 5 from burst lock clock generation circuit 4 is input to phase comparator 7 via switch 8c. Therefore, the phase comparator 7 compares the phases of the burst lottery clock 5 and the line lock clock 3 from the line lock clock generation circuit 2, and inputs a signal corresponding to the phase difference to the line lock clock generation circuit 2. . The line lock clock generation circuit 2 includes a phase comparator 7
It operates to match the phase of the output line lock clock 3 with the phase of the burst lock clock 5 based on the output signal of the line lock clock 3 .

As explained above, in each embodiment, when the video signal input from the video signal input terminal 1 is a non-standard signal, the line lock clock 3 has a wide synchronization pull-in range and has good followability against jitter, etc. is applied to the synchronization signal generation circuit 9 and the signal processing circuit 10, and when the signal is a standard signal, the line lock clock 3 is applied to the burst rotor clock 5.
is synchronized with the synchronization signal generation circuit 9 to make it highly stable, and
In addition, the signal processing circuit 10 includes a burst rotary clock 5.
(In the fifth embodiment, line lock clock 3) is provided.

Therefore, the synchronization signal generation circuit 9 can synchronize even when any non-standard signal is input manually, and also generates a very stable synchronization signal when a standard signal is input. be able to.

Furthermore, the signal processing circuit 10 can achieve high image quality even when a standard signal is input or when a non-standard signal is input.

Furthermore, as described above, when a standard signal is input, different clocks are given to the synchronization signal generation circuit 9 and the signal processing circuit 0, except in the fifth embodiment. The clocks are synchronized, so there are no problems such as beat interference or screen shaking.

[Effects of the Invention] In the present invention, a line lock clock (a clock generated in synchronization with a horizontal synchronizing signal included in an input video signal) is used as a burst clock (a clock generated in synchronization with a color burst signal included in the video signal). clocks generated synchronously)
In addition, synchronization is performed only when the video signal is a standard signal.

Then, for the signal processing circuit, if a non-standard signal is input manually, a line lock clock is input, and if a standard signal is input, a burst lock clock or a line lock clock synchronized with the burst lock clock is input. are given respectively, so in the signal processing circuit,
Regardless of whether a standard signal is input or a non-standard signal is input, high image quality, that is, image quality can be improved.

In addition, the synchronization signal generation circuit is provided with a line lock clock when a non-standard signal is input, and a line lock clock synchronized with the burst lottery clock when a standard signal is input. Therefore, the synchronization signal generation circuit can synchronize no matter what kind of non-standard signal is input, and when a standard signal is input, it can generate a very stable synchronization signal. It can be performed.

Also, when a standard signal is input, different clocks may be applied, such as a burst clock to the signal processing circuit and a line lock clock to the synchronization signal generation circuit. Since both clocks are synchronized when input, problems such as beat interference and screen shaking do not occur.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention;
FIG. 3 is a block diagram showing a second embodiment of the invention, FIG. 3 is a block diagram showing a third embodiment of the invention, FIG. 4 is a block diagram showing a fourth embodiment of the invention, and FIG. FIG. 5 is a block diagram showing the fifth embodiment of the present invention, and FIGS. 6(a) and (b)
are block diagrams showing conventional clock generators, respectively.
It is. Description of symbols 1...Video signal input terminal, 2...Line rotary clock generation circuit, 3...Line lock clock, 4...
・Burst lock clock generation circuit, 5... Burst lock clock, 6... Standard/non-standard signal detection circuit,
7... Phase comparator, 8a, 8b, 8c... Switch, 9... Synchronization signal generation circuit, 10... Signal processing circuit, 17... Variable delay circuit, 18... Synchronization separation Phase comparator circuit, 19... Voltage controlled oscillator, 20... Adder Agent Patent attorney Akio Namiki Figure 2: X4 Figure 5

Claims (1)

[Claims] 1. A first clock generating means for generating a first clock synchronized with a color burst signal included in a video signal;
a second clock generation means for generating a second clock synchronized with a horizontal synchronization signal included in the video signal; a detection means for detecting whether the video signal conforms to a predetermined standard; a phase control means for synchronizing the phase of the second clock with the first clock when the video signal is detected to be a signal conforming to the standard as a result of detection by the detection means; selecting means for inputting a second clock and selecting and outputting one of the first and second clocks according to the result of detection by the detecting means; The second clock is input to a synchronization signal generation means, and the synchronization signal generation means generates a synchronization signal based on the second clock, and the clock output from the selection means is input to the signal processing means, A clock generation device characterized in that the signal processing means performs signal processing on the video signal based on the clock. 2. first clock generation means for generating a first clock synchronized with a color burst signal included in the video signal;
a second clock generation means for generating a second clock synchronized with a horizontal synchronization signal included in the video signal; a detection means for detecting whether the video signal conforms to a predetermined standard; a phase control means for synchronizing the phase of the second clock with the first clock when the video signal is detected to be a signal conforming to the standard as a result of detection by the detection means; The second clock is input to a synchronous signal generating means, the synchronous signal generating means generates a synchronous signal based on the second clock, and the second clock is input to a signal processing means. A clock generation device characterized in that the signal processing means performs signal processing on the video signal based on the second clock. 3. The clock generation device according to claim 1 or 2, wherein the phase control means determines whether or not to synchronize the phase of the second clock with the first clock depending on the result of detection by the detection means. A clock generation device characterized by having a switching means for switching. 4. The clock generating device according to claim 1, 2 or 3, wherein the second clock generating means oscillates in synchronization with a horizontal synchronizing signal included in the video signal, and outputs the second clock as an oscillation output. oscillation means for outputting a clock; the phase control means converts the second clock into the first clock;
1. A clock generation device, wherein the second clock is phase-synchronized with the first clock by directly controlling the oscillation means. 5. The clock generation device according to claim 1, 2 or 3, wherein the phase control means outputs an output from the second clock generation means when phase synchronizing the second clock with the first clock. A clock generation device characterized in that the second clock is phase-synchronized with the first clock by controlling the phase of the second clock.