JPH02246514A - Timing signal generator - Google Patents

Abstract

PURPOSE:To expand the delay setting range of timing pulses up to two cycles by putting two delay counters in two-cycle operation alternately. CONSTITUTION:The timing signal generator is provided with a cycle counter 2 which counts a variable reference clock 101 and generates a cycle pulse 102 from a counting end output and the two delay counters 5a and 5b independently. Then a multiplexer 3 puts the two delay counters 5a and 5b in the two-cycle operation alternately. Namely, the two delay counters 5a and 5b can count up to two cycles in a one-cycle shift state. Consequently, the delay time setting range of the timing pulses is expanded up to two cycles.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present inventor is concerned with line devices such as LSI, and has recently developed a prototype LSI that has high speed, high topology, and a wide delay setting range.
．． #c1il: This invention relates to a timing signal generator with an extremely effective timing signal.

[Conventional technology]

Conventional timing signal generators with high speed and ellipticity are
Seeding Opinion, 1-International Seminar Test Conference (September 1987) Volume 7
Straw 84 negative from page 6 (proc, I IEE E I
ntl I"gst Carbj',,pp,76-8
4 rept, 1987). Hereinafter, a conventional example will be explained using Figures 4 and 5. The conventional timing generator is a period counter that measures the reference clock 101 of the edible reference clock 11 period Tck, whose cycle can be varied by the setting signal 11, the number of times determined by the period setting signal 12, and outputs a counting output 20. 2.1f
A comparator 1 that compares the ta output 20 and the delay setting signal 15 and generates a timing pulse 106 when both have been used for a while.
Consists of 0. Figure 5 is an example in which the timing pulse 1060 cycle is set to 6Wt of the reference clock cycle by the circumference Al3a foot signal 12, and the °C delay time is set by the iA arc setting [15]. Counter 2 repeats the operation of counting the reference clock six times. If N is the data of delay setting range 15, then timing pulse 1 when N=Q
06 is like the fifth solid line.If N=5, a delay time of Tck*N can be generated as shown in the figure.

In the conventional system of Su4Gang, since the Taifu clock period Tck can be arbitrarily set using the setting signal 11, the variable reference clock generator is equipped with a variable reference clock generator based on the highly stable Kyojun Kabutosha of Suishokenkiji. If we use Iser et al. There is a judgment that the i6 discrete timing pulse 106 is superior at any period. .

[Problem to be solved by the invention]

In most timing devices used in LSI testing, it is desired to expand the timing pulse delay setting range in order to improve testability. But if the conventional
T technique is Wt number ratio output 20 delay setting of period counter 2
Compared to the No. 1 No. 15, the timing pulse is output when one kuk is reached, so the delay setting range is Q~(
18th period-Tck).

An object of the present invention is to increase the timing pulse delay setting range to 2.
It lies in expanding to the cycle. Furthermore, the present invention provides an automatic calibration mechanism for blacking, which eliminates the effects of alignment delays that occur along with this.

[Means to solve the problem]

Among the above purposes, in order to expand the set delay time of the timing pulse to two cycles, a cycle counter and a delay counter that determine the cycle are provided independently, and the two -M counters and the multiplexer are connected to the two counters. The two cycles are operated alternately.

Furthermore, in order to eliminate the influence of wiring delays, a variable delay circuit for calibration, a fixed delay circuit that delays the Hamaha clock that drives the delay counter, and a periodic pulse are installed in the signal transmission path inside the timing signal generator. An automatic calibration controller is provided, which is capable of measuring the delay time Td of the timing pulse when used as a reference, and which controls a variable delay circuit for calibration based on the measurement result.

[Effect]

The period counter counts the possible quasi-clocks and generates the MJ period pulse. The periodic pulse is distributed by a multiplexer to two delay counters for each period, and the delay counters start counting the reference clock based on the applied periodic pulse. At least two delay counters can count up to two periods with a one-period shift. Therefore, the delay time setting range of the timing pulse is expanded to two periods.

#I'kl difference measuring device measures the time %Td- of the rising edge of the periodic pulse and the timing pulse, and measures e! The change in the time difference Tct when the rack period is changed is transmitted to the automatic calibration control section. Variable for retention)! ! Local government circuit MJ
Controls the delay time until the M pulse is stamped into the fi counter. The automatic calibration control unit adjusts the amount of time between the variable delay clock and the periodic pulse to exceed the value measured by the time difference measuring device, so the wiring of the variable reference clock is corrected. The effects of delay can be removed.

〔Example〕

Hereinafter, an example of a drawing of the present invention will be explained using Figure 1, Figure 2, Figure 2, and Figure 3. Figure i@1 is a timing generator equipped with an automatic calibration mechanism according to the present invention, and Figure 2 is its operation molding.

The timing gK generator according to the invention has a setting signal 11
A variable reference clock oscillator 1 whose oscillation period Tck can be varied rapidly, a period counter 2 which counts the output of the variable reference clock 101 and generates a periodic pulse 102 from the counting end output, and a MiJ91 pulse 102 every period. Distributing demultiplexer 5, distributed periodic pulse 10
4 delay circuits (and 4b) that delay 5α (and IQSb), and a delay counter 5α (and 5b) that starts the rt cycle by the blocked periodic pulse 104α (and 1aaA)! ! ! m counter counting output 10
An OR gate 6 which takes the tSS sum of 5α and 105b, a time interno that measures the time difference 102 between the timing pulse 106 and the periodic pulse (based on the measurement results 108 of the clock counter 8 and the time interval counter 8, variable delay circuits 4α and 4btl) It is comprised of an automatic calibration control section 9 for controlling. 7 represents wiring delay.

Next, the operation will be explained using Figure A2. The period counter 2 calculates the number of ridges given by the period setting signal 12 from the Kaga standard α-tuk 101, and calculates the period signal 10 from the counting end output.
Generates 2. In the example in Figure 2, period = (possibly based on α
TsukuX6). The periodic pulse 102 generates a periodic pulse 105α in one round J9145 by the demultiplexer 5.
and variable delay circuits 4α and 44 distributed to 105b.
Y is retrospectively applied to delay counters 5α and 5b. When the period gI numbers 104α and 104b are applied, the delay counters 5G and 5b start counting the α clocks 107 according to the variable reference, and the delay counters 5G and 5b start counting the α clocks 107 based on the variable reference, and set the delay setting g! By No. 1 15α and 15b”
1: When only the value N to be collected is counted, the ti number ratio output is 10
5z and 105b are output. The fmm phase summation timing pulse 106 for both of these pulses is output.

wI2 figure 105a, 105b and 106, 'iliEm's molding work, slow tat feet number 15α and 15b are 'S sweet' with N=0 set, and the dotted line is the enemy shadow when N=11 is set. It is. According to the present invention, for the stock when N=11, (2 periods - Tck)
Delayed revisions are possible at the village. and a quick clock cycle'
Since the fck can be set quickly using the setting signal 11, the variable reference clock generator can be used with a synthesizer based on a crystal-based single-shot clock generator, etc., using a high-precision timing pulse 106 or an arbitrary clock. The advantage of being superior to the cycle is the same as the conventional method.

By the way, in order to actually implement the timing generator shown in Figure 1, it is necessary to input the delay counter 5α from the clock input of the 8M counter 2.
, 5b until the counting start input, tα, tb, and the variable reference α-k distribution delay time t from the period counter 2 to the delay counters 5α, 5b. The distortion of the standard clock period Tck is calculated as [7ck174 &n
Is it necessary to adjust it within this range? At the ceremony, Korowacho and O(to
-ta (tckmin or 0 (to -tb
(It becomes tckmil.

This is a period counter)! ! Depending on the timing of the ground, manufacturing variations in the melting delay time, etc., the relationship between the periodic pulse in the delay counter and the variable reference α, one period, or
This is because, if the deviation is more than that, and the α-k cycle is varied from the reference, the delay time of the timing pulse, which should not be changed in the first place, will change.

Therefore, a method of automatically calibrating the upper delay time according to the present invention will now be explained using Fig. 5.

The valley shape in FIG. 5 shows the shaping of the valley based on the rising edge of the periodic pulse 102. The shaping when the reference clock period is the minimum value of Tck 4 is shown by a solid line, and the shaping when TtJ is increased is shown by a solid line. The enemy shadow is shown by a dotted line. In order to simplify the explanation below, the path (102 to 102) of the delay counter 5a is
103α to 104α to 105α) will be described. Further, it is assumed that the delay setting g1 consideration 15α gives N;0. The variable reference α check 101 becomes the variable reference α check 107 delayed by the wiring delay 7 and is applied to the delay counter.

First, when fckmLn(to-ta), when the variable reference clock 7# period is increased from 7ck 4, the rising edge of the output timing pulse 106 changes to the direction where the delay time becomes smaller as shown by the dotted line. Then 0<t
When o-1α<Tckm&ru, the rising edge of the timing pulse 106 does not change in time even if the variable reference clock period Tck is changed. In other words, the purpose is to calibrate it to this state. Then, when to-ta (0, the variable reference clock period Tc is changed from min to Tc), the rising edge of the output timing pulse 106 changes in the direction of increasing S extension time as shown by the dotted line. The time interval counter 8 calculates the delay time Td of the periodic pulse 102 and the timing pulse 106.
, and change the variable reference clock period from 7Ckmtn to f! #17XJ shi, -j! A local time open time 1'cL is small (when it becomes tckrni
It is determined that rL(to -ta), and i of the variable delay block circuit 1NI4α is determined by the calibration signal 109 of the sea bream calibration control
! The point at which the delay time TcL does not change even if the A time period tα is changed and the α time period is changed based on the variable standard (0 to
-1α<Tckmin), the automatic calibration ends. Conversely, the variable reference clock period 'IkTckr
When the delay time Td increases from nil b.
i! By reducing the delay time ta of the A delay circuit 4α, automatic calibration can be performed by a colleague. Also, before self-calibration, 2Tc
km&le (to -ta) If to and ta are included in the stock and are far apart, the width of change in the delay time of the timing pulse will be 2WI with respect to the width of change in the variable reference clock period. From the relationship between the variation width of the clock cycle and the variation width of the delay time of the timing pulse, the variable M ground circuit 4
It is also possible to roughly estimate the delay time that should change by one in α.

According to the present invention, the timing g! By measuring the influence of the wiring delay time inside the i generator, automatic performance correction can be realized using the variable delay circuit formed in the V'3 section.

[Young fruit of invention]

According to the invention, since the two delay counters can each operate for two cycles, the delay setting range of the timing pulse can be reduced to two.
It is possible to expand the period.

In addition, the self-calibrating pickling barrel allows the use of a variable reference clock even in a configuration in which a period counter and a delay counter for two seedlings are provided independently, so period pulses and timing pulses can be produced and controlled at high speed.

Therefore, with the above configuration, it is possible to achieve both high accuracy of periodic pulses and timing pulses and expansion of the delay setting range of timing pulses.

[Brief explanation of drawings]

Figure 1 is a configuration diagram of a timing signal generator equipped with an automatic adjustment mechanism that is an example of the present invention, Figure 2 is a diagram of the operation of Figure 1, and Figure 5 is a diagram of the timing signal generator in accordance with the present invention. Myself! An explanatory diagram of the iI calibration mechanism, Figure 4 is a configuration diagram of a conventional example, and Figure 5 is a slant-shaped diagram showing motion forming of a conventional example. 1... Variable reference clock generator 2... Period counter 5... Demultiplexer 4α (and ah)... Variable delay circuit 5α (S and sb)... Delay counter 6... OR gate
7... Melting resistance delay 8... Time interval counter 9... Own wJ role positive control s10... Comparator +02 3rd haze

Claims (1)

[Claims] 1. M units of counters that generate periodic pulses and M delay counters that determine delay time are provided, a multiplexer that operates the delay counters for M cycles, and the outputs of the delay counters that have operated for M cycles are synthesized. 1. A timing signal generator comprising an OR gate, characterized in that the period of a reference clock can be arbitrarily set. 2. In the timing signal generator according to claim 1, a variable delay circuit for calibration is inserted in the transfer path of the periodic pulse, and a time difference measuring device is provided to measure the time difference between the periodic pulse and the timing pulse, and this time amount and the reference clock are A timing signal generator equipped with an automatic calibration mechanism, which focuses on the relationship between cycles and controls a variable delay circuit to eliminate the influence of wiring delays within the timing signal generator, thereby enabling automatic calibration. vessel.