JPH02244491A - Semiconductor device and semiconductor storage device - Google Patents

Abstract

PURPOSE:To reduce the parasitic capacity of a common collector line and to execute the operation at a high speed by providing a multi-emitter transistor on a sense amplifier, and providing plural common collector lines against data of 1 bit. CONSTITUTION:That which contains pre-sense amplifier blocks B3, B4 and B6, a cascode amplifier block B10 and a current switch block B11 works as a sense amplifier. As for the cascode amplifier, a multi-emitter bipolar transistor Q20 and Q21 having two emitters are provided in the cascode amplifier block B10. Accordingly, a common collector line being a common data line connected the cascode amplifier block B10 can be divided into a pair of CC1 and CC2 and a pair of CC3 and CC4. In such a way, the parasitic capacity of the common collector line can be reduced, and the operation can be executed at a high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device suitable for high-speed operation and a semiconductor memory device to which the same is applied.

[Conventional technology]

A conventional device is described, for example, in Japanese Patent Laid-Open No. 132416/1983. This is shown in Figure 2.

This figure shows part of the circuitry of the device, from the memory cells to the sense amplifiers.

In the following description, a bipolar transistor will be referred to as a transistor, and a MOSFET will be referred to as a MOS.

Symbols B1 and B2 each indicate an example of a data line block in the memory cell array. A memory cell to be accessed can be selected from a plurality of memory cell arrays arranged in a matrix in the X and Y directions by inputting signals to the signal line X1, signal lines Yl, Y2, etc. .

Symbols DLI to DL4 are data lines, and symbol CELL l.

CELL2 is a memory cell with latch function, code M5
．． M6. M7. M8 is a transfer MO3 that determines whether or not to transmit memory cell information to the data line; reference numeral M9~
M12 sends data line information to common data lines CDI and CD2.
Transfer MO8 determines whether or not to transfer the information to the other party.

B3 is a pre-sense block that converts the differential voltage input signal from the common data line into a differential current signal. Code Ql
, Q2 are level shift transistors, symbols Di, D
2 is a diode, and symbol M13°M2S is a MOS.

This pre-sense block includes transistors Q 3 , Q4 and MOS Mll, Q3, which form a differential amplifier. An operation is performed in which the differential voltage entering the base of Q4 (7) becomes a current signal and is transmitted to the common collector lines CCI and CC2.

Normally, a plurality of pre-sense blocks B4 similar to B3 are connected to the same common collector line pair, and it is possible to select the signal from among them by the signals input to the terminals Sl, S2, etc. I can do it.

Block B5 converts current signals input from common collectors IccI and CC2 into voltage signals and converts them into terminals Ql and Q2.
This is a circuit that outputs to. Resistive elements R1, R2, transistor Q7. Q8, diode D3. MO3, M19~
M21 constitutes a cascode amplifier, and CCI, C
The differential current input from C2 is connected to Q7. It is output as a differential voltage between the collectors of Q8. Transistor, Q 10.
Qll.

Diode D4. D5. MO8, M22. M23 constitutes a level shift circuit, and the next stage resistive elements R3, R4,
Transistor Q12. Q13. The signal is converted to a signal level suitable for input to a differential amplifier consisting of MO8°M24. The circuit of FIG. 2 shows part of a memory cell array and sense amplifier in a semiconductor memory device.

[Problem to be solved by the invention]

The above conventional technology does not take into account speedup,
When trying to achieve even higher speeds, the following problems occurred.

Generally, in order to transmit electrical signals at high speed, the signal amplitude of the signal path is reduced, and the parasitic capacitance of this path is reduced.

It is important to reduce parasitic resistance. For example, the second
In the conventional circuit shown in the figure, if you try to increase the memory capacity, the capacitance and resistance of the common data line and common collector line described above will inevitably increase, so it is possible to simultaneously increase the capacity and speed of the storage device. It was difficult to do so.

An object of the present invention is to achieve speeding up of a semiconductor memory device.

Another object of the present invention is to provide a semiconductor device used in a semiconductor memory device that can achieve high speed.

[Means to solve the problem]

The features of the present invention that achieve the above object are as follows: memory cell array.

an address decoder that provides address information to the memory cell array; an input buffer that provides an address signal to the address decoder; and based on the address information from the address decoder,
In a semiconductor memory device comprising a sense amplifier that amplifies a memory cell signal and an output buffer into which the output of the sense amplifier is input, the sense amplifier has a multi-emitter transistor.

A feature of the semiconductor device of the present invention that achieves the above-mentioned other objects is that it includes a plurality of differential voltage-differential current converting means, and the output of one differential voltage-differential current converting means is connected to one set of data bus lines. The set of common data bus lines has one or more differential voltages -
A differential current converting means is connected, and a current for converting the differential current signal of the set of common data bus lines into a voltage signal is -
It has a voltage conversion means, and the current-voltage conversion means includes two
More than one set of the common data bus lines are connected.

[Effect]

Conventionally, the parasitic capacitance and parasitic resistance of common data bus lines, that is, common collector lines, have been large for the following reasons.

That is, among the terminals of planar transistors for integrated circuits, the collector terminal, which generally has the largest parasitic capacitance with the substrate, is shared, resulting in a large parasitic capacitance.

Therefore, in order to reduce this capacitance, it is necessary to reduce the number of pre-sense blocks connected to a set of common collector lines. However, in the conventional technology, there was only one common collector line per 1 bit of data, so it was necessary to increase the number of data multiplexes in other places, that is, increase the number of data lines that are actually connected to the common data line. However, these methods led to an increase in the delay time in the common data line, and in the end the delay time could not be shortened.

In the present invention, by providing a plurality of common collector lines for one bit of data, the parasitic capacitance of each common collector line can be reduced, and high speed operation can be achieved.

〔Example〕

Hereinafter, the present invention will be described in detail using the drawings.

FIG. 3 shows a schematic configuration of the entire semiconductor memory device.

Address signals entering the input buffer are decoded into address information for individual addresses through an address decoder, and these are input to the memory cell array and sense amplifier. Address in the row direction in the memory cell array (
Xi, X2) and the column direction address (Yl, Y2.Sl,
The information selected by B2) is amplified by the sense amplifier, input to the output buffer, and output from there to the outside.

Note that in FIG. 3, the write circuit and the like are omitted.

Next, FIG. 1 shows a portion of the memory cell array and sense amplifier in FIG. 3.

Data line block Bl in the memory cell array.

The output from B2 is a set of common data lines CDI.

Output to CD2. One set of common data lines is input to pre-sense amplifier block B3. Multiple pre-sense amplifier blocks, for example B3°B4, 86, etc.
It is connected to a pair of common collector lines CC1 and CC2, which are a set of common data lines. Further, a pair of common collector lines CC3 and CC4, which are another set of common data lines, are connected to a plurality of other pre-sense amplifier blocks, such as B7.
°B8, 89, etc. are connected.

These two sets of common data lines are connected to one cascode amplifier block BIO. The output of the cascode amplifier block BIO is the current switch block Bll.
is input.

Pre-sense amplifier block (e.g. B3.B4゜B6
) converts the differential voltage appearing on one set of common data lines CDl and CD2 to one set of common collector lines CC1 and C
It is a differential voltage-differential current conversion means that outputs a differential current to C2.

The cascode amplifier block BIO has one set of common collector lines CCI and CC2 (or CC3 and CC4)
This is a current-to-voltage conversion means that converts the differential current appearing in the voltage signal into a voltage signal.

The block including the pre-sense amplifier block, cascode amplifier block, and current switch block works as a sense amplifier.

In the embodiment shown in FIG. 1, the cascode amplifier is configured to include multi-emitter bipolar transistors Q20 and Q21 having two emitters in the cascode amplifier block.

As a result, two common collector lines (CC
I and CCD pair and CC3 and CC4 pair). This makes it possible to reduce the capacitance and resistance per set of common collector lines, which are one set of common data lines, compared to the case where the lines are not divided.

In this embodiment, the number of emitters is two, but it can also be three or more. This allows the common data line to be divided into three or more.

This embodiment will be compared with the conventional configuration shown in FIG.

Data line block Bl in the memory cell array.

This is the same as the case shown in FIG. 2 in that the data from B2 is made into a differential voltage signal between the common data lines CDI and CD2, and this is converted into a current by the pre-sense block B3. The difference from FIG. 2 is that the transistor Q7 of the cascode amplifier block BIO. The common collector line can be divided by changing M8 to a multi-emitter (bipolar) transistor Q20°Q21. C81-C8
5 is a constant current source, RIO is a resistor (which may be composed of a diode, etc.), and a multi-emitter transistor Q
20. This is a load element for keeping the base potential of Q21 constant. Block B10 is called a multi-emitter cascode amplifier. In this figure, multi-emitter transistor Q2
0. Q21 has two emitters, but by increasing the number of emitters, the number of input common collector line pairs can be increased.

A pre-sense block (e.g., B3.B4.B6) activated by a selection signal (e.g., SL) input to each pre-sense block among all common collector lines input to - multi-emitter cascode amplifiers.
．． B7. B8. B9) must be only one.

According to this embodiment, the parasitic capacitance and parasitic resistance of the common collector line can be reduced without increasing the number of elements, and the signal transmission speed can be increased.

FIG. 4 shows another embodiment of the invention, blocks 820--
B22 is a cascode amplifier such as a multi-emitter cascode amplifier, and one or more sets of its common collector lines are MOS M2O.

M31 is added. According to this configuration, the signal line BSO
By setting the cascode amplifier B20 to a "High" level, it is possible to lower the output of the cascode amplifier B20 to below the logic "Low" level. As a result, block B20. B21
．． The outputs of multiple cascode amplifiers such as B22, etc. are connected to transistors Q30-Q31, D30, etc. as shown in the figure. Wired-OR logic can be achieved with an emitter follower stage consisting of a diode D31 and constant current sources C830 and C831. In other words, if there are N cascode amplifiers, only one of the N signal lines from BSO to BSN connected to each should be set to "Low" level, and all other signal lines should be set to "High'" level. According to “L
It is possible to select only the output signal of the cascode amplifier at the "o w" level and transmit it to the next stage.

Q20. It is possible to provide the same function by lowering the collector of Q21 with MOS etc., but in that case, Q20
．． In some cases, the collector potential of Q21 drops below the base potential (this is said to enter saturation). Like block B20, multi-emitter transistor Q20. Q2
If the method is to lower the emitter potential of multi-emitter transistor Q20. There is an advantage that there is no need to worry about saturation of Q21.

Figure 5 specifically shows the effect of applying the embodiment. The horizontal axis of the graph represents the number of pre-sense blocks connected to a set of common collector lines, and the vertical axis represents the delay time of the sense amplifier section in that case. shows.

This is the result of a computer simulation assuming typical conditions.

As is clear from FIG. 5, the delay time increases as the number of pre-sense blocks attached to the common collector line increases. In this embodiment, for example, the conventional 16 pre-sense blocks connected to the common collector line can be reduced to 8.

Under the conditions shown in FIG. 5, a speed increase of approximately Q, 8 m5ec can be achieved.

Still another embodiment of the present invention will be described with reference to FIG. In the method of pulling down the common collector line like the cascode amplifier 820 in FIG. 4, the transistor Q3 of the pre-sense amplifier connected to the previous stage. The collector potential of Q4 will drop, and Q3. The saturation margin in Q4 will decrease slightly. Furthermore, since the common collector line, which has a relatively large capacity, is moved, the amplitude is small, so a recovery time is required, albeit slightly. Therefore, as shown in FIG. 6, a multi-emitter transistor Q22. Q23 has an emitter that is not connected to the common collector lines CC1 to CC4, and is used as a pull-down-only emitter. MOS M32°M33 is connected to it, and cascode amplifier selection or non-selection is performed using MOS M32. It is configured to be controlled by the gate potential BSO of M33.

According to this configuration, there is an advantage that the saturation of the transistor in the previous stage or the adverse effects caused by the common collector line recovery time are eliminated.

The symbols in the diagram starting with M are MOS transistors,
Items starting with Q are bipolar transistors, items starting with D are diodes, and items starting with R are load elements such as resistors.
Those starting with CD indicate common data lines, those starting with CC indicate common collector lines, and those starting with C8 indicate constant current sources.

The semiconductor device described above is usually used in a semiconductor memory device, but it can also be used in a microprocessor with a built-in memory device.

〔Effect of the invention〕

According to the present invention, it is possible to reduce the parasitic capacitance and parasitic resistance of the common bus line on which data multiplexing is performed, thereby shortening the signal transmission time and achieving the effect of increasing the speed of the semiconductor memory device.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a part of a sense amplifier and a memory cell array according to an embodiment of the present invention, FIG. 2 is a diagram showing a conventional circuit, and FIG. 3 is an overall configuration of a semiconductor memory device according to an embodiment of the present invention. FIG. 4 is a diagram showing a part of the memory cell array and sense amplifier of another embodiment of the present invention, and FIG. 5 is a diagram showing the number of pre-sense blocks connected to a set of common collector lines and the sense amplifier section. FIG. 3 is a diagram showing an example of the relationship between the delay time and the delay time. FIG. 6 is a diagram showing a part of a sense amplifier according to still another embodiment of the present invention. M5. M6. M9. Mlo, M13. M14. M2S・
...MOS transistor, Q20. Q21...Multi-emitter transistor, Di, D2. D3. D4゜D5
...Diode, R1, R2, RIO...Load element, CD 1 , CD 2 .:l Mon data line, C
C.I. CC2, CC3, CC4...Common collector wire, C8
I, C52, C53, C84, C55...constant current source.

Claims (1)

[Claims] 1. A memory cell array, an address decoder that provides address information to the memory cell array, an input buffer that provides an address signal to the address decoder, and based on the address information from the address decoder,
A semiconductor memory device comprising: a sense amplifier that amplifies a memory cell signal; and an output buffer into which the output of the sense amplifier is input, wherein the sense amplifier has a multi-emitter transistor. 2. a memory cell array, an address decoder that provides address information to the memory cell array, an input buffer that provides an address signal to the address decoder, and based on the address information from the address decoder,
In a semiconductor memory device comprising a sense amplifier that amplifies a memory cell signal and an output buffer into which the output of the sense amplifier is input, the sense amplifier divides a data bus from the memory cell array into two or more groups. A semiconductor memory device characterized by having a cascode amplifier. 3. It includes a plurality of differential voltage-differential current conversion means, the output of one differential voltage-differential current conversion means is connected to a set of common data bus lines, and the output of one differential voltage-differential current conversion means is connected to a set of common data bus lines. is connected to one or more differential voltage-to-differential current converting means, and has a current-to-voltage converting means for converting the differential current signal of the set of common data bus lines to a voltage signal, and the current- A semiconductor device characterized in that two or more sets of the above-mentioned common data bus lines are connected to the voltage conversion means. 4. The semiconductor device according to claim 3, wherein the differential voltage-differential current conversion means includes a bipolar transistor. 5. The semiconductor device according to claim 3, wherein a cascode amplifier is used as the current-voltage conversion means. 6. The semiconductor device according to claim 5, wherein a multi-emitter transistor is used as a bipolar transistor constituting the cascode amplifier. 7. The semiconductor device according to claim 3, wherein the current-voltage conversion means has a function of lowering the output level to "Low" by inputting a non-selection signal, and by wire-ORing these outputs through an emitter follower circuit. A semiconductor device characterized by multiplexing. 8. The semiconductor device according to claim 7, wherein a cascode amplifier is used as the current-voltage conversion means. 9. The semiconductor device according to claim 8, wherein a multi-emitter transistor is used as a bipolar transistor constituting the cascode amplifier. 10. A memory cell array, an address decoder that provides address information to the memory cell array, an input buffer that provides an address signal to the address decoder, and based on the address information from the address decoder,
A semiconductor memory device comprising a sense amplifier that amplifies a memory cell signal and an output buffer into which the output of the sense amplifier is input, wherein the sense amplifier has a plurality of cascode amplifiers. . 11. The semiconductor memory device according to claim 10, wherein each of the plurality of cascode amplifiers uses a multi-emitter transistor. 12. The semiconductor memory device according to claim 11, wherein the multi-emitter transistor has an emitter connected to a pull-down circuit. 13. A microprocessor comprising the semiconductor memory device according to claim 1 or the semiconductor device according to claim 3.