JPH0224439B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a telemeter system, and more particularly to a method for selectively calling terminal devices from a central device in a telemeter system.

[Prior art]

In a telemeter system, a central device (in-house device) selectively calls a large number of terminal devices (transmitters) that are distributed in remote locations, and each terminal device transmits data to the central device when called. . There are various calling methods for this terminal device, but a typical one is to synchronously count the counters provided in each terminal device under control from the central device side, and each terminal device has an internal counter value. There is a method in which data is transmitted when the value matches a value unique to the own device.

Conventionally, in such a terminal device paging method using synchronous counting, the clock pulse and reset pulse for synchronous counting control are modulated (for example, frequency modulated) and transmitted to each terminal device through a common line, or each pulse is Mainly, one of the methods of transmitting pulses through separate lines is adopted. However, in the former case, a modulation circuit and a demodulation circuit must be installed in the central device and the terminal device, respectively, and in a telemeter system that transmits data directly without modulating it, the central device and the terminal device become complicated. There's a problem. On the other hand, the latter method not only increases the number of lines between the central device and the terminal devices, but also has the problem of being prone to malfunctions due to pulse attenuation and noise contamination during transmission.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned problems, and it is possible to reliably call a terminal device from the central device through the minimum number of lines, and also to simplify the internal circuits of the central device and the terminal device involved in call control. The purpose is to provide a new terminal device paging method.

[Structure of the invention]

In the present invention, a control line common to all terminal devices is provided between the central device and the terminal devices, and means for opening and closing this control line is provided in the central device. In addition, within each terminal device, two charging/discharging circuits with different time constants are connected to the control line so as to discharge when the circuit is closed, and a charging voltage is always applied, and each of these charging/discharging circuits. The output voltage of the control line is input, the counter is reset when the control line is closed for a first period, and the counter is counted when the control line is closed for a second period that is different in length from the first period. A counter control circuit for counting up or counting down is provided. Then, after closing the control line for a first period on the central equipment side and resetting the counters of each terminal equipment, the second
By intermittently closing the control line for each period of time, and counting up or down the counter of each terminal device, the terminal devices are sequentially called up and sent data to the central device.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows the system configuration of a telemeter system according to the present invention. In the figure, 1 is a central device, from which four lines L ₁ to _{L 4} come out. 2 is a terminal device, and each line L ₁ to _{L 4}
It is connected to the central device 1 via.

The configuration of the central device 1 will be explained with reference to FIG.
In the figure, 3 and 4 are DC power supplies, which are connected in series with each other. The positive terminal of power supply 3 is connected to line L ₁ ,
The negative pole is permanently connected to the line _L2 . The line _L3 is connected to the positive pole of the power supply 3 or the negative pole of the power supply 4 by switches 5 and 6.
_L4 is always connected to the negative pole of the power supply 4 via the low resistor 7. 8 is a voltage reading circuit that reads the voltage across the low resistor 7 (received data), and 9 is a control circuit that controls the switches 5 and 6 and the voltage reading circuit 8.

FIG. 3 is a circuit diagram of the terminal device 2. The terminal device 2 has the same configuration except for how to select the output terminal of the counter, which will be described later.

In FIG. 3, 11 is a voltage stabilizing circuit, which includes Darlington-connected transistors Q ₁ ,
Q ₂ , a resistor R ₁ and a Zener diode ZD ₁ connected between the lines L ₁ and L ₂ . The connection point between Zener diode ZD ₁ and resistor R ₁ is transistor Q ₂
connected to the base of The voltage V ₁ of the power supply 3 in the central device 1 is applied between the lines L 1 and L ₂ , but the voltage between the lines L _{1 and} L ₂ at the connection position of each terminal device is applied to the lines L ₁ and L ₂ on the way. The amount of voltage drop varies depending on the line length and line current value from the terminal device to the central device.
For this reason, in this embodiment, the voltage between the lines L ₁ and L ₂ is input to the voltage stabilizing circuit 11 to obtain a constant DC voltage on the output side of the circuit.

12 and 13 are charging/discharging circuits, which have different time constants as described later. The charging/discharging circuit 12 is a capacitor
Consisting of C ₁ , resistors R ₂ , R ₃ , diodes D ₁ , D ₂ ,
The other charging/discharging circuit 13 includes a capacitor C ₂ , a resistor R ₄ ,
It consists of R ₅ , diodes D ₃ and D ₄ . The resistors R ₂ and R ₄ determine the charging time constant of the capacitors C ₁ and C ₂ respectively, and the output voltage of the voltage stabilizing circuit 11 is applied to the capacitors as a charging voltage via the resistors R ₂ and R ₄ . Applied to C ₁ and C ₂ . Resistors R ₃ and R ₅ together with capacitors C ₁ and C ₂ determine the discharge time constant, and capacitors C ₁ and C ₂ are connected to the line via resistors R ₃ and R ₅ and diodes D ₂ and D _4. Connected to L ₃ . Diodes D ₂ and D ₄ are provided to prevent reverse current, and diodes D ₁ and D ₃ are provided as capacitors.
This is provided to keep the voltage constant when C ₁ and C ₂ complete discharge.

A counter control circuit 14 is composed of two voltage detection circuits 15 and 16. These voltage detection circuits 15 and 16 detect whether the input voltage is above or below a predetermined threshold, and specifically, a well-known Schmitt trigger circuit or the like is used. The output voltage e ₁ of one charge/discharge circuit 12 is input to one voltage detection circuit 15 , and the output voltage e ₂ of the other charge/discharge circuit 13 is input to the other voltage detection circuit 16 .
The output voltages e ₃ and e ₄ of each voltage detection circuit 15 and 16 are as follows:
Counter 17 reset input R and clock input
CK respectively. Note that the power supply voltage for the counter 17 and the voltage detection circuits 15 and 16 is supplied from the voltage stabilization circuit 11.

Reference numeral 18 denotes a voltage stabilizing circuit, which includes Darlington-connected transistors Q ₃ , Q ₄ and Q ₅ , Q ₆ , a Zener diode ZD ₂ , resistors R ₆ , R ₇ , and a capacitor C ₃ . This voltage stabilizing circuit 18 operates only when the counter 17 counts up to a value (i) specific to the terminal device, and outputs a constant voltage between the output lines 19 and 20, which stabilizes the voltage between the lines L ₁ and L ₂ . Output to. That is, when the output corresponding to the value (i) of the counter 17 is at the "L" level, the transistor _Q4 is turned off, so the voltage stabilizing transistor _Q5 is in the off state, but the value (i) of the counter 17 is While the output corresponding to i) is at "H" level, transistor _Q4
turns on and closes the circuit between Zener diode ZD ₂ and line L ₂ , transistors Q ₅ and Q ₆ are forward biased, and the stabilized voltage is applied to output lines 19 and 2.
Output between 0 and 0. When a voltage is output between the output lines 19 and 20, the subsequent sensor circuit 21 operates.

The sensor circuit 21 detects strain with a bridge-type strain meter 23 (for example, a semiconductor strain meter), converts the strain value (transmission data) into a current, and transmits it to the central device 1. 22 is an operational amplifier for driving the strain meter 23 with a constant current, and its operating voltage is connected to the output line 1.
Given from 9,20. The first terminal of the strain meter 23 is connected to the output of the operational amplifier 22, and the second terminal opposite thereto is connected to the inverting input (-) of the operational amplifier 22, and is also connected to the output line through a resistor _R10 . 20. A constant voltage is applied from the battery 27 to the non-inverting input (+) of the operational amplifier 22 .

Operational amplifiers 24, 25, transistors Q ₇ , Q ₈
The diodes D ₅ , D ₆ and the resistor R ₁₁ pass a current proportional to the potential difference between the third and fourth terminals of the strain meter 23 into the line.
It constitutes a current conversion circuit that flows through the loops of L ₃ and L ₄ . Operational amplifiers 24 and 25 are connected to output lines 19 and 20
The output is the base of transistors Q ₇ and Q ₈ , the inverting input (-) is the emitter of transistors Q ₇ and Q ₈ , and the non-inverting input (+) is the strain meter. It is connected to the third and fourth terminals of 23. Transistors Q ₇ , Q ₈ , diodes D ₅ , D ₆ , and resistor R ₁₁ are connected in series with lines L ₃ , L ₄ . Although detailed operational analysis is omitted,
The voltage stabilizing circuit 18 is activated, and the lines L ₃ and L ₄
During the period when voltage is applied between
A current of value I shown by the following equation flows through L ₃ and L ₄ .

I≒e/R ₁₁ Here, e is the output of the strain meter 23, that is, the potential difference between the third and fourth terminals. However, operational amplifier 2
No. 4,25 has a sufficiently large oven gain and input impedance.

Here, the charge/discharge circuits 12 and 13 and the voltage detection circuits 15 and 16 will be explained.

When the switch 6 in the central device 1 is opened,
Capacitors C ₁ and C ₂ are charged, and each charging/discharging circuit 1
The output voltages e ₁ and e ₂ of 2 and 13 eventually rise to the applied charging voltage, that is, the output voltage (positive voltage) of the voltage stabilization circuit 11. In this state, when switch 6 is closed and the loop of lines L ₂ and L ₃ is closed,
Capacitors C ₁ and C ₂ start discharging, and the output voltage e ₁ ,
e ₂ gradually decreases. Since the power supply 4 is inserted into the loop of the lines L ₂ and L ₃ with a polarity that promotes discharge, the output voltages e ₁ and e ₂ drop beyond O volts, but the diodes D ₁ and D ₂ are conductive. Once the voltage drops to a negative voltage, it will not drop any further. When switch 6 is opened, charging begins and output voltages e ₁ and e ₂ rise again.

The voltage detection circuits 15 and 16 are connected to the charging and discharging circuits 12,
When the output voltages e ₁ and e ₂ of 13 are above a predetermined threshold, the output voltages e ₃ and e ₄ are held at "H" level, but when the output voltages e ₁ and e ₂ are lower than the threshold, the output voltage
Hold e ₃ and e ₄ at "L" level. The time T 1 , T 2 it takes for the output voltages e ₁ , e ₂ to drop to the above thresholds after starting discharging from a fully charged state, and the time T ₁ , T ₂ it takes for the output voltages e 1 , e 2 to fall to the above thresholds, and
The time T ₃ and T ₄ until e ₁ and e ₂ rise to the threshold value is
The values _of capacitors C ₁ and _{C 2} and resistors R ₂ to _{R 5} , voltage _detection circuit 15,
16 threshold values and the voltage value of the power supply 4 are determined. Note that it is not necessary to insert the power supply 4 into the discharge loop, but if the power supply 4 is inserted and current is drawn, it becomes easier to set the threshold values of the voltage detection circuits 15 and 16, and the discharge curve approaches a straight line. Therefore, there is an advantage that the voltage detection operation by the voltage detection circuits 15 and 16 becomes sharp.

Next, while referring to the timing diagram in Figure 4,
The overall operation of this embodiment will be explained.

Before starting to call each terminal device 2, the control circuit 9 of the central device 1 closes the switch 6 with the switch 5 open (time t ₁ ). As a result, the charging/discharging circuits 12 and 13 start discharging, and after _an hour T1, the output voltage _e3 of the voltage detection circuit 15 is inverted to the "L" level, and the counter 17 is reset. time t ₁
The control circuit 9 opens the switch 6 at time t ₂ when Ta time (T _a >T ₁ ) has elapsed since then. Charge/discharge circuit 12,1
3 starts, first the output voltage e ₄ of the voltage detection circuit 16 is inverted to the "H" level, and then the output voltage e ₃ of the voltage detection circuit 15 is inverted to the "H" level. This completes resetting the counters 17 in all terminal devices 2.

The control circuit 9 keeps the switch 6 open from time t ₂ until time t ₃ when T _b time (T _b ≫ T ₃ ) has elapsed, and after completely charging the charging/discharging circuits 12 and 14, the switch 6 is opened. is closed for T _c time (T ₁ > T _c > T ₂ ). Since the output voltage e ₂ of the charge/discharge circuit 13 drops below the threshold of the voltage detection circuit 16 (T _c > T ₂
Therefore, the output voltage _e4 of the same voltage detection circuit 16 is "L"
The counter 17 counts up by 1. Then the output voltage e ₂ increases again,
When the threshold value is exceeded, the output voltage _e4 is inverted to the "H" level. On the other hand, since the output voltage e ₁ of the charging/discharging circuit 12 starts to rise again before falling to the threshold of the voltage detection circuit 15 (because T ₁ > T _c ), the output voltage e ₃ of the voltage detection circuit 15 is "H". It remains at the same level. The control circuit 9 keeps the switch 6 open for a time T _d from time t ₄ to t ₅ , and after charging and discharging circuits 12 and 13 are completely charged, the switch 6 is closed again for a time T _c . As a result, the counter 1 in each terminal device 2
7 counts up by 1. Similarly below,
By intermittently closing the switch 6 at _Tc time intervals at _Td time intervals, the counter 17 is sequentially counted up.

In parallel with this counter-up control,
The control circuit 9 closes the switch 5 at regular intervals while the switch 6 is open, and instructs the voltage reading circuit 8 to read.

On the other hand, among the many terminal devices 2, in only one terminal device whose value of the internal counter 17 matches the value unique to the device itself, the transistor _Q4 is turned on and the sensor circuit 2 is turned on.
1 is activated and data transmission becomes possible. That is, that one terminal device is connected to the central device 1 at that time.
It is being called upon by more people. When the switch 5 in the central device 1 is closed, a current of a value corresponding to the strain value (transmission data) detected by the strain meter 23 is generated from the sensor circuit 21 in the specific terminal device being called at that time. is sent to the loop of lines L ₃ and L ₄ . This current flows through the resistor 7 in the central device 1.
The voltage is converted into a voltage and read by the voltage reading circuit 8.

〔Effect of the invention〕

As described in detail above, the present invention enables synchronized counting by opening and closing lines connected to two charging/discharging circuits in each terminal device on the central device side and controlling charging/discharging of each charging/discharging circuit. clock pulse (corresponding to e ₄ above) and reset pulse (e ₃ above)
) is generated inside the terminal device. That is, the configuration is such that clock and reset control is performed through a common line, and the number of lines for synchronous count control can be reduced compared to a system in which clock pulses and reset pulses are transmitted from a central device through separate lines. In addition, in a system in which clock pulses and reset pulses are directly transmitted from a central device, malfunctions are likely to occur due to attenuation of each pulse and noise contamination, but the present invention is based on charging and discharging of a charging and discharging circuit that is essentially less susceptible to noise. Since the clock pulse and reset pulse are generated inside the terminal device, there is no possibility of malfunction as described above.
Furthermore, since there is no need for a modulation circuit and a demodulation circuit as in the system that modulates and transmits clock pulses and reset pulses, the circuit configuration related to call control in the central device and terminal devices can be simplified as in the above embodiment. .

[Brief explanation of drawings]

1 to 4 are diagrams for explaining one embodiment of the present invention, in which FIG. 1 is a system configuration diagram of a telemeter system, FIG. 2 is a circuit diagram of a central device, and FIG. 3 is a terminal device. FIG. 4 is a timing chart for explaining the operation. 1...Central device, 2...Terminal device, 4...Power supply for current attraction, 6...Switch for charge/discharge control,
12, 13... Charge/discharge circuit, 14... Counter control circuit, 15, 16... Voltage detection circuit, 17...
Counter, 18...Voltage stabilization circuit, 21...Sensor circuit, _L1 to _L4 ...Line.

Claims (1)

[Claims] 1. In a telemeter system in which a central device selectively calls a plurality of terminal devices and transmits data to the central device, a line common to all the terminal devices is provided between each terminal device and the central device, and , a means for opening and closing the line is provided in the central unit, and in each terminal unit, two terminals having different time constants are connected to the line so as to discharge when the line is closed, and to which a charging voltage is constantly applied. It uses two charge/discharge circuits, a counter with a different value set for each terminal device, and the output voltages of the two charge/discharge circuits as input, and resets the counter when the line is closed for a first period. , a counter control circuit that counts up or down the counter when the line is closed for a second period that is different in length from the first period, and a count value of the counter and a set value of the counter match. A sensor circuit that operates at certain times is provided, and the central device closes the line for the first period and then intermittently closes the line for the second period to cause the counter to count and calculate the count value. 1. A terminal device calling method characterized in that a terminal device whose counter setting value matches the value of the counter is called and the terminal device is made to send data to a central device. 2. The terminal device calling system according to claim 1, characterized in that a power source for drawing current is connected in series to the line connected to the charging/discharging circuit. 3 The counter control circuit includes a first voltage detection circuit that inverts the logic level of the output voltage depending on whether the output voltage of one charge/discharge circuit is higher or lower than a predetermined threshold, and a first voltage detection circuit that inverts the logic level of the output voltage depending on whether the output voltage of one charge/discharge circuit is higher or lower than a predetermined threshold. and a second voltage detection circuit that inverts the logic level of the output voltage depending on whether it is higher or lower than a threshold value, and supplies the output voltage of the first voltage detection circuit to the reset input of the counter, and the second voltage detection circuit 2. The terminal device calling system according to claim 1, wherein the output voltage of the counter is applied to the clock input of the counter.