JPH0224209Y2 - - Google Patents

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Publication number
JPH0224209Y2
JPH0224209Y2 JP1982095433U JP9543382U JPH0224209Y2 JP H0224209 Y2 JPH0224209 Y2 JP H0224209Y2 JP 1982095433 U JP1982095433 U JP 1982095433U JP 9543382 U JP9543382 U JP 9543382U JP H0224209 Y2 JPH0224209 Y2 JP H0224209Y2
Authority
JP
Japan
Prior art keywords
signal
circuit
supplied
division
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP1982095433U
Other languages
Japanese (ja)
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JPS59261U (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
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Priority to JP9543382U priority Critical patent/JPS59261U/en
Publication of JPS59261U publication Critical patent/JPS59261U/en
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Granted legal-status Critical Current

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Description

【考案の詳細な説明】 本考案は走査電子顕微鏡等の像信号処理回路に
関し、特に2種の信号の除算信号を像信号として
用いるようにした走査電子顕微鏡等の像信号処理
回路に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an image signal processing circuit for a scanning electron microscope or the like, and more particularly to an image signal processing circuit for a scanning electron microscope or the like which uses a divided signal of two types of signals as an image signal.

走査電子顕微鏡においては二次電子信号、透過
電子信号、反射電子信号等の各種の検出信号が得
られるが、その内の2種の信号を除算回路に導
き、2種の信号の除算された信号を陰極線管に供
給して像を表示することが行われている。この場
合、除算回路は有限の出力電圧を有しているから
この値になると飽和状態となる。すなわち、除算
回路の分子と分母に入力される信号の大きさが適
切でないと、該回路は容易に飽和状態となり、除
算信号による像観察が不可能になつてしまう。従
来飽和状態となつた際には、その都度、オペレー
タは像を観察しながら分子あるいは分母に入力さ
れる信号の大きさを調整していたが、この作業は
甚だ面倒である。
In a scanning electron microscope, various detection signals such as a secondary electron signal, a transmitted electron signal, and a reflected electron signal are obtained. Two of these signals are led to a division circuit, and a signal obtained by dividing the two signals is generated. is supplied to a cathode ray tube to display images. In this case, since the division circuit has a finite output voltage, it becomes saturated when this value is reached. That is, if the magnitudes of the signals input to the numerator and denominator of the division circuit are not appropriate, the circuit easily becomes saturated, making it impossible to observe an image using the division signal. Conventionally, whenever saturation occurred, the operator would adjust the magnitude of the signal input to the numerator or denominator while observing the image, but this work was extremely troublesome.

本考案は上述した点に鑑みてなされたもので、
面倒な調整作業を伴わず、検出信号の変動によつ
ても、除算回路が飽和せず、良好な像観察を可能
とする走査電子顕微鏡等の像信号処理回路を提供
することを目的とする。
This invention was made in view of the above points,
It is an object of the present invention to provide an image signal processing circuit for a scanning electron microscope, etc., which does not require troublesome adjustment work, does not saturate a division circuit even when a detection signal fluctuates, and enables good image observation.

本考案に基づく走査電子顕微鏡等の像信号処理
回路は、試料への荷電粒子線の照射に伴い、該試
料から得られる2種の異つた情報信号を除算回路
によつて除算し、該除算信号を像信号として表示
装置へ供給するようにした像信号処理回路におい
て、該2種の信号の内少くともいずれか一方の信
号を信号強度可変手段を介して該除算回路に供給
し、該除算回路の出力信号を基準信号と比較する
比較手段を設け、該比較手段からの信号に応じて
該信号強度可変手段を制御し、該除算回路に供給
される該2種の異なつた情報信号の強度比を変化
させるように構成している。
The image signal processing circuit of a scanning electron microscope or the like based on the present invention divides two different information signals obtained from the sample by a dividing circuit when the sample is irradiated with a charged particle beam, and the divided signal is An image signal processing circuit configured to supply an image signal to a display device as an image signal, wherein at least one of the two types of signals is supplied to the division circuit via a signal strength variable means, and the division circuit is provided with comparison means for comparing the output signal of the output signal with a reference signal, and controls the signal strength varying means in accordance with the signal from the comparison means to determine the intensity ratio of the two different information signals supplied to the division circuit. It is configured to change the

以下本考案の一実施例を添付図面に基づき詳述
する。
An embodiment of the present invention will be described below in detail with reference to the accompanying drawings.

第1図は本考案の第1の実施例を示しており、
図中1及び2は像信号処理回路の入力端子であ
り、端子1には例えば二次電子検出信号が供給さ
れ、端子2には例えば反射電子検出信号が供給さ
れている。該端子1及び2は夫々減衰器3及び4
に供給され、任意の振幅に設定される。該減衰器
3及び4の出力は夫々可変減衰器5及び6に供給
される。該可変減衰器5の出力信号は除算回路7
の分子端子に供給され、他方の可変減衰器6の出
力信号はダイオードD及び抵抗R1及びR2の接続
点を経て除算回路7の分母端子に供給される。該
ダイオードD及び抵抗R1,R2は、可変減衰器6
の出力信号強度が零に近くなり、分子に比べて分
母が非常に小さくなつた場合に、該除算回路7の
出力が容易に飽和してしまうために、該除算回路
の分母入力が零になることを防ぐために設けられ
ている。該可変減衰器6の出力信号強度が抵抗
R1とR2との分割比で決められる電圧値以下とな
ると、該ダイオードDは非導通状態となり、該除
算回路7の分母入力には該抵抗の分割比で決めら
れる電圧が印加される。該除算回路7の出力信号
は陰極線管(図示せず)に接続されている端子T
に供給されると共に比較回路8にも供給され、基
準電源9からの基準電圧と比較される。該比較回
路8は除算回路7の出力電圧が該基準電圧を越え
た時パルスを発生する。該パルスはカウンター1
0に供給されるが、該カウンター10は供給され
たパルスに基づき前記可変減衰器5及び6の減衰
率を制御する。
FIG. 1 shows a first embodiment of the present invention,
In the figure, 1 and 2 are input terminals of the image signal processing circuit, terminal 1 is supplied with, for example, a secondary electron detection signal, and terminal 2 is supplied with, for example, a reflected electron detection signal. The terminals 1 and 2 are connected to attenuators 3 and 4, respectively.
and set to an arbitrary amplitude. The outputs of the attenuators 3 and 4 are supplied to variable attenuators 5 and 6, respectively. The output signal of the variable attenuator 5 is sent to the divider circuit 7.
The output signal of the other variable attenuator 6 is supplied to the denominator terminal of the divider circuit 7 via the connection point of the diode D and the resistors R 1 and R 2 . The diode D and resistors R 1 and R 2 are connected to the variable attenuator 6.
When the output signal strength of becomes close to zero and the denominator becomes very small compared to the numerator, the output of the division circuit 7 easily becomes saturated, and the denominator input of the division circuit becomes zero. It is designed to prevent this from happening. The output signal strength of the variable attenuator 6 is
When the voltage falls below the voltage value determined by the division ratio of R 1 and R 2 , the diode D becomes non-conductive, and the voltage determined by the division ratio of the resistors is applied to the denominator input of the division circuit 7. The output signal of the division circuit 7 is sent to a terminal T connected to a cathode ray tube (not shown).
It is also supplied to the comparison circuit 8 and compared with the reference voltage from the reference power supply 9. The comparator circuit 8 generates a pulse when the output voltage of the divider circuit 7 exceeds the reference voltage. The pulse is counter 1
0, and the counter 10 controls the attenuation rates of the variable attenuators 5 and 6 based on the supplied pulses.

上述した如き構成において、まず減衰器3及び
4が手動で調整され、適宜なる強度の信号が除算
回路7に供給される。又、比較回路8に供給され
る基準電圧源からの基準電圧値は、除算回路7の
飽和電流値より若干低く設定される。このような
状態で像の観察が行われるが、端子1及び2に供
給される二次電子信号及び反射電子信号は試料状
態に応じて変化し、例えば、ある時点で二次電子
信号が強くなると、それに伴つて除算回路7の出
力電圧が高くなる。該回路7の電圧が基準電圧源
9からの電圧値以上となると該比較回路8からは
パルスが発生しカウンター10に供給されるが該
カウンター10は供給されたパルスに基づいて可
変減衰器5,6を制御する。該可変減衰器5はカ
ウンター10にパルスが供給される毎に、所定量
ずつ該減衰率が高められるように制御され、可変
減衰器6はカウンター10にパルスが供給される
毎に、所定量ずつ減衰率が低められる。その結
果、除算回路7は飽和せず、常に良好なる像観察
を行うことができる。
In the configuration as described above, first, the attenuators 3 and 4 are manually adjusted, and a signal of appropriate strength is supplied to the divider circuit 7. Further, the reference voltage value from the reference voltage source supplied to the comparator circuit 8 is set to be slightly lower than the saturation current value of the divider circuit 7. The image is observed in this state, but the secondary electron signal and reflected electron signal supplied to terminals 1 and 2 change depending on the sample state. For example, if the secondary electron signal becomes strong at a certain point, , the output voltage of the divider circuit 7 increases accordingly. When the voltage of the circuit 7 exceeds the voltage value from the reference voltage source 9, a pulse is generated from the comparator circuit 8 and is supplied to the counter 10. Based on the supplied pulse, the counter 10 converts the variable attenuator 5, Control 6. The variable attenuator 5 is controlled so that the attenuation rate is increased by a predetermined amount each time a pulse is supplied to the counter 10, and the variable attenuator 6 is controlled to increase the attenuation rate by a predetermined amount each time a pulse is supplied to the counter 10. Attenuation rate is reduced. As a result, the division circuit 7 is not saturated, and good image observation can always be performed.

第2図は本考案の他の実施例を示しており、第
1図の実施例と同一部分は同一番号を付し、その
詳細な説明を省略する。この実施例において除算
回路7の出力信号は比較回路8に供給されると共
に、第2の比較回路11に供給される。該比較回
路11は基準電圧源12からの基準電圧値と該除
算回路7の出力電圧とを比較し、該除算回路7の
出力電圧が基準電圧より低くなつた際にパルスを
発生する。該比較回路11はフリツプフロツプ回
路13に接続されているが、該フリツプフロツプ
回路13は比較回路11からのパルスの供給を受
けてローレベル信号を発生し、又、走査信号発生
回路(図示せず)に接続された端子14を介して
供給される走査画面の−フレーム終了毎の消去信
号によつてリセツトされる。該フリツプフロツプ
回路13は端子14からの消去信号が供給される
ゲート回路15に接続されており、該消去信号は
該フリツプフロツプ回路の出力がハイレベルに維
持されている時にのみ該ゲート回路15を通過し
てアツプダウン・カウンター16のアツプ端子に
供給される。該カウンター16のダウン端子には
比較回路8からのパルスが供給される。
FIG. 2 shows another embodiment of the present invention, in which the same parts as in the embodiment of FIG. 1 are given the same numbers, and detailed explanation thereof will be omitted. In this embodiment, the output signal of the division circuit 7 is supplied to a comparator circuit 8 and also to a second comparator circuit 11 . The comparison circuit 11 compares the reference voltage value from the reference voltage source 12 and the output voltage of the division circuit 7, and generates a pulse when the output voltage of the division circuit 7 becomes lower than the reference voltage. The comparison circuit 11 is connected to a flip-flop circuit 13, which receives pulses from the comparison circuit 11 and generates a low level signal, and also outputs a low level signal to a scanning signal generation circuit (not shown). It is reset by an erase signal supplied through the connected terminal 14 at the end of each frame of the scanning screen. The flip-flop circuit 13 is connected to a gate circuit 15 to which an erase signal from a terminal 14 is supplied, and the erase signal passes through the gate circuit 15 only when the output of the flip-flop circuit is maintained at a high level. and is supplied to the up terminal of the up-down counter 16. A pulse from the comparator circuit 8 is supplied to the down terminal of the counter 16.

上述した実施例は除算回路7の出力信号が小さ
くなつた場合に自動的にその出力を大きくするこ
とを可能とするもので、該基準電圧源12の電圧
値は基準電圧源9の電圧値より低く設定されてい
る。該端子14には第3図aに示す走査信号発生
回路からの消去信号パルスP1が供給されており、
該除算回路7の出力が基準電圧源12の電圧値以
上となると第3図bに示すパルスP2が比較回路
11から発生する。該パルスP2の供給を受けフ
リツプフロツプ回路13はローレベル信号を出力
し、その結果第3図aの消去信号パルスP1はゲ
ード回路を通過することができずカウンター16
の計数値に変化は無い。尚第3図cはフリツプフ
ロツプ回路13の出力を、第3図dはゲート回路
15の出力信号を示している。従つてこの状態で
は前記可変減衰器5,6による信号の減衰率にも
変化が無い。この状態の後、走査信号発生回路に
よる走査画面の1フレーム分の走査が終了し、消
去信号パルスが解除された直後にフリツプフロツ
プ回路13はリセツトされ、その出力はハイレベ
ルとなる。一方1フレーム走査の内に除算回路7
の出力が継続して基準電圧値より低い場合には、
比較回路11からはパルスが発生せず、従つてフ
リツプフロツプ回路13の出力はハイレベルに維
持される。その結果、消去信号パルスはゲート回
路15を通過し、カウンター16のダウン端子に
供給され、その計数値を低くする。このカウンタ
ー16の計数値が低くされたことに伴い、前記可
変減衰器5,6は制御され、該減衰器5は所定量
その減衰率が低くされ、減衰器6は所定量その減
衰率が高くされて、除算回路分子入力信号強度を
大きくし、分母入力信号強度を小さくして、結果
として除算回路出力を観察に適した信号レベルと
する。
The embodiment described above makes it possible to automatically increase the output when the output signal of the division circuit 7 becomes small, and the voltage value of the reference voltage source 12 is higher than the voltage value of the reference voltage source 9. It is set low. The terminal 14 is supplied with an erasing signal pulse P1 from the scanning signal generating circuit shown in FIG. 3a,
When the output of the divider circuit 7 exceeds the voltage value of the reference voltage source 12, a pulse P2 shown in FIG. 3b is generated from the comparator circuit 11. In response to the supply of the pulse P2 , the flip-flop circuit 13 outputs a low level signal, and as a result, the erase signal pulse P1 of FIG.
There is no change in the count value. Incidentally, FIG. 3c shows the output signal of the flip-flop circuit 13, and FIG. 3d shows the output signal of the gate circuit 15. Therefore, in this state, there is no change in the signal attenuation rate by the variable attenuators 5 and 6. After this state, the flip-flop circuit 13 is reset immediately after the scanning signal generating circuit finishes scanning one frame of the scanning screen and the erasing signal pulse is released, and its output becomes high level. On the other hand, within one frame scanning, the division circuit 7
If the output of continues to be lower than the reference voltage value,
No pulse is generated from comparator circuit 11, so the output of flip-flop circuit 13 is maintained at a high level. As a result, the erase signal pulse passes through the gate circuit 15 and is supplied to the down terminal of the counter 16, lowering its count value. As the count value of the counter 16 is lowered, the variable attenuators 5 and 6 are controlled, and the attenuator 5 has its attenuation rate lowered by a predetermined amount, and the attenuator 6 has its attenuation rate increased by a predetermined amount. Then, the numerator input signal strength of the division circuit is increased and the denominator input signal strength is decreased, resulting in the division circuit output having a signal level suitable for observation.

以上本考案を詳述したが本考案は簡単な構成に
より観察に適した像信号を陰極線管の如き表示装
置に供給することができる。尚、本考案は上述し
た実施例に限定されることなく幾多の変形が可能
である。例えば、除算回路に供給される2種の信
号強度を共に制御するように構成したが、一方の
信号のみ制御しても良い。又走査電子顕微鏡を例
に本考案を説明したが、他の荷電粒子線装置にも
本考案を適用し得る。
The present invention has been described in detail above, and the present invention can supply image signals suitable for observation to a display device such as a cathode ray tube with a simple configuration. Note that the present invention is not limited to the embodiments described above, and can be modified in many ways. For example, although the two types of signal intensities supplied to the division circuit have been configured to be controlled together, only one signal may be controlled. Further, although the present invention has been explained using a scanning electron microscope as an example, the present invention can be applied to other charged particle beam devices.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図及び第2図は夫々本考案の一実施例を示
すブロツク図、第3図は第2図に示した実施例を
説明するための信号波形を示す図である。 3,4:減衰器、5,6:可変減衰器、7:除
算回路、8:比較回路、9:基準電圧源、10:
カウンター。
1 and 2 are block diagrams showing one embodiment of the present invention, and FIG. 3 is a diagram showing signal waveforms for explaining the embodiment shown in FIG. 2. 3, 4: attenuator, 5, 6: variable attenuator, 7: division circuit, 8: comparison circuit, 9: reference voltage source, 10:
counter.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 試料への荷電粒子線の照射に伴い、該試料から
得られる2種の異なつた情報信号を除算回路によ
つて除算し、該除算信号を像信号として表示装置
へ供給するようにした像信号処理回路において、
該2種の信号の内少なくともいずれか一方の信号
を信号強度可変手段を介して該除算回路に供給
し、該除算回路の出力信号を基準信号と比較する
比較手段を設け、該比較手段からの信号に応じて
該信号強度可変手段を制御し、該除算回路に供給
される該2種の異なつた情報信号の強度比を変化
させるように構成した像信号処理回路。
Image signal processing in which two different information signals obtained from a sample are divided by a division circuit as the sample is irradiated with a charged particle beam, and the divided signal is supplied as an image signal to a display device. In the circuit,
Comparing means is provided for supplying at least one of the two types of signals to the dividing circuit via the signal strength varying means, and comparing the output signal of the dividing circuit with a reference signal, and An image signal processing circuit configured to control the signal intensity variable means in accordance with a signal to change the intensity ratio of the two different information signals supplied to the division circuit.
JP9543382U 1982-06-25 1982-06-25 Image signal processing circuit Granted JPS59261U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9543382U JPS59261U (en) 1982-06-25 1982-06-25 Image signal processing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9543382U JPS59261U (en) 1982-06-25 1982-06-25 Image signal processing circuit

Publications (2)

Publication Number Publication Date
JPS59261U JPS59261U (en) 1984-01-05
JPH0224209Y2 true JPH0224209Y2 (en) 1990-07-03

Family

ID=30227902

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9543382U Granted JPS59261U (en) 1982-06-25 1982-06-25 Image signal processing circuit

Country Status (1)

Country Link
JP (1) JPS59261U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5586059A (en) * 1978-12-25 1980-06-28 Hitachi Ltd Ion micro analyser

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5586059A (en) * 1978-12-25 1980-06-28 Hitachi Ltd Ion micro analyser

Also Published As

Publication number Publication date
JPS59261U (en) 1984-01-05

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