JPH02241284A - Encoder - Google Patents

Abstract

PURPOSE:To improve encoding efficiency by providing a controller, which controls the delay time of a delaying device and outputs the delay time for each section, and three encoders to respectively encode the output signals of an adder, subtracter and controller, and compressing an encoding signal by using correlation between input signals. CONSTITUTION:Two input signals Lti and Rti are divided to the sections of a fixed time D respectively by using a divider 10. The total sum of an absolute value in a section T1 of the output from the subtracter is computed to the input signal Rti with an mD as a parameter. Then, the delay time mD, in which a value is made minimum, is defined as the delay time optimum for the Rti in the section T1 and outputted as the data of 4 bits from the controller. Accordingly, since the absolute value of the output from a subtracter 13 in the section T1 is made small, a first encoder 15 can execute encoding by a smaller word length, for example, by one bit. Samely, concerning the second and third sections, the delay time is outputted as the data of 4 bits for each section from the controller with the mD as the parameter.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to an encoding device for compressing audio and image signals.

BACKGROUND OF THE INVENTION In recent years, encoding devices have been using signal compression techniques to transmit higher quality audio and images using limited transmission line capacity, such as in video telephones. Many of the signal compression techniques used for this purpose use temporal correlation of a single signal.

An example of the above-mentioned conventional encoding device will be described below with reference to the drawings.

FIG. 3 shows the configuration of a conventional encoding device. In FIG. 3, 111 is a delay device, 112 is a subtracter, 11
3 is a quantizer, which is connected as shown.

The operation of the encoding device configured as described above will be described below. First, the input signal is given a fixed time delay by the delay device 111, and then the difference between the input signal and itself is taken by the subtracter 112. This operation is interpreted as removing the autocorrelation component of the input signal and extracting the residual. Quantizer 11
3 encodes this residual, and in a simple case, the residual signal is requantized to, for example, 4 bits. Information truncated by the encoder 113 cannot be decoded by any decoder.

(For example, "Digital signal processing of images, published by Kogyo Shinbunsha, written by Takahiko Fukinuki, p. 171)."

Problems to be Solved by the Invention However, if the above configuration is applied as is to a case where there are multiple input signals, and each human input signal is encoded individually, the data amount of the encoded output signal will be smaller than the number of input signals. Since it is multiplied by n (n), there was a problem that the compression effect was poor.

In view of the above problems, the present invention provides an encoding device that efficiently compresses and encodes a plurality of input signals.

Means for Solving the Problems In order to solve the above problems, the encoding device of the present invention includes a divider that divides the signals of multiple channels into intervals of a fixed time, and an output signal for each interval of the multiple channels of the divider. A delay device that adds an arbitrary time delay to each channel, an adder and a subtracter that use the output signal of the delay device to create a sum signal and a difference signal, and a The delay time of the delay device is controlled by an integer multiple of the above-mentioned fixed time so that the value is minimized, and the output signals of the adder, subtracter, and controller are encoded by a controller that outputs the delay time for each section, respectively. The encoder includes a first encoder, a second encoder, and a third encoder.

Effect: With the above-described configuration, the present invention utilizes the correlation between a plurality of input signals, which has not been used in the past, to compress encoded signals and improve the information transmission rate.

Embodiment Hereinafter, an encoding apparatus according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows the configuration of an encoding apparatus according to an embodiment of the present invention, in which the number of input signals is two. In FIG. 1, 10 is a divider, 11 is a delay device, 12 is an adder, 13 is a subtracter, 14 is a controller, 15 is a first encoder, 16 is a second encoder, and 17 is a In the third encoder, two input signals are each divided into sections of fixed time by a divider 10, a delay is added to the output of the divider 10 by a delay device 11, and the output is sent to an adder 12 and a subtracter. 13, the output of the subtracter 13 is input to the controller 14, and the output of the controller 14 and the outputs of the adder 12 and subtracter 13 are input to the first encoder and the second encoder, respectively. and a third encoder.

FIG. 2 shows the output of the divider 10, which divides the input signal into three sections Tl, T2 . This is the case when it is divided into T3. In Fig. 2, (a) is the right channel of the music signal;
(b) is the left channel.

Regarding the encoding device configured as above, the first
The operation will be explained using FIG.

Let the two input signals be the left channel and right channel signals of a music signal, and let the left channel signal at an arbitrary time ti be L (ti) and the right channel signal R (ti).

First, two input signals L(ti) and R(ti)
is divided into sections each having a fixed time period using the divider 10.

Assume that n samples of music signals are included in this section. Here, each section is divided into three sections as shown in FIG. The left channel signal in section T1 is L(ti)
, i=1.2.・・・n, right channel signal, R
(ti), i=1.2. =n, the left channel signal in section T2 is L(ti), i=n+1. n+2.・
・2n, the right channel signal is R(ti), i=n+1.
n-1-2,=2n, the left channel signal in section T3 is L(ti), 1=2n+1.2n+2.・・・
3n, the right channel signal is R(ti), 1=2n+1,
2n+2. ...3n.

Next, each section TIT2 divided by the delay device 11
．． A delay is added to the signal R(ti) of T3. First, focusing on the first section TI, when a delay mD that is an integral multiple of a certain time period is added to the signal R(ti) by the delay device 11, the output signal RmD of the delay device is expressed as Rm D (ti) = R (ti) 10 α (ti, m
D) −(1)

Signal L (ti) and signal Rm D with delay mD
Adder 12 and subtracter 13 when (ti) is input
The outputs of are respectively L (ti) 1Rm D (ti) −L(ti)+R(ti)+α(ti, mD) −
(2) L (ti) -Rm D (ti) -L (ti) -R(ti) -α(ti, mD)
−(3).

The two signals are the left channel and right channel signals of the music signal, and the correlation between the signals is high, so at any time ti
Let the left channel signal be L(ti) and the right channel signal be R(ti), then R(ti) −L (ti)
-1-β(ti) ...(4)(l L
(ti) l >> 1β(ti) l ).

β is a real number.

Therefore, equations (2) and (3) are L (ti) 10Rm D (ti) −2L (ti)+β(ti) + cx (ti, m
D) L (ti) -Rm D (ti) (β(ti)+α(ti, mD)) ...(5) ...(6) It can be expressed as follows.

The sum of the absolute values of the subtracter output in the interval TI is as follows. For the input signal R(ti), calculate equation (7) using mD as a variable, and calculate the delay time m when the value is the minimum.
Let D be the optimum delay time of the right channel signal R(ti) in section T1, and output from the controller as 4-bit data. Therefore, the output of the subtractor 13 in the interval T1 -
(β(ti) + α(ti, mD) ti = 1
.

Since the absolute values of 2, . . . , n are small, the second encoder 15 can encode with a smaller word length, for example, 1 bit.

On the other hand, the output of the adder 12 (2L(ti)+β(ti)+α
(ti, mD)) at any time (ti) is 2 L (ti) >> (β(ti) + at
(ti, mD)), so the encoder 1 is twice as large as L (ti) and has at most 1 bit more than the conventional encoder.
This can be achieved with 3.

Similarly, for the second and third sections, using mD as a variable, calculate the sum of the absolute values of the outputs of the subtracters in each section, and calculate the delay time when the minimum sum is obtained for that section. 4 from the controller as the optimal delay time of
Output as bit data for each section.

The data amount of the output signal of a conventional encoder is 1
4 bits per sample, 8 bits for both left and right channels.
It had become a bit.

Assuming that the total number of samples is 120, the data amount of the entire encoder output signal in this embodiment is 5 bits per sample in the first encoder, which is 1 bit more than the conventional one, and 5 bits in the second encoder per sample. outputs 1 bit, and the third encoder outputs 4 bits in 1 section.
Since bits are output, there will be 3 x 4 bits in 3 sections, and 1
The number of samples is 3 x 4 ÷ 120 = 0.1 bits, and the total is 5 + 1 + (4 ÷ 120) It becomes possible.

As described above, according to this embodiment, there is a divider that divides the signals of multiple channels into intervals of a fixed time, and a delay of an arbitrary time is added for each channel to the output signal of the divider for each interval of the multiple channels. A delay device, an adder and a subtracter that use the output signal of the delay device to create a sum signal and a difference signal, and an output signal of the subtractor as input, and the output signal is input for a certain period of time so that the absolute value of the input signal is minimized. A controller that controls the delay time of the delay device by an integer multiple and outputs the delay time for each section, a first encoder that encodes the output signals of the adder, the subtracter, and the controller, and a second encoder that encodes the output signals of the adder, subtracter, and controller, respectively. The encoder includes an encoder and a third encoder, and when the number of input signals is two, it is possible to realize an efficient encoder by utilizing the correlation between the input signals.

Note that in this embodiment, the first and second encoders 14.
15 is a 5.1-bit quantizer, but a general encoder may be used, for example, the entire encoding apparatus shown in FIG. 3 may be used. In addition, in this embodiment, the data amount is 4 bits as the output for each section from the delay device.
In general, it can be any bit.

Furthermore, in this embodiment, a delay is added only to the right channel signal of the input signal, but the left channel signal or
A delay may be added to both channel signals. Further, in this embodiment, the input signal is divided into three sections, but the number is not limited to three and may be any number. Further, although the present embodiment shows the case where the number of input signals is two, the encoding efficiency can generally be improved in the same manner even when the number of input signals is three or more.

Effects of the Invention As described above, the present invention includes a divider that divides a signal of multiple channels into intervals of a fixed time, and a delay of an arbitrary time for each channel to the output signal of the divider for each interval of the multiple channels. A delay device, an adder and a subtracter that use the output signal of the delay device to create a sum signal and a difference signal, and an output signal of the subtractor as input, and the output signal is input for a certain period of time so that the absolute value of the input signal is minimized. Control the delay time of the delay device with an integer multiple,
It includes a controller that outputs a delay time for each section, and a first encoder, a second encoder, and a third encoder that encode output signals of the adder, subtracter, and controller, respectively. By doing so, it is possible to realize efficient encoding such as obtaining better quality with the same transmission capacity when there are multiple input signals.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an encoding apparatus according to an embodiment of the present invention, FIG. 2 is a diagram showing the output of a divider, and FIG. 3 is a block diagram of a conventional encoding apparatus. 10...divider, 11...delay unit, 1
2...Adder, 13...Subtractor, 14
...Controller, 15...First encoder, 16...Second encoder, 17...
Third encoder, 111...delay unit, 112...
...Subtractor, 113...Quantizer.

Claims (1)

[Claims] a divider that simultaneously inputs signals of multiple channels and divides the input signals of the multiple channels into intervals of a certain time;
A delay device that adds an arbitrary time delay for each channel to the output signal for each section of the plurality of channels of the divider, and a sum signal and a difference signal are created using the output signal for each section of the plurality of channels of the delay device. an adder and a subtracter; a controller that receives the output signal of the subtracter, controls the delay time of the delay device, and outputs the delay time for each section; the adder, the subtracter, and the controller; The controller includes a first encoder, a second encoder, and a third encoder that respectively encode the output signal of the controller, and the controller encodes the absolute value of the output signal of the subtracter for each section. An encoding device characterized in that the delay time of the delay device is controlled so that the sum of values is minimized, and the delay time is an arbitrary integral multiple of the certain time.