JPH02240936A - Semiconductor element - Google Patents

Abstract

PURPOSE:To reduce a noise figure by providing an insulating film in a part not contributing to mutual conductance, out of parts of junction between a channel part and a substrate gate part. CONSTITUTION:An insulating film 8 is disposed between a substrate 1 and a source region 6 as well as a drain region 7. Therefore a pn junction is not formed between a gate part on the substrate 1 side and the source region 6 and, consequently, a junction capacity dose not exist. Accordingly, the capacity in this part does not contribute to mutual conductance, and therefore J-FET of low capacity can be formed without deteriorating the mutual conductance and a gate input capacity. In addition, the junction capacity is not generated also between the gate part on the substrate 1 side and the drain region 7 and a feedback capacity is reduced as well. Thereby a noise figure is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a junction field effect transistor, and more particularly to the structure of a broadband, low noise, low capacitance junction field effect transistor.

[Conventional technology]

Junction field effect transistors (J-FETs) are used in video camera preamplifiers.

For example, FIG. 13 is a diagram showing an n-channel type J-FET. This n-channel J-FET has an n-type epitaxial layer 2 on the main surface (upper surface) of a substrate 1 made of P-type silicon. A p-type gate (C)wi region 5 and a p-type gate (C)6N region 5 are formed on an island 4 provided in this epitaxial layer 2 and surrounded by a P-type isolating region 3 that reaches the substrate 1. It has a structure in which a source (S) Off region 6 and a drain (D) SJI region 7 are provided on the left and right, both of which are n♦-shaped.

Further, a predetermined portion of the surface of the epitaxial layer 2 is made of SiO
It is covered with an insulator P14B made of an x film. Further, a source voltage $49 is provided on the source region 6, and a drain electrode 10 is provided on the drain region 7. Further, on the back surface of the substrate 1, a gate electrode 11 is provided. This gate electrode 11 is electrically connected to the gate H1 region 5 via the isolation region 3. In addition,
Regarding J-FET, please refer to "Electronic Device ■" published by Shokodo.
Published November 7, 1978, described on pages 157 to 162.

[Problem to be solved by the invention]

J-FETs for video camera preamplifiers are required to have low input capacitance and high mutual conductance characteristics in order to reduce noise in video camera preamplifier sets. Measures to reduce the input capacitance include (1) making the gate length as narrow as possible, and (2) lowering the p-type impurity concentration in the substrate, but with either method, the capacitance is However, the mutual conductance (
g, ) and an increase in gate input resistance (Rg).

An object of the present invention is to obtain a junction field effect transistor that can have a low capacitance without deteriorating mutual conductance g and gate input resistance Rg.

The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] A brief overview of typical inventions disclosed in this application is as follows.

That is, the J-FET of the present invention has a structure in which an insulating film is provided between the source region, the drain region, and the substrate.

[Effect]

As described above, in the J-FET of the present invention, since an insulating film is provided between the source region and drain region and the substrate, a pn junction is formed between the gate portion on the substrate side and the source region. Junction capacitance ceases to exist because it is no longer formed. Therefore, since the capacitance of this portion does not contribute to mutual conductance, a low capacitance J-FET can be formed without deteriorating mutual conductance and gate input capacitance. Furthermore, no junction capacitance is generated between the gate portion and the drain region on the substrate side, and feedback capacitance is also reduced.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view showing the main parts of a semiconductor element constituting a J-FET according to an embodiment of the present invention, FIG. 2 is a schematic plan view, and FIGS. FIG. 3 is a cross-sectional view showing a state in which a wafer is formed with a rich pattern on the main surface of the wafer, FIG. 4 is a cross-sectional view of the wafer showing an insulating film state, and FIG. Figure 6 is a cross-sectional view of the wafer showing the state in which photoresist has been selectively formed! i! A cross-sectional view of a wafer showing a state in which a portion of the edge film is removed, FIG. 7 is a cross-sectional view of a wafer showing a state in which an epitaxial layer is selectively formed on the main surface, and FIG. 8 is a cross-sectional view of a wafer showing a state in which a polysilicon film is formed on the main surface. 9 is a sectional view of the wafer showing the state in which a photoresist film has been selectively formed; FIG. 10 is a sectional view of the wafer in which the polysilicon film has been selectively removed; FIG. 11 is a cross-sectional view of the wafer showing a state in which isolation is formed, and FIG. 12 is a cross-sectional view of the wafer on which J-FETs are formed.

The semiconductor device according to the present invention, that is, the J-FET, has a first
As shown in the figure and FIG. 2, it is a rectangular body. As shown in FIG.
A substrate 1 made of silicon (semiconductor) of conductivity type), a channel part 12 made of n-type (second conductivity type) provided on the main surface of this substrate 1, and a channel part 12 arranged so as to surround this channel part 12. and p electrically connected to the p÷-shaped substrate 1.
- Insulation provided at the interface between the shaped isolation region 3 and the island 4 consisting of the supplementary substrate 1 and the channel portion 12 surrounded by the isolation region 3, and in the region facing the source region and drain region, which will be described later. It consists of 11915.16. Furthermore, in the surface layer of the island 4, as shown in FIG.
A fil region 5 is formed, and an n◆-type source region 6 and a drain region 7 are formed on both sides of the gate region 5.
is provided. Both ends of the gate region 5 are separated from the island 4 and form a p◆-shaped isolation region 3.
It has extended to. Therefore, the gate region 5 is electrically connected to the substrate 1, and the substrate 1 also functions as a gate.

On the other hand, the main surface side of the substrate l is covered with an insulating film 8. However, the insulating film 8 on the source region 6 and drain region 7 is removed, and a source electrode 9 and a drain electrode 1G made of aluminum are provided in this portion. As shown in FIG. 2, the source electrode 9 and the drain electrode 10 have one end separated from the island 4 and a wide wire bonding pad 17, 18 formed at the tip. Said island4. Gate region 5, source region 6. Drain region7. Source electrode 9. drain electrode lO
Each pattern is as shown in FIG. Further, the insulating films 15 and 16 are hatched areas in the figure. Further, on the back side of the substrate 1, a gate electrode 11 made of an Au-based electrode is formed.

Such a J-FET consists of a p-type substrate and a source region 6
Since the insulating films 15 and 16 are disposed between the capacitor and the drain region 7, a pn junction unlike in the conventional product does not occur at this interface, so that no junction capacitance occurs.

Next, a method for manufacturing a J-FET will be described with reference to FIGS. 3 to 13.

First, a substrate l made of p÷ type (first conductivity type) silicon and having a thickness of about 350 IIm is prepared. Since this substrate 1 has a large diameter of several inches, it will be referred to as a wafer 20 hereinafter. As shown in FIG. 3, this wafer 20 is selectively coated with photoresist WI! on its main surface. 21 is formed, and using this photoresist film 21 as a mask, the main surface of the wafer 20 is etched away to a depth of about 1 μm to form depressions 22,
23 is formed. These enrichments 22 and 23 are formed widely in regions facing the source region 6 and drain region 7, and are hatched regions as shown in FIG.

Next, the photoresist film 21 is removed.

Thereafter, as shown in FIG. 4, a 1 μm thick film of Sin! is applied over the entire main surface of the wafer 20. The insulating film 24 consisting of a CV
It is formed by D method or thermal oxidation method.

In the case of the thermal oxidation method, for example, the insulating film 24 is formed by processing for 260 minutes under a lOOOO'C furnace cold wet 08. Note that in the insulating film 24, the insulating film 24 embedded in the depressions 22 and 23 is replaced by the insulating film 15. This will be referred to as an insulating film 16.

Next, a photoresist film 25 is selectively formed on the main surface of the wafer 20 by conventional photolithography. As a result, a photoresist film 25 is formed on the insulation 115 and the insulation film 16.

Next, the exposed insulating film 24 is etched using the photoresist film 25 as a mask, and the photoresist film 25 is removed to form an insulating structure selectively buried in the main surface of the substrate 1, as shown in FIG. A wafer 20 having a film 15 and an insulating film 16 is formed.

Next, as shown in FIG. 7, an n-type epitaxial layer 2 is formed on the exposed main surface of the substrate l of the wafer 20. Epitaxial growth can be performed, for example, using 5iHx Cf
Lt (silicon dioxide) and PR.

By processing at 1070° C. for 2 minutes while flowing (phosphine), an n-type epitaxial layer 2 with a thickness of 1.0 pm is formed.

Next, n-type polysilicon is deposited over the entire main surface of the wafer 20 by CVD. The processing conditions were 570°C while flowing SiHm (monosilane) and PH1.
Treat at ℃ for 400 minutes. As a result, as shown in FIG. 8, an n-type polysilicon layer 3 with a thickness of about 1°0 μm
0 is formed.

Next, as shown in FIG. 9, the insulation is removed by conventional photolithography. 1115 and insulation 11116
After forming a photoresist film 31 only on the upper polysilicon layer 30, using the photoresist film 31 as a mask,
removing the polysilicon layer 30 on N2 during epitaxy;
Then, the photoresist film 31 is removed to obtain a wafer 20 as shown in FIG. In addition, in the figure, it is divided into an n-type epitaxial layer 2 and an n-type polysilicon layer 30, but since it is an n-type (second conductivity type) in the following, it will ultimately be called a channel. Since this is the region, it will be referred to as the channel section 12.

Next, as shown in FIG.
After providing an insulator 118 with a thickness of approximately λ, boron (B) is implanted at a high concentration to form a p♦-shaped isolation region 3 that reaches the substrate l.

As a result, a rectangular island 4 is formed as shown in FIG.

Next, the insulation WA8 is removed in stripes, and boron implantation and phosphorus implantation are performed to form the p◆-shaped game H1 region 5, as shown in FIG.
Then, a source region 6 and a drain region 7, which are n◆-shaped and are disposed with this gate region 5 in between, are formed. In this case, the gate region 5 is provided so as to extend away from the island 4, as shown in FIG. 2, and as a result is electrically connected to the p◆-type substrate l. Next, the insulating film 8 facing the source region 6 and drain region 7 is removed, and a source electrode 9 and a drain electrode 10 made of aluminum are formed in this portion. Further, the wafer 20 is thinned by back etching the lower surface of the substrate l. The thickness of the wafer 20 is approximately 160 pm.
After that, a gold thread gate electrode 11 is formed on the back surface of the substrate l by vapor deposition. Thereafter, the wafer 20 is divided vertically and horizontally, and a large number of semiconductor elements as shown in FIG. 1 are formed.

According to such an embodiment, the following effects can be obtained.

(1) In the J-FET of the present invention, since the SSO-rich film is provided between the gate region and the source and drain regions on the substrate side, the pn capacitance in this portion can be eliminated.

(2) According to (1) above, in the J-FET of the present invention, the gate region, source region, and drain region on the substrate side have pn
Since no capacitance is generated, input capacitance and feedback capacitance are reduced, resulting in the effect that a reduction in noise figure can be achieved.

(3) In manufacturing the J-FET of the present invention, after an insulating film is partially provided on the main surface of the substrate, an n-type layer is formed by epitaxial growth and formation of a polysilicon film, and then this n-type layer is Since the J-FET is manufactured by forming the gate region, source region, and drain region, the reproducibility is good (
The effect that J-FET can be manufactured is obtained.

(4) According to the above (1) to (3), according to the present invention, a synergistic effect is obtained in that a low-noise J-FET can be manufactured at low cost.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. In the above description, the invention made by the present inventor is mainly applied to the manufacturing technology of junction field effect transistors, which is the background field of application of the invention, but the invention is not limited thereto.

The present invention can also be applied to an IC incorporating at least a junction field effect transistor.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

In the junction field effect transistor of the present invention, input capacitance and feedback capacitance can be reduced by providing an insulating film in a portion of the junction between the channel portion and the substrate gate portion that does not contribute to mutual conductance. A reduction in noise figure can be achieved.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a sectional view showing the main parts of a semiconductor element constituting a J-FET according to an embodiment of the present invention, FIG. 2 is a schematic plan view of the same, and FIG. 3 is a diagram of the present invention. Figure 4 is the same (cross-sectional view of the wafer showing the insulating film formed state), Figure 5 is the same (the cross-sectional view of the wafer showing the state where photoresist is selectively formed, Figure 6 is the same (a cross-sectional view of the wafer showing a state in which a portion of the insulating film is removed, Figure 7 is a cross-sectional view of the wafer showing a state in which an epitaxial layer is selectively formed on the main surface), and Figure 8 is the same ( A cross-sectional view of a wafer showing a state in which a polysilicon film is formed on the main surface, FIG. 9 is a cross-sectional view of a wafer showing a state in which a photoresist film is also selectively formed, and FIG. FIG. 11 is a cross-sectional view of the wafer showing the removed state. FIG. 12 is a cross-sectional view of the wafer with J-FETs formed. FIG. 13 is the conventional J-FET. - It is a sectional view showing the principal part of the semiconductor element in which the FET was formed. 1... Substrate, 2... Epitaxial layer, 3... Isolation region, 4... Island, 5... Gate region , 6... Source region, 7... Drain region, 8... Insulating film, 9... Source electrode, 10... Drain electrode, 11... Gate electrode, 12... Channel portion, 15... Insulating film, 16... Insulating film, 17...
- Wire bonding bat, 18... Wire bonding butt, 20... Wafer, 21... Photoresist film, 22... Hollow, 23... Hollow, 24...
Insulating film, 25... Photoresist film, 30... Polysilicon layer, 31... Photoresist film. Figure 1 Figure 2 Figure 5 Figure 6 Figure 12.13-L11! Green butterfly 22.23→1

Claims (1)

[Claims] 1. A semiconductor substrate of a first conductivity type, a channel part of a second conductivity type formed on the main surface of this substrate, and a first conductivity formed in a surface layer part of the channel part and electrically connected to the substrate. A semiconductor element comprising a gate region of a type, and a source/drain region of a second conductivity type provided on a surface layer of the channel portion and sandwiching the gate region, the semiconductor device comprising: 1. A semiconductor device, characterized in that an insulating film that does not form a capacitance is provided in a region facing the source region and the drain region at an interface with the source region and the drain region.