JPH02240895A - Small size semiconductor memory - Google Patents
Small size semiconductor memoryInfo
- Publication number
- JPH02240895A JPH02240895A JP1060961A JP6096189A JPH02240895A JP H02240895 A JPH02240895 A JP H02240895A JP 1060961 A JP1060961 A JP 1060961A JP 6096189 A JP6096189 A JP 6096189A JP H02240895 A JPH02240895 A JP H02240895A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- secondary battery
- voltage
- magnetic disk
- power
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 11
- 230000000087 stabilizing effect Effects 0.000 abstract description 5
- 239000003990 capacitor Substances 0.000 description 9
- 230000006641 stabilisation Effects 0.000 description 9
- 238000011105 stabilization Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 6
- 230000002265 prevention Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000001514 detection method Methods 0.000 description 2
- 238000007599 discharging Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 238000009499 grossing Methods 0.000 description 2
- 230000007257 malfunction Effects 0.000 description 2
- 230000005856 abnormality Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 238000003079 width control Methods 0.000 description 1
Landscapes
- Dram (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、ｎ倍電圧回路を用いてデータの不揮発性化機
構を実現するバラアップ電源回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a variable-up power supply circuit that implements a data non-volatility mechanism using an n-fold voltage circuit.
従来の装置は、特開昭６３−１４３９９号公報に記載の
ように、リコール時にワード線を全選択としてビット線
に所定の電位を与えＳＲＡＭセルのフリップフロップを
リセットし、ＳＲＡＭのフリップフロップのノードを所
定の状態にリセットすることにより、リコールの簡単、
確実化を図っていた。As described in Japanese Unexamined Patent Application Publication No. 14399/1983, the conventional device resets the flip-flop of the SRAM cell by fully selecting the word line and applying a predetermined potential to the bit line at the time of recall. Easy recall by resetting the
I was trying to make sure.
上記従来技術は、受電がＤＣ入力の場合についての配慮
がなされておらず、従来技術が利用出来ない問題があっ
た。The above-mentioned conventional technology does not take into consideration the case where the power reception is DC input, and there is a problem that the conventional technology cannot be used.
本発明は、受電がＤＣ入力の場合に、停電時に内ａ２次
電池からｎ倍電圧安定化回路を設けるすｔにより、メモ
リのデータを磁気ディスクに退避可能にし、データの不
揮発性化機構を実現することにある。The present invention makes it possible to save memory data to a magnetic disk by providing an n-fold voltage stabilization circuit from a secondary battery in the event of a power outage when receiving power from DC input, thereby realizing a data non-volatile mechanism. It's about doing.
（３１題を解決するための手段〕
上記目的を達成するために、ｎ倍圧安定化回路を考案し
たものである。また、電力効率を上げる為ＯＮ抵抗の小
さいＭＯＳＦＥＴ、順電圧降下の小さいダイオードを選
択したものである。また信頼性を向上させるために、負
荷変動による出力電圧を常時監視し、ＰＷＭ制御するこ
とにより、出力電圧の安定化を図ったものである。さら
に回路素子数を少なくし、経済的にしたものである。(Means for solving 31 problems) In order to achieve the above objective, an n-fold voltage stabilization circuit was devised.In addition, to increase power efficiency, MOSFETs with small ON resistance and diodes with small forward voltage drop were used. In addition, in order to improve reliability, the output voltage due to load fluctuations is constantly monitored and PWM control is performed to stabilize the output voltage.Furthermore, the number of circuit elements is reduced. This was done economically.
（作用）
ｎ倍電圧安定化回路は、停電時に内蔵２次電池に切替え
た時のみ動作するものであり、停電時でない時には影響
を及ぼさない。(Function) The n-fold voltage stabilization circuit operates only when switching to the built-in secondary battery during a power outage, and has no effect when there is no power outage.
また、ｎ倍電圧安定化回路は、基本的には。Also, the n-fold voltage stabilization circuit is basically.
ＭＯＳ−ＦＥＴのソース・ドレイン間ドロップ分及び逆
流防止用ダイオードの順方向電圧ドロップ分のロスしか
発生しない為、素子の選択によっては、かなり電力効率
の良いｎ倍電圧安定化回路を実現出来る。また、ＭＯＳ
−ＦＥＴの０Ｎ１０ＦＦ信号の時間を変化させる事によ
り、電力効率を向上させる事も可能である。また、内蔵
２次電池の寿命もしくは、誤動作がない限り、本ｎ倍電
圧安定化回路が誤動作する事はない。Since only the loss caused by the drop between the source and drain of the MOS-FET and the forward voltage drop of the reverse current prevention diode occurs, depending on the selection of elements, it is possible to realize an n-fold voltage stabilizing circuit with considerably high power efficiency. Also, MOS
- It is also possible to improve power efficiency by changing the time of the 0N10FF signal of the FET. Furthermore, unless the built-in secondary battery has a lifespan or malfunctions, this n-fold voltage stabilization circuit will not malfunction.
【実施例〕
以下、本発明の一実施例を第１図、第２図、第３図を用
いて説明する。第１図は、小型半導体記憶装置の全体構
成図を示す、ＤＲＡＭチップを内蔵したメモリ部と上位
装ｆｉ（ＣＰＵ）及び磁気ディスク装置との信号のやり
とりを行なうコントロール部で構成した小型半導体ファ
イルとメモリ部のデータを退避（アンロード）したり、
データをメモリ部に復元（ロード）させるための磁気デ
ィスク装置と停電時に電源供給を行なう二次電池を内蔵
した不揮発性化機構１で構成できる。また通常の電源供
給は上位装置から不揮発性化機構を経由して、該小型半
導体ファイル及び該磁気ディスクを駆動するＤＣ入力（
＋５Ｖ、＋１２Ｖ）が供給される。[Embodiment] An embodiment of the present invention will be described below with reference to FIGS. 1, 2, and 3. Figure 1 shows an overall configuration diagram of a small semiconductor storage device, which is composed of a memory section containing a DRAM chip, a control section that exchanges signals with the host system FI (CPU), and a magnetic disk device. Save (unload) data in memory,
It can be configured with a non-volatile mechanism 1 that includes a magnetic disk device for restoring (loading) data into a memory section and a secondary battery for supplying power during a power outage. In addition, normal power is supplied from the host device via the non-volatile mechanism to the DC input that drives the small semiconductor file and the magnetic disk.
+5V, +12V) are supplied.
第２図は、該不揮発性化機構１の機能ブロック図を示す
、該不揮発性化機構１は基本的には、内／１１２次電池
、充電回路、２次電池切換回路、異常検出回路及び今回
考案したｎ倍電圧安定化回路２で構成出来る。上位装置
から小型半導体ファイル及び磁気ディスク駆動用ＤＣｔ
源（＋５Ｖ、＋１２ｖ）が供給される０通常の電源供給
方法は、該上位装置からのＤＣ入力（＋５Ｖ、＋１２Ｖ
）を該不揮発性化機構１をスルーで通り供給する。FIG. 2 shows a functional block diagram of the non-volatile mechanism 1. The non-volatile mechanism 1 basically consists of an internal/112 rechargeable battery, a charging circuit, a secondary battery switching circuit, an abnormality detection circuit, and It can be configured with the n-fold voltage stabilization circuit 2 that we have devised. DCt for small semiconductor file and magnetic disk drive from host device
The normal power supply method is to use DC input (+5V, +12V) from the host device.
) is supplied through the non-volatileization mechanism 1.
該内ｆｉ２次電池は、通常時は、＋１２Ｖ電源を用いて
、充電回路から充電電流を流しトリクル充電を実施する
。停電時は、該小型半導体ファイルに停電検出信号を送
出すると共に、入力切替回路にて、内蔵２次電池に切替
え、該内Ｉａ２次電池から２次電池切替回路を通って該
小型半導体ファイル及び該磁気ディスク装置に電源を供
給する。ここで問題となるのは、ＤＣ入力電源の最大値
が＋１２■であり、該内蔵２次電池には常時トリクル充
電を行なう必要があり、該内蔵２次電池の電圧は＋１２
ｖより小さくせざるを得ない、したがって停電時は、該
内蔵２次電池電圧から＋１２Ｖ電源回路を作る必要があ
る。Normally, the inner fi secondary battery performs trickle charging by flowing a charging current from a charging circuit using a +12V power supply. In the event of a power outage, a power outage detection signal is sent to the small semiconductor file, and the input switching circuit switches to the built-in secondary battery, from which the Ia secondary battery passes through the secondary battery switching circuit to the small semiconductor file and the Supplies power to the magnetic disk device. The problem here is that the maximum value of the DC input power supply is +12■, and the built-in secondary battery must be constantly trickle charged, and the voltage of the built-in secondary battery is +12
Therefore, in the event of a power outage, it is necessary to create a +12V power supply circuit from the built-in secondary battery voltage.
第３図に今回問題点を解決する手段として考案したｎ倍
電圧安定化回路を示す。基本的には。Figure 3 shows an n-fold voltage stabilization circuit devised as a means to solve this problem. Basically.
ＯＮ抵抗の小さいＰチャネルＭＯ８ＦＥＴＱＩ。P-channel MO8FETQI with low ON resistance.
ＮチャネルＭＯ８ＦＥＴＱ２．パスコン・充放電平滑用
キャパシタ０１〜Ｃ３，キャパシタ放電用ブリーダ抵抗
Ｒ１，Ｒ２，逆流防止用ダイオードＤＩ、Ｄ２及び発振
回路を内蔵し、ＲＷＭ （パルス幅制御）制御可能なコ
ントロールＩＣ１と、外部外付は抵抗Ｒ３〜ＲＩＯ及び
キャパシタＣ４で構成出来る。N-channel MO8FETQ2. Built-in bypass capacitor/charging/discharging smoothing capacitors 01 to C3, bleeder resistors R1 and R2 for capacitor discharge, backflow prevention diodes DI and D2, and an oscillation circuit, control IC1 that can control RWM (pulse width control), and external can be composed of resistors R3 to RIO and capacitor C4.
原理的には、Ｑｌ、Ｑ２のＭＯＳＦＥＴをある周期のく
り返しパルスで０Ｎ１０ＦＦさせ、Ｑ２ＯＮ時のキャパ
シタＣ２充電電圧分と（Ｖ Ｉ ＋１−Ｑ１ソース・ド
レインドロップ）を加算し、キャパシタＣ３で平滑化し
、リップル電圧を小さくして、ＶＯＬＩＴを得る回路で
あるｍ ＶｏｔｅＴは計算式■で導ける。In principle, MOSFETs Ql and Q2 are turned 0N10FF with repeated pulses of a certain period, and the charging voltage of capacitor C2 when Q2 is turned on is added to (V I +1 - Q1 source/drain drop), and the result is smoothed by capacitor C3. mVoteT, which is a circuit that reduces the ripple voltage and obtains VOLIT, can be derived from formula (2).
ＶＯｇｙ＝２ＶＢ＝ＩＤｔ ｙ ｔ Ｖａｔ Ｌｘ
Ｙ ＊ Ｖｏｆｆｉ −■ＩＤＩはＱ１ドレイン
電流、γ【はＱＩ ＯＮ抵抗。VOgy=2VB=IDt y t Vat Lx
Y * Voffi - ■IDI is Q1 drain current, γ[ is QI ON resistance.
Ｖ Ｄ ｌはＤｌ順方向電圧？ＩＤｌはＱ２ドレイン電
流。Is V D l the Dl forward voltage? IDl is Q2 drain current.
γ、は、Ｑ２ＯＮ抵抗、ＶＤ！は、Ｄ２順方向電圧を示
す。γ is the Q2ON resistance, VD! indicates the D2 forward voltage.
さらに、負荷電流の変動によるＶ。ＵＴの変動を抑え安
定化する手段として、Ｖｏｏアの出力電圧を監視し、基
準電圧と比較し、Ｑｌ、Ｑ２の０Ｎ１０ＦＦ時間を変化
させるＰＷＭ制御を実施し、出力電圧ＶｏｕＴを常に一
定にする安定化回路を設けた。また第３図は、ｎ倍電圧
安定化回路の基本構成であり、ＭＯＳＦＥＴ、充放電用
キャパシタ、逆流防止ダイオードを多段結合する事によ
り、バリエーションは増加する。また、ＭＯＳＦＥＴの
ＯＮ抵抗の選択及びダイオードの個数に応じて出力電圧
のバリエーションも増加する。Additionally, V due to variations in load current. As a means of suppressing and stabilizing the fluctuations of UT, we monitor the output voltage of VooA, compare it with the reference voltage, and implement PWM control that changes the 0N10FF time of Ql and Q2 to stabilize the output voltage Vout at all times. A conversion circuit was installed. Further, FIG. 3 shows the basic configuration of an n-fold voltage stabilizing circuit, and its variations can be increased by connecting MOSFETs, charging/discharging capacitors, and backflow prevention diodes in multiple stages. Furthermore, variations in output voltage also increase depending on the selection of the ON resistance of the MOSFET and the number of diodes.
（発明の効果〕
本発明によれば、停電時に該内蔵２次電池から磁気ディ
スク装置を駆動出来るＤＣ電源を供給する事が出来、該
小型半導体ファイルのメモリデータを該磁気ディスク装
置に退避させる不揮発性化機構を実現出来る効果がある
。(Effects of the Invention) According to the present invention, DC power that can drive the magnetic disk device can be supplied from the built-in secondary battery during a power outage, and a non-volatile DC power source that can save memory data of the small semiconductor file to the magnetic disk device can be provided. It has the effect of realizing the sexualization mechanism.
また、本機能は、簡単な回路及び素子数で電力効率を７
５％以上とれる面からも性能的にも経済的にも効果があ
る。In addition, this function improves power efficiency by 7 points with a simple circuit and number of elements.
It is effective both in terms of performance and economy since it can be taken at 5% or more.
第１図は本発明の一実施例の小型半導体記憶装置の全体
構成図、第２図は第１図の不揮発性化機構の機能ブロッ
ク図、第３図は第２図のｎ倍電圧安定化回路の基本回路
図である。
１・・・不揮発性化機構、２・・・ｎ倍圧安定化回路。
３・・・ＰチャネルＭＯ８ＦＥＴ、４・・・Ｎチャネル
ＭＯ８ＦＥＴ、５・・・充放電キャパシタ、６・・・逆
流防止ダイオード、７・・・平滑キャパシタ、８・・発
振器内蔵ＰＷＭ制御ＩＣ，９・・・くり返しパルス信号
。
躬 １ のFig. 1 is an overall configuration diagram of a small semiconductor memory device according to an embodiment of the present invention, Fig. 2 is a functional block diagram of the non-volatility mechanism shown in Fig. 1, and Fig. 3 is an n-fold voltage stabilization diagram of Fig. 2. It is a basic circuit diagram of a circuit. 1...Non-volatile mechanism, 2...N double pressure stabilization circuit. 3... P channel MO8FET, 4... N channel MO8FET, 5... Charge/discharge capacitor, 6... Backflow prevention diode, 7... Smoothing capacitor, 8... PWM control IC with built-in oscillator, 9... ...Repeated pulse signal. 1 of 1
Claims (1)
ら成る小型半導体ファイル装置とデータ退避用の磁気デ
ィスク装置及び停電時のデータ不揮発性化機構を内蔵し
た小型半導体記憶装置において、停電時の該小型半導体
ファイル装置と該磁気ディスク装置への電源供給手段と
して、二次電池と電池切替回路より成る不揮発性化機構
にｎ倍電圧回路を具備し、不揮発性化機構を実現可能に
したことを特徴とする小型半導体記憶装置。1. In a small semiconductor storage device consisting of a memory section and a control section using DRAM, a magnetic disk device for saving data, and a built-in data non-volatility mechanism in the event of a power outage, the small semiconductor file in the event of a power outage As a power supply means for the device and the magnetic disk device, a non-volatility mechanism consisting of a secondary battery and a battery switching circuit is equipped with an n-fold voltage circuit, thereby making it possible to realize a non-volatility mechanism. Semiconductor storage device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1060961A JPH02240895A (en) | 1989-03-15 | 1989-03-15 | Small size semiconductor memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1060961A JPH02240895A (en) | 1989-03-15 | 1989-03-15 | Small size semiconductor memory |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02240895A true JPH02240895A (en) | 1990-09-25 |
Family
ID=13157513
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1060961A Pending JPH02240895A (en) | 1989-03-15 | 1989-03-15 | Small size semiconductor memory |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02240895A (en) |
-
1989
- 1989-03-15 JP JP1060961A patent/JPH02240895A/en active Pending
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