JPH02240583A - Circuit margin measuring method for data discriminating circuit - Google Patents

Abstract

PURPOSE:To discriminate whether or not an error by varying separately two pulse intervals of a test pulse train of a repeated pattern by which a demodulation output becomes all '0' or '1', and the time shift quantity, and monitoring the demodulation output. CONSTITUTION:A test pulse train generating circuit 3a outputs a pulse train obtained by shifting two pieces of pulses A, B of a pulse interval Tab by respective shift quantities Ta, Tb. The test pulse train is demodulated by a demodulating circuit 25 through a data discriminating circuit 24, and the result of error detection of an error detecting circuit of a demodulation output + DECDT is stored in the corresponding column of a memory MM of a processor MPU. The processor MPU checks whether the time shift quantities Tb and Ta exceed the upper limit or not, and operates the time shift quantity and the interval Tab of the shift pulse, when they exceed the upper limit. Subsequently, the processor MPU checks whether the shift pulse interval Tab exceeds the upper limit or not. In such a manner, Tab=1 in which one pulse is interposed between the shift pulses A and B is set, Ta is determined, Tb is swung to '0'-(n), and similarly, Ta is swung to '0'-(n), and the result of an error is obtained.

Description

[Detailed description of the invention] [Table of contents] Overview Industrial field of application Prior art (Figure 9) Means for solving the Lm problem to be solved by the invention (Figure 1) Example of operation (Measurement) Explanation of the device (Figs. 2 to 6) Φ) Explanation of the measurement method (Figs. 7 and 8) (b) Explanation of other embodiments Effects of the invention [Summary] Data used in magnetic disk drives, etc. Regarding the circuit margin measurement method for measuring the operating limit of a discriminator circuit, the purpose of this study is to also measure the dynamic characteristics of fFJ, and a data discriminator circuit that discriminates the data of an input signal using the output of a phase-locked circuit that synchronizes with the input signal is used. In a circuit margin measuring method for a data discrimination circuit, the measuring means measures the operating limit of the data discrimination circuit by inputting a test pulse train and monitoring the demodulation output of a demodulation circuit that demodulates the discrimination button of the data discrimination circuit. Input a test pulse train with a repeating pattern in which the demodulated output is all "0" or "l", select two pulses from the test pulse train, and calculate the pulse interval of the two pulses and the time of each individual pulse. The demodulated output is monitored by changing the shift amounts individually.

[Industrial application field]

The present invention relates to a circuit margin measuring method for measuring the operating limit of a data discrimination circuit used in a magnetic disk drive or the like.

In a reproduction system of a magnetic disk drive, a data discrimination circuit is used to separate a read pulse from a read signal.

Such data discrimination is performed by the output of a phase-locked circuit that is phase-synchronized with the input read signal, so it is necessary to measure the tracking limit of the phase-locked circuit in order to understand the performance.

[Conventional technology]

FIG. 9 is an explanatory diagram of the prior art.

In a magnetic disk device, for magnetic, 2nd and 1st,
A recording/reproducing circuit 2 is provided.

Recording is performed by modulating the write data in the modulation circuit 21 and driving the magnetic head l through the write driver 20.

On the other hand, for reproduction, the read signal of the magnetic head l is amplified by the read amplifier 22, then converted into a pulse by the peak detector 23, the read pulse is manually inputted to the data discrimination circuit 24, noise etc. are removed, and the demodulation circuit 25 demodulates the read signal. output the read data.

The data discrimination circuit 24 includes a phase synchronization circuit (referred to as a VFO circuit) 24a and a data separation circuit 24b.The VFO circuit 24a creates a read clock that is phase-synchronized with the input signal, and the data separation circuit 24b is generated using the read clock. Operate to separate data from input read pulses.

The VFO circuit 24a includes a phase comparator 240 that performs a phase comparison between an input signal and an output read clock, and a phase comparator 24.
A charge pump 241 that integrates a phase difference of 0, and a loop filter 2 that limits the band of the output of the charge pump 241.
42, and a VCO (voltage controlled oscillator) 24 that generates a clock with a frequency according to the voltage output of the loop filter 242.
It is composed of 3.

To measure the margin of the data discriminating circuit 24, a method is adopted in which test data (test pulse train) is injected from the measuring device 3 into the data discriminating circuit 24 and demodulation error is monitored.

Conventionally, two methods have been known as methods for measuring this margin.

The first method is "l"0" as shown in FIG. 8(B).
, the generation time of a specific pulse P in the test data of a simple repeating pattern is shifted forward or backward in time, and the demodulation data is used to monitor how far the shift must be before an error occurs. It estimates the margin.

The second method is to generate various data patterns as test data, time-shift a specific pulse P therein, and measure the limit value at which an error occurs in each data pattern.

[Problem to be solved by the invention]

However, in the first conventional method, only one specific pulse P is time-shifted, so there is a problem that only a static margin can be obtained.

Actual data has unequal pulse intervals, and it is possible that the data discrimination margin decreases with a particular data pattern, but it has not been possible to measure such pattern effects.

In addition, in the conventional second method, various data patterns are generated, so although circuit margins including pattern effects can be measured, a data comparison circuit between the injected test pattern and the demodulated data is required. , a problem has arisen in that the circuit configuration of the measuring instrument 3 becomes complicated.

Therefore, an object of the present invention is to provide a circuit margin measuring method for a data discrimination circuit that can easily measure dynamic characteristics.

[Means to solve the problem]

FIG. 1 is a diagram showing the principle of the present invention.

As shown in FIG. 1, the present invention inputs a test pulse train to a data discrimination circuit 24 that discriminates the data of the input signal based on the output of a phase synchronization circuit 24a that is synchronized with the input signal. Demodulation circuit 25 that demodulates the discrimination data
By monitoring the demodulated output of the data, the data discrimination circuit 2
In the circuit margin measurement method of a data discriminator circuit that measures the operating limit of ``4'', the measuring means 3 determines that all demodulated outputs are
Input a test pulse train with a repeating pattern of "0" or "1", and input the test pulse train's
, B Select two pulses A and B, and calculate the pulse interval T a b of the two pulses A and B, and the time shift of each pulse) l'
The demodulated output is monitored by changing l'-a and Tb individually.

[Effect]

First, in the present invention, since a repetitive button whose demodulated output is all "0" or "J" is used as a test pulse train, it is possible to determine whether there is an error or not without the need for data comparison of the demodulated output.

Secondly, it is possible to select two pulses to be time-shifted, and the inter-pulse MTab and time shifts lTa and Tb of the two pulses are individually changed, making it possible to measure various data patterns. It becomes possible to measure dynamic characteristics including pattern effects.

〔Example〕

(a) Description of measuring instrument FIG. 2 is an overall configuration diagram of an embodiment of the present invention.

In the figure, the same parts as shown in Figures 1 and 9 are:
Indicated by the same symbol.

3a is a test pulse train ordering circuit which, as described later in FIG.
It generates a test pulse train +RAW having a repetitive pattern of , receives demodulated data +DECDT, and outputs it to a microprocessor system 3b, which will be described later.

3b is a microprocessor system, which has a microprocessor MPU, a memory MM, and a bus BUS, and the processor MPU has parameters TCI, Te3, Te3, Te3 (Ta b), Te of the test pulse train to be generated.
3, Te3 (Ta) and Te3 (Tb) are output to the test pulse train generation circuit 3a via the bus BUS, and the memory M
M is pulse interval 'I'ab, time shift lTa, T
It stores the measurement results corresponding to b.

26 is a timing control circuit which outputs successive timing signals +RDGT indicating a valid data ifi area to the test pulse train generation circuit 3a, the data separation circuit 24b, and the demodulation circuit 25.
This is what is output to.

Figure 3 is a block diagram of the test pulse train generation circuit configured in Figure 2, Figure 4 is a block diagram of the play circuit configured in Figure 3, and Figures 5 and 6 are waveform diagrams of the main parts of the configuration in Figure 3. be.

In FIG. 2, 30 is a measurement timing generator;
The read timing signal RDGT is manually input to the first flip-flop FFI which generates the synchronous operation signal (see FIG. 5), and the VFO preparation period T from the processor MPU.
The first register R1 that stores CI and the synchronous operation signal ■
as a trigger, register R1's VFO preparation time TCI
is preset, and the first counter CTR1 generates a VFO preparation period signal (see FIG. 5) with a period of '1' CI.
, a second register R2 that stores the measurement period TC2 from the processor MPU, and a measurement period TC2 of the second register R2 using the output of the first counter CTR1 as a trigger.
is preset, and the measurement period signal ◎ (fifth
(see figure), a third register R3 that stores the end period TC3 from the processor MPU, and the output of the second counter CTR2 as a trigger, the end period TC3 of the third register is preset, the third counter CT generates a termination signal (see FIG. 5) and resets the first flip-flop FFI.
It has R3.

31 is a pulse setting unit, which includes a register R4 that stores the pulse interval TC4 (Tab) from the processor MPU;
The output ■ of the second flip-flop 1FF2, which will be described later, is used as a trigger, and the pulse interval TC4 (Ta b
) is preset, and the pulse interval signal ■(
(see FIG. 5), and a register R that stores the interval TC5 from the processor MPU.
5 and the output of the fourth counter CTR4 as a trigger,
Interval TC5 of register R5 is preset, period TC
The fifth counter CTR5, which generates the interval signal ◎ of 5 (see FIG. 5), is reset by the output -T2 of the second counter CTR2, and the output of the fifth counter CTR5 and the fourth
It operates on the output of the counter CTR4, and the pulse interval signal ■
(It has a second flip-flop FF2 that generates 1fIO in FIG. 5).

32 is a pulse train output section, into which the pulse interval signal ■ is inputted as data, and the output -T? of the second counter CTR2? A reset input is input to the third flip-flop FF3 which generates a pulse interval signal ■, a pulse interval signal ■ is input as data, and a reset input is input to the output of the second counter CTR2 -T2, which generates a pulse interval signal ■. A fourth flip-flop F generates a delayed signal (see Figure 6).
A first AND gate that performs a logical product of F4, the pulse interval signal ■ of the third flip-flop FF3, and the inverted pulse interval signal ■ of the fourth flip-flop FF4, and generates the first pulse selection signal ■. A second AND which performs a logical product of Al, the inverted pulse interval signal (■) of the third flip-flop FF3, and the pulse interval signal (■) of the fourth flip-flop FF4, and generates a second pulse selection signal (■). The gate A2, the sixth register R6 that stores the time shift amount TC6 (Ta) of the first shift pulse A from the processor MPU, and the output ■ of the first AND gate Al as a trigger. First play circuit D that generates a pulse ■ delayed by time shift amount Tc6
LY1, a seventh register R7 that stores the time shift 1-ftTc7 (Tb) of the second shift pulse B from the processor MPU, and the seventh register R7 that stores the time shift 1-ftTc7 (Tb) of the second shift pulse B from the processor MPU. time shift) ITC7 The second play circuit DLY2 that generates the delayed pulse @ takes the AND of the clock CLK of the clock generator (described later) 33 and the inverted output of both AND gates At and A2, and outputs the clock CLK. The outputs of the third AND gate A3, the first and second play circuits DLYI and DLY2, and the AND gate A3, which prohibit the output during the period of the first and second pulse selection signals, are logically summed, and the test pulse train +R is obtained.
It has an OR gate OR that outputs AWDT.

33 is a clock generator, and the clock + shown in FIG.
34 is an error detection unit that generates CLK, and a fourth AND gate A4 that outputs the output +DECDT of the demodulation circuit AlB25 (see FIG. 2) at the timing of the output ◎ of the second counter CTR2; The output of the AND gate A4 is used as the clock, and the output of the second counter CTR2◎
The fifth flip-flop FF5 generates an error output +ERR(Q) using the data as data.

Next, the play circuits DLYI and DLY2 will be explained with reference to FIG.

321 is a flip-flop circuit, which uses trigger ■ or ■ as a clock input and generates output ■;
This is a sawtooth wave generation circuit, and the flip-flop circuit 3
The sawtooth wave (■) is generated in response to the output (■) of 21.

323 is a DAC (digital/analog converter) and has a digital time shift amount Ta.

324 is a comparator that compares the sawtooth wave ■ with the analog amount ◎, and generates the lower output when ◎〉■. 325.326 is a receiver that compares It receives and outputs the output of the device 324, and generates an output pulse (2).

Therefore, in the configurations of FIGS. 3 and 4, as shown in FIGS. 5 and 6, in synchronization with the read timing signal
A circuit preparation period) TCI is taken, and a measurement period TC2 is set by a second counter CTR2.

The pulse setting section 31 generates three pulse interval signals (2) and [F] during the measurement period TC2.

Furthermore, the pulse train output section 32 creates pulse selection signals ■ and ■ that select the pulses to be shifted by the third and fourth flip-flops FF3 and FF4 and the AND gates A1 and A2, and selects the pulses between the clock pulses +CLK. In addition to cutting with AND gate A3, the time-shifted pulses are output to play circuits DLYI and D according to the time shift amount.
Generated at LY2 and inserted into clock pulse +CLK.

Therefore, the output pulse train becomes a repeated bang of "100", and in the RLL (1,7) code, it becomes all "0"' after demodulation.

In FIG. 6, time shifts 1Tc6 and Te3 from the rear end of the previous clock are set, and time shifts l-1T
The pulse A of c6 is earlier than the original pulse position (Earl
y), the pulse B of the time shift amount TC7 is later than the original pulse position.

(b) Explanation of measurement method FIG. 7 is a processing flow diagram of an embodiment of the present invention.

■ The processor MPU determines the pulse interval Ta of the shift pulse.
Set b to the initial value "1".

At this time, fixed parameters TCI to TC3 and Te3 are set in advance in the first to third registers R1 to R3 and the fifth register R5.

■ Next, the processor MPU generates the first shift pulse A.
Time shift I T a 'l: Initial 4M r O3
Set to .

■Furthermore, the processor MPU generates a second shift pulse B.
Set the time shift 1lTb to the initial 4M' OJ.

■ Furthermore, the processor MPU sets Tab, Ta, and Tb to registers R4, R6, and R of the test pulse train generation circuit 3a.
7 via the bus BUS.

Then, the test pulse train generation circuit 3a outputs a pulse train obtained by shifting two pulses A and B with a pulse interval Tab by shift amounts Ta and Tb, respectively, as explained in FIGS. 5 and 6.

In the example shown in FIG. 5, a pulse train including three shifted pulses A and three shifted pulses B is output for one set.

The test pulse train is passed through the data discrimination circuit 24 to the demodulation circuit 2.
The error detection result of the error detection circuit 34 of the demodulated output terminal ECDT is notified to the processor MPU and stored in the corresponding column of the memory MM.

Here, if there is no error, the demodulated output is all "0", and if there is an error, all the demodulated outputs are no longer "on", and the error detection result becomes "1".

(2) Then, the processor MPU updates the time shift tiTb of the second time shift pulse B to (Tb+1).

Next, the processor MPU checks whether the time shift lTb exceeds the upper limit "n", and if it does not, returns to step (2).

■ On the other hand, if it exceeds (Ta), in order to repeat the time shift 1lTa of the first time shift pulse A,
+1).

Next, the processor MPU checks whether the time shift ITa exceeds the upper limit "m", and if it does not, returns to step (2).

■ On the other hand, if it is exceeded, then operate the interval Tab between the two shift pulses.

That is, the processor MPU determines the shift pulse interval Tab
is updated to (Tab+1).

Next, the processor MPU checks whether the shift pulse interval Tab exceeds the upper limit "L", and if it does not exceed the upper limit, the process returns to step (2), and if it does, the process ends.

In this way, set Tab=1 with one pulse intervening between shift pulses A and B, decide Ta, and set Tb to 0-
Let it roll up to n and get an error result.

Similarly, change Ta, vary Tb from 0 to n, and execute.

The same thing is done this time with Tab=2 (two pulses are interposed between shift pulses A and B), 3, and -L.

That is, using Tab as a parameter, Ta and Tb are varied independently to examine the margin limit.

After obtaining the measurement results in this manner, a closed curve of the results is drawn in a two-dimensional graph as shown in the explanatory diagram of FIG.

That is, the vertical axis is Ta, the horizontal axis is Tb, and each pulse interval Ta
Plot the margin limit (limit where an error occurs) for each b.

In FIG. 8, the shaded area is the range where no errors occur, and the rest are areas where errors occur.

Then look at how the four corners of the graph are cut off.

If the data discrimination circuit had no pattern effect, this graph would be a square.

For example, if the upper left corner of Fig.
When a time shift occurs on the Early side (of pulse B),
It can be seen that the circuit margin is significantly reduced.

It can also be seen from the figure that the interval between two time shifts has the smallest margin when Tab=2.

In this way, dynamic characteristics including pattern effects can be easily measured.

Such a two-dimensional graph in FIG. 8 may be automatically output from the contents of the memory MM in a microprocessor system, or may be plotted and entered by a human on a graph paper etc. from the contents of the memory MM. .

(C) Description of other embodiments In the embodiment described above, the time signal is generated by a counter in FIG. .

Also, the repetition pattern in which the demodulated output is all "0" or "1" is not limited to the repetition of rloooJ, but may be other patterns (the shift pulse interval and the time shift amount are
Measurements can be made in various ranges depending on the data discrimination circuit.

Although the present invention has been described above using examples, the present invention can be modified in various ways according to the gist of the present invention, and these are not excluded from the present invention.

〔Effect of the invention〕

As explained above, according to the present invention, since a repeating pattern in which the demodulated output is all "0" or "1" is used as the test pulse train, it is possible to determine whether there is an error or not without the need for data comparison of the demodulated output. This has the effect of being able to distinguish between

In addition, it is possible to select two pulses to be time-shifted, and the pulse interval and time shift amount of the two pulses are individually varied and measured, making it possible to measure dynamic characteristics including pattern effects. It has the effect of becoming.

[Brief explanation of drawings]

Fig. 1 is a diagram of the principle of the present invention, Fig. 2 is an overall block diagram of an embodiment of the present invention, Fig. 3 is a block diagram of the test pulse train generation circuit configured in Fig. 2, and Fig. 4 is a block diagram of the test pulse train generation circuit configured in Fig. 3. A block diagram of the play circuit, FIGS. 5 and 6 are waveform diagrams of main parts of the configuration shown in FIG. 3, FIG. 7 is a processing flow diagram of an embodiment of the present invention, and FIG. 8 is a detailed explanatory diagram of the present invention. FIG. 9 is an explanatory diagram of the prior art. In the figure, 2/l--data discrimination circuit, 24a--phase synchronization circuit, 25-- demodulation circuit, measuring means.

Claims (1)

[Claims] A test pulse train is input to a data discrimination circuit (24) that discriminates the data of the input signal using the output of a phase synchronized circuit (24a) synchronized with the input signal, and the data discrimination circuit (24) discriminates the input signal. In a circuit margin measuring method for a data discriminator circuit (24), which measures the operating limit of the data discriminator circuit (24) by monitoring the demodulation output of a demodulation circuit (25) that demodulates data, the measuring means (3) detects the demodulation output. Input a test pulse train with a repeating pattern of all "0" or "1", select two pulses (A, B) of the test pulse train, and set the pulse interval (A, B) of the two pulses (A, B). 1. A circuit margin measuring method for a data discrimination circuit, characterized in that the demodulated output is monitored by individually changing the time shift amount (Ta, Tb) of each pulse.