JPH02238710A - Switch circuit - Google Patents

Abstract

PURPOSE:To ensure excellent isolation and to reduce the loss by connecting sources of output source follower FETs of a unit circuit in common and switching the FETs with ON, OFF of an amplifier circuit. CONSTITUTION:Sources of output source follower FETs 4, 6 are connected in common. Thus, with the FET 4 turned on and the FET 6 turned off for example, the source and gate of the FET 6 are reverse-biased, the source and gate capacitance of the FET 6 is decreased to suppress the leakage of the signal from the FET 4 to the FET 6 thereby taking isolation between input terminals 1, 2 and the flowing of a drain current of the FET in the ON state to the FET in the OFF state is prevented by using diodes 7, 8 connecting to the sources of the FETs 4, 6. Moreover, amplifier circuits A, B are switched by ON/OFF. Thus, excellent isolation is ensured and the transmission loss is avoided.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a switch circuit with a large power and one output. It can be suitably used in such applications where, when selectively receiving broadcast radio waves, the radio waves of one radio wave will not leak into the area where the other radio wave is being received and cause interference. This relates to switch circuits.

[Conventional technology]

FIG. 14 is an explanatory diagram showing a satellite broadcast community reception system as an application example of the switch circuit to which the present invention is applied.

In the same figure, ANTI and 2 are the antenna and CH, respectively.
I, 2 are signal paths, SWI, 2 are switch circuits, and TVI, 2 are television receivers.

TV reception taTVI, 2 are each switch circuit SW
By switching I and 2, signals arriving from either antenna can be received.

Now, on the TV receiver TVIO side, the switch circuit SWI is switched to the terminal a side and the signal from the antenna ANT 1 is received via the signal path CI{1, and on the other hand, on the TV receiver TV2 side, the switch circuit SW2 is It is assumed that the antenna ANT2 is switched to the terminal b side and a signal from the antenna ANT2 is received via the signal path CH2.

At this time, if in the switch circuit SWI, the isolation between terminals a and b is poor and the signal input to the switch circuit SWI via the signal path CHI leaks to the terminal b side, this leakage signal is shown as a broken line. The signal from the antenna ANT2 is routed through the signal path CH2 to the television receiver TV2, which receives the signal from the antenna ANT2 and the antenna A.
This results in interference reception of signals from the NTI, resulting in an undesirable situation.

As a conventional example of the above-mentioned signal switching switch circuit using a field effect transistor FET, there is a known one described in Japanese Patent Application Laid-Open No. 80974/1983, which changes the gate voltage of the FET. Switching was performed by changing the resistance value between the control drain and source.

[Problem to be solved by the invention]

The conventional switch circuit described above uses the drain and source of the FET as a signal transmission path, and focuses on changes in the resistance value between the drain and source and operates this as a type of variable resistor to perform switching. was.

Therefore, even when the FET is ON (switch is ON), there is a problem in that a certain resistance value exists between the drain and the source, that is, in the signal path, resulting in transmission loss. Furthermore, in order to maintain good isolation from other circuits, it is necessary to configure the switch circuit according to the above-mentioned conventional technology in multiple stages, but this increases transmission loss.
It has been difficult to both ensure isolation and reduce loss.

An object of the present invention is to provide a multi-input/l-output switch circuit that ensures good isolation and has no transmission loss.

[Means for solving assignments]

In order to achieve the above object, in the present invention, a signal input is guided to an output source follower FET via an amplifier circuit, and the FET is
Prepare as many unit circuits as the number of signal inputs that connect the source as the output side of T to a common output terminal, and determine which signal input is output to the common output terminal (that is, switching operation)
was decided by turning on and off the amplifier circuit that amplifies the signal input.

[Operation] In the present invention, since the switching operation is performed by turning the amplifier circuit on and off (ON, OFF), the input signal is amplified by the increasing circuit of the unit circuit and output, and no transmission loss occurs.

Furthermore, by making the sources of the output source follower FETs of the unit circuits common, the source voltage of the FET in the ON state reverse biases the source and gate of the other FETs in the OFF state. Since the inter-input capacitance becomes very small, good isolation between inputs can be maintained.

〔Example〕

FIG. 1 is a circuit diagram showing a first embodiment of the present invention. The configuration of this embodiment is as follows.

That is, the input terminal 1 is connected to the input terminal of the amplifier circuit A, the output terminal of the amplifier circuit A is connected to the gate G of the FET 4, the power supply terminal of the amplifier circuit 8 is made common to the drain D of the FET 4, and the voltage control is performed. The anode of the diode 7 is connected to the source S of the FET 4, the input terminal 2 is connected to the input terminal of the amplifier circuit B, the output terminal of the amplifier circuit B is connected to the gate G of the FET 6, and the amplifier circuit The power supply terminal of B and the drain D of FET6 are made common, and connected to the voltage control terminal 5, and a diode 8 is connected to the source of FET6.
The anodes of the diodes 7 and 8 are connected together, and the cathodes of the diodes 7 and 8 are connected to the output terminal 9, and the hole terminal 9 is grounded via the current source 49. Next, the operation will be explained. The signals input from input terminals 1 and 2 are applied to voltage control terminals 3 and 5 at low voltage levels. It is selected by the high combination and is output from the output terminal 9.

Now, if we apply a high level voltage to 1t oppressed IB4 child 3 and a low level voltage to 5, the signal input from terminal 1 will be O.
The FET is amplified by the amplifier circuit A and turned on.
It is output from terminal 9 via 4. On the other hand, the signal input from terminal 2 is transmitted through amplifier circuit B and FET 6, which are turned off.
is sufficiently attenuated and does not affect the output.

Furthermore, the source-gate of FET 6 which is turned OFF and the diode 8 are reverse biased by the source voltage of FET 4 which is turned ON, and the capacitance between the source and gate of FET 6 becomes smaller, causing the signal input from terminal 1 to leak to terminal 2. prevent.

Conversely, if a low level voltage is applied to terminal 3 and a high level voltage is applied to terminal 5, only the signal input from terminal 2 will be output to terminal 9 based on the same principle as above, and FET 4 will be turned off.
between the source and gate of , and the diode 7 is turned on
It is reverse biased by the source voltage of ET6 to prevent the signal input from terminal 2 from leaking to terminal 1.

In addition, one of the FETs 4 and 6 is turned ON and the other is turned OFF by switching the input, but the drain-source current in the ON state flows to the current source 49 via the diode connected in the forward direction, but the other By means of a diode connected with opposite polarity to the source of the OFF state FET,
There is no leakage to the OFF side circuit.

The feature of this embodiment is that each source of the output source follower FETs 4 and 6 is made common, so that FET 4 is turned on and off.
When ETi<OFF(7), the source and gate of FET6 is reverse biased, the capacitance between the source and gate of FET6 becomes small, and signal leakage from the FET4 side to the FET6 side is suppressed (when FET4 is OFF and FET6 is ON, (the opposite), sufficient isolation can be taken between the input terminals 1 and 2, and the diodes 7.8 connected to the sources of each FET 4 and 6 allow the FETs in the OFF state to be turned ON.
This prevents the drain current of the current FET from flowing into the O
This is done to prevent any negative effects on the circuits in the FF state. Furthermore, since switching is performed by turning the amplifier circuit ON and OFF, it has the characteristic that no transmission loss occurs.

As an application example of this embodiment, as already explained with reference to FIG. etc. are possible.

FIG. 2 shows a second embodiment of the invention. In this embodiment, in the first embodiment, the drain D of FET 4 is connected to voltage control terminal 3, and the drain D of FET 6 is connected to voltage control terminal 5.
Instead of connecting the drains D of FETs 4 and 6 to the power supply voltage terminal 41,
The sources of the ETs 4 and 6 are directly shared without connecting diodes, and are connected to the output terminal 9.

The operation of this embodiment will be explained below. Input/output and input switching are performed in the same manner as in the first embodiment. The applied voltage level to the terminal 41 is kept high regardless of input switching. Currently, each of my children is 3.5 high. When a low voltage is applied, a signal input from terminal 1 is amplified by amplifier circuit A, which is turned on, and output from terminal 9 via FET 4, which is turned on. Further, since the signal inputted from the terminal 2 is sufficiently attenuated by the amplifier circuit B and the FET 6 which are turned off, it does not affect the output. At this time, FET
The source and gate of FET 6 are reverse biased by the source voltage of FET 4 which is ONL, and at the same time the drain and gate of FET 6 are reverse biased by the voltage applied to terminal 41. - The inter-gate capacitance is reduced, and signal leakage from the FET4 side to the FET6 side is suppressed (the opposite is true when terminal 3 is low and terminal 5 is high).

The feature of this embodiment is that the drains of the output source followers 4 and 6 are made common, and the voltage level applied to the terminal 41 connected thereto is always kept high regardless of input switching. A reverse bias is applied between the drain and gate, and the output source followers 4 and 6 are
By making each source common, the FE in the OFF state
Since the source of T is reverse biased by the source voltage of the FET in the ON state, sufficient isolation is maintained between the input terminals and no transmission loss occurs.

FIG. 3 shows a third embodiment of the present invention. In this embodiment, in the first embodiment, the drain of the FE74 is connected to the terminal 3,
Instead of connecting the drain of FET6 to terminal 5,
The drain of T4 is connected to terminal 3 via diode 42, the drain of FET 6 is connected to terminal 5 via diode 43, and each source of FET 4.6 is made common without connecting a diode. It is configured to be connected to terminal 9.

Next, the operation of this embodiment will be explained. Input/output and input switching are performed in the same manner as in the first embodiment.

The voltage level currently applied to the voltage control terminal is set to terminal 3, which is high. When terminal 5 is set to low, the signal input from terminal 1 is amplified by the amplifier circuit A in the ON state, and the signal input from the terminal 1 is amplified by the amplifier circuit A in the ON state.
It is output to terminal 9 via ET4. At this time, OFF
There is an ON state FET between the source and gate of FE76.
FET6 is reverse biased by the source voltage of FET6.
The source-to-gate capacitance of FET 4 is reduced, and signal leakage from the FET 4 side to the FET 6 side is suppressed. Further, due to the diode 43, the drain-source current of the FET 4 in the ON state flows to the current source 49 without leaking to the terminal 5.

The signal input from terminal 2 is sufficiently attenuated by amplifier circuit B and FET 6 which are turned off, and does not affect the output. Terminal 3 is low. The opposite is true when terminal 5 is high.

The feature of this embodiment is that the switching operation is performed by turning the amplifier circuit ON and OFF, so that the input signal is ON and OFF.
The output source follower FET 4.6 has a common source, and the source and gate of the FET in the OFF state are reverse biased by the source voltage of the FET in the ON state. By doing so, it is possible to maintain sufficient isolation between the input terminals. FIG. 4 shows a fourth embodiment of the present invention. This example is the third
In the switch circuit shown as an example, FET4
and 6 are configured to share the drains. The operation of this embodiment is such that a high voltage level is applied to the common drains of FETs 4 and 6 regardless of whether the voltage level applied to the terminal 3.5 is high or low, or low or high. Therefore, the operation is similar to that of the switch circuit shown as the second embodiment.

Furthermore, as explained in the second embodiment, the present embodiment is characterized in that no transmission loss occurs and that sufficient isolation between input terminals can be maintained.

FIG. 5 shows a fifth embodiment of the present invention. In this embodiment, the amplifier circuit in the switch circuit shown in the first embodiment is F.
This is an example configured with ET. Since the basic configuration is the same as that of the first embodiment, the circuit configuration of the amplifier circuit, its operation, and characteristics will be explained below.

The input terminal of amplifier circuit A (B) is a gate-grounded amplifier FE.
Source of TIO (13) and FETIO (13)
Resistor 11 (14) and inductor 12 (15) are connected to the source of
The drain of FETIO (13) is connected to the gate of source follower 25 (30), and FET2
The source of FET 35 (30) is connected to the gate of gate input amplification FET 35 (38) via diode 26 (31), and also connected to the drain of FET 27 (32), and the source of FET 35 (38) is connected to resistor 36 (39).
), the gate of FET27 (32) is grounded, and the source of FET27 (32) is connected to resistor 28 (33
), the drain of FETIO (13) is connected to the source of FET16 (18) via resistor 17 (19), and the gate of FET16 (18) is connected to resistor 21 (
23), the drain of FET16 (18) is connected to terminal 3 (5), the gate of FE116 (1B) is grounded to terminal 3 (5) via resistor 20 (22),
Connect the drain of FET25 (30) to diode 24 (2
9) to terminal 3 (5), and FET25 (3
0) is connected to FET3 through resistor 34 (37).
5 (38), and this connection point is used as the output of the amplifier circuit.

Next, the operation of the amplifier circuit will be explained. Now, if the applied voltage level at terminal 3 is high and that at terminal 5 is low, then terminal l
The signal input from the FETIO is amplified by the FETIO and output to its drain. At this time, since the FET 16 acting as a load on the drain of the FETIO appears as a negative resistance at a certain frequency, the frequency characteristic of the gain of the FETIO becomes such that a peak occurs near the frequency where the FET 16 appears as a negative resistance. The signal passing through FETIO is input to the gate of FET 35 via source follower FET 25 and diode 26, is amplified by FET 35, and reaches FET 4. Also, the drain voltage of FETIO (13) is FETIO6 (18), resistors 17, 2
Since it is determined by a constant voltage source consisting of 0.21 (19.22.23), fluctuations due to variations in constants of each element are small. FET27 (32) and resistor 28 (3
3) A constant current source consisting of a source follower FET25 (
30) to stabilize the operation.

The feature of this embodiment is that by setting the peaking characteristic of the FETIO so as to correct the frequency characteristic of the amplification FET 35, the frequency characteristic of the switch circuit becomes flat up to high frequencies, so that it can be used in a high frequency band. It's right there. This is suitable for use, for example, as an input switching switch in the input section of a satellite broadcasting receiver.

Furthermore, when converting the switch circuit in this embodiment into an IC, the circuit excluding loads 11, 12, 14, 15, resistor 40, and terminal 9 is configured inside the IC (therefore, the cathodes of diodes 7 and 8 are connected to the outside of the IC). It is possible to correct the gains of FETIO and 13 by appropriately selecting the constants of loads 11, 12 and 14.15. Also, in the case of resistor 40, FET
It becomes possible to correct the characteristics of Nos. 4 and 6.

In the above IC-based switch circuit, the portion of the circuit configured in the IC that is supplied with power from the terminal 3 is connected to the l-th I
C and a two-chip configuration in which the part supplied with power from terminal 5 is the second IC, the present embodiment can be applied to either a 1-input satellite broadcast receiver or a 2-input satellite broadcast receiver, for example. When using a switch circuit, a one-input satellite broadcasting receiver includes the first IC chip and the resistor 11. The inductor 12, the terminal 9, and the resistor 40 are used as the first-stage input amplifier circuit, and the other two-input satellite broadcasting receiver has a switch circuit shown in FIG. 5 configured as a two-chip circuit using the above method. It can be used as an input switch.

To explain briefly, when used for a 1-input receiver, l
When a chip IC is used in a two-input receiver, it is sufficient to have two chips, and one type of IC chip can be used for receivers with different numbers of inputs. Therefore, this embodiment is suitable for configuring an IC-based satellite broadcasting receiver.

FIG. 6 shows a sixth embodiment of the present invention. This embodiment is an example in which the amplifier circuit constructed from the FET shown in the fifth embodiment is used as the amplifier circuit of the switch circuit shown in the second embodiment. The operation and characteristics of the amplifier circuit of this embodiment are similar to those of the fifth embodiment, and the operations and characteristics of the switch circuit are similar to those of the second embodiment.

In addition, resistors 11 and 14, inductors 12.15, terminals 41 and 9, and resistor 40 are provided outside the IC, and other parts are integrated into ICs, and among the parts that are integrated into ICs, the part that is supplied with power from terminal 3 and FET 4 are They were configured in the same IC, and this was designated as the first IC. Among the parts that were to be integrated into the IC, the part that was supplied with power from terminal 5 and the FET 6 were configured in the same IC, and this was designated as the second IC. When a two-chip configuration is adopted, as shown in the fifth embodiment, this embodiment is suitable for configuring an IC-based satellite broadcasting receiver.

FIG. 7 shows a seventh embodiment of the present invention. In this embodiment, in the amplifier circuit of the switch circuit shown in the third embodiment,
This is an example using the amplifier circuit configured by the FET shown in the fifth embodiment. The operation and characteristics of the amplifier circuit in this example are the same as those shown in the fifth example, and the operations and characteristics of the sinch circuit in this example are the same as those shown in the third example. It is.

In addition, similarly to the fifth embodiment, when the resistors 11, 14, the inductor 12.15, the terminal 9, and the resistor 40 are provided outside the IC, and the other parts are integrated into an IC, and even when integrated into two chips, It has the features shown in the fifth embodiment above.

FIG. 8 shows an eighth embodiment of the present invention. This embodiment is an example in which the amplifier circuit shown in the fifth embodiment is used as the amplifier circuit of the switch circuit shown in the fourth embodiment. The operation and characteristics of the amplifier circuit in this example are the same as those shown in the fifth example, and the operations and characteristics of the switch circuit in this example are the same as those shown in the fourth example. be.

In addition, when the switch circuit in this embodiment is integrated into an IC, the resistors 11 and 14, the inductors 12 and 15, and the terminal 9
, the resistor 40 and the common contact of the drains of the FETs 4 and 6 are provided outside the IC, and the other parts are configured inside the IC. By adopting a two-chip configuration in which the FET 4 is the first IC and the other parts are the second ICs, it has the same characteristics as the fifth embodiment.

FIG. 9 shows a ninth embodiment of the present invention. In this embodiment, the input terminal 44 is connected to the input terminal of the amplifier circuit C, the output terminal of the amplifier circuit C is connected to the gate G of the FET 46,
The drain D of the FET 46 is connected to the power supply terminal of the amplifier circuit and also to the voltage control terminal 45, and the source S of the FET 46 is connected to the anode of the diode 47 to form one unit circuit. A plurality of unit circuits are provided, and the cathode of each unit circuit is shared and connected to the output terminal 9, and the terminal 9 is connected to the current source 49.
This is a multi-input, one-output switch circuit configured to be grounded through the ground. In other words, this embodiment is an extension of the switch circuit shown in the first embodiment to a multi-input configuration.

Next, the operation of the switch circuit in this embodiment will be explained.

To select one signal from among the signals input from each input terminal and output it from terminal 9, set the voltage level applied to the voltage control terminal of the unit circuit to which the desired signal is input to high, and then This is done by setting the voltage control terminal to low.

Now considering the case where the voltage level applied to the terminal 45 is high and the other voltage control terminals are low, the signal input from the terminal 44 is amplified by the amplifier circuit C and the FET in the ON state is
46 and a diode 47 to the terminal 9. At this time, the sources and gates of the source follower FETs of other unit circuits are reverse biased by the source voltage of the FET 46 in the ON state, so the capacitance between the sources and gates becomes small, and the isolation between the terminal 44 and other input terminals decreases. As in the case of the first embodiment, the ration is maintained sufficiently.

The feature of this embodiment is that the unit circuits are integrated into ICs, the number of ICs is the same as the number of input signals, and the diode cathode of each IC is shared, so that it can be applied to circuits with any number of inputs, and each unit Only one unit circuit in the circuit is ON
Therefore, it is sufficient to provide one current source 49 regardless of the number of inputs so that the current equivalent to 71 output source followers FE always flows. Other features are similar to those of the first embodiment. FIG. 10 shows a tenth embodiment of the present invention. In this embodiment, the input terminal 44 is connected to the input terminal of the amplifier circuit C, the power supply terminal of the amplifier circuit C is connected to the voltage control terminal 45, and the output terminal of the amplifier circuit C is connected to the gate G of the output source follower FET 46. This unit circuit is made up of a plurality of unit circuits having the same circuit configuration as this unit circuit, and each source of the output source follower FET of each unit circuit is shared, connected to the output terminal 9, and further connected to the terminal 9. 9 as current source 4
9 to ground through the output source follower F of each unit circuit.
Each drain of the ET is made common and the power supply voltage terminal 4
The configuration is such that it is connected to 1.

In other words, this embodiment is an extension of the switch circuit shown in the second embodiment to a multi-input configuration.

Next, the operation of this embodiment will be explained. Input switching is as above 9th
As in the case of the above embodiment, this is done by setting the voltage control terminal of the unit circuit to which the desired signal is input to high level, and setting the other terminals to low level. Now considering the case where the terminal 45 is high and the other voltage control terminals are low, the signal input from the terminal 44 is amplified by the amplifier circuit C, and the FET 4 in the ON state is
6 and is output to terminal 9. At this time, the voltage between each source and gate of the output source follower FET of other unit circuits is O.
The output source follower FET in the OFF state is reverse biased by the source voltage of the FET 46, and is further reverse biased by the terminal 41 to which a high voltage level is always applied between the drain and gate of the output source follower FET in the OFF state. The source-gate capacitance and drain-gate capacitance of the follower FET are reduced, and sufficient isolation is maintained between the terminal 44 and other input terminals.

In this example. The feature is that, as in the case of the ninth embodiment, by converting each unit circuit into an IC, it is possible to correspond to a circuit with any number of inputs by providing the same number of ICs as the number of inputs. Unit circuit in ON state is always 1
Therefore, it is sufficient to provide one current source 49 regardless of the number of inputs so that the current equivalent to one output source follower FE7 always flows. Other features are similar to those of the second embodiment.

FIG. 11 shows an eleventh embodiment of the present invention. In this embodiment, in the unit circuit shown in the ninth embodiment, no diode is connected to the source of the output source follower FET 46, and Instead of directly connecting the gate of the voltage control terminal 45 to the voltage control terminal 45, the unit circuit is connected via a diode 48, and the source of the output source follower FET of each unit circuit is made common and connected to the terminal 9. is configured to be grounded via a current source 49. In other words, the switch circuit shown in the third embodiment is expanded to have a multi-input configuration.

Similar to the ninth and tenth embodiments, the feature of this embodiment is that each unit circuit is made into an IC, so that any circuit with any number of inputs can be equipped with the same number of ICs as the number of inputs. Furthermore, since the number of unit circuits in the ON state is always one regardless of input switching, one current source 49 is provided regardless of the number of inputs, and the output source follower FE
It would be good if the current for one T was allowed to flow at all times. Other features are similar to those of the third embodiment.

FIG. 12 shows a twelfth embodiment of the present invention. In this embodiment, the drains of the output source follower FETs of each unit circuit are made common in the eleventh embodiment. Therefore, the unit circuit in this embodiment and the unit circuit shown in the eleventh embodiment have the same circuit configuration. Further, the switch circuit in this embodiment can be said to be an extension of the switch circuit shown in the fourth embodiment to have a multi-input configuration.

The feature of this embodiment is that, as in the ninth, first and eleventh embodiments, each unit circuit is made into an IC. Furthermore, since there is always one unit circuit in the ON state, one current source 49 is provided regardless of the number of inputs, and the output source follower FE71
It would be a good idea to make the current for each individual flow at all times.
Other features are similar to those of the fourth embodiment. 1st
Figure 3 shows a thirteenth embodiment of the present invention. This embodiment is obtained by removing reactances 12 and 15 from the amplifier circuits A and B shown in the fifth embodiment. The features and operation of this embodiment are the same as those of the fifth embodiment.

In addition, the amplifier circuits in this embodiment are
When used as the amplifier circuit shown in the previous embodiments, its operation and characteristics are similar to those of the amplifier circuit shown in the fifth embodiment, and the operation and characteristics of the switch circuit are the same as those shown in each of the above embodiments. be.

〔Effect of the invention〕

According to the switch circuit of the present invention, the amplifier circuit therein is
Since switching is performed by turning N and OFF, there is an effect that no transmission loss occurs.

In addition, the output source follower FE that constitutes the switch circuit
By configuring T to apply reverse bias when it is OFF, there is an advantage that isolation characteristics between each input terminal can be improved.

[Brief explanation of drawings]

1 to 13 are circuit diagrams showing one embodiment of the present invention, and FIG. 14 is an explanatory diagram showing a joint reception system for satellite broadcasting. Explanation of symbols 1, 2. 44...Input terminal, 9...Output terminal, 3,
5, 45... Voltage control terminal, 41... Power supply voltage terminal, 7, 8, 24, 26, 29, 31, 42. 43, 47
．． 48...diode, 11, 14.17.
19, 20, 21, 22, 23, 28. 33, 34, 3
6.37, 39.40...Resistance, 12.15...Inductor, 4,6,10,13.16,18.25,2
7.30.32,35,38.46...-FET, 49
...Current source, A, B, C...Amplification circuit. Agent Patent Attorney Akio Namiki Voltage Voltage Control 3 Figures etc. 2 Figure 4 Figure 5 Figure 7 Figure 6 Figure 8 Figure @ 9 Figure H Figure 10 Figure 12 Figure 13 Zuyasu 14 figure procedural amendment June 1999

Claims (1)

[Claims] A switch circuit that selects one of the signals inputted from a first input terminal and a second input terminal and outputs the selected signal from an output terminal, the first input terminal (1) The output terminal of the first amplifier circuit is connected to the input terminal of the first amplifier circuit (A), and the output terminal of the first amplifier circuit is connected to the gate of the first field effect transistor FET (4). The drain terminal of the FET and the power supply terminal of the first amplifier circuit are shared and connected to a first voltage control terminal (3), and the source of the first field effect transistor FET is connected through a diode (7). the second input terminal (2) is connected to the input terminal of the second amplifier circuit (B), and the output terminal of the second amplifier circuit is connected to the second field effect type Connected to the gate of the transistor FET (6), and connected to the second voltage control terminal (5) by sharing the drain terminal of the second field effect transistor FET and the power supply terminal of the second amplifier circuit. , the source of the second field effect transistor FET is connected to an output terminal (9) via a diode (8), and the output terminal is connected to a constant potential via a current source (49), A signal input from either the first or second input terminal is selected based on a combination of low and high voltage levels applied to the first voltage control terminal and the second voltage control terminal, respectively. A switch circuit characterized in that a signal is output from an output terminal. 2. A switch circuit that selects either one of the signals inputted from the first and second input terminals and outputs it from the output terminal, the first input terminal (1) being connected to the first amplifier circuit ( A), the output terminal of the first amplifier circuit is connected to the gate of the first field effect transistor FET (4), and the power supply terminal of the first amplifier circuit is connected to the first voltage. Control terminal (3
), and the second input terminal (2) is connected to the second amplifier circuit (
B), the output terminal of the second amplifier circuit is connected to the gate of a second field effect transistor FET (6), and the power supply terminal of the second amplifier circuit is connected to a second voltage. The control terminal (5) is connected to the power supply voltage terminal (41) by making the drain terminal of the first field effect transistor FET (4) common to that of the second field effect transistor FET (6). and connect the source terminal of the first field effect transistor FET (4) and the second field effect transistor FET (6).
) are commonly connected to the output terminal (9) and connected to a constant potential via a current source (49), which is applied to the first voltage control terminal and the second voltage control terminal, respectively. A switch circuit characterized in that a signal inputted from one of the first and second input terminals is selected and outputted from the output terminal based on a combination of low and high voltage levels. 3. A switch circuit that selects either one of the signals inputted from the first and second input terminals and outputs it from the output terminal, the first input terminal (1) being connected to the first amplifier circuit ( A), the output terminal of the first amplifier circuit is connected to the gate of the first field effect transistor FET (4), and the drain terminal of the first field effect transistor FET is connected to the diode. (42) is shared with the power supply terminal of the first amplifier circuit and connected to the first voltage control terminal (3), and the source of the first field effect transistor FET is connected to the output terminal (9). , the second input terminal (2) is connected to the input terminal of the second amplifier circuit (B), and the output terminal of the second amplifier circuit is connected to the second field effect transistor FE.
T(6), the drain terminal of the second field effect transistor FET is shared with the power supply terminal of the second amplifier circuit via a diode (43), and a second voltage control terminal is connected to the gate of the second field effect transistor FET. (5), the source of the second field effect transistor FET is connected to the output terminal (9), and the output terminal is connected to a constant potential via a current source (49), a low voltage level applied to the first voltage control terminal and the second voltage control terminal, respectively;
A switch circuit characterized in that a signal input from either one of the first and second input terminals is selected and outputted from the output terminal based on a combination of high signals. 4. A switch circuit that selects one of the signals input from each of N input terminals (N is 2 or an integer exceeding 2) and outputs it from a common output terminal, which has one input terminal. (44) is connected to the input terminal of the amplifier circuit (C), the output terminal of the amplifier circuit is connected to the gate of the field effect transistor FET (46), and the drain terminal of the field effect transistor FET and the amplifier circuit A unit circuit is provided in which the power supply terminals of the field effect transistors are shared and connected to one voltage control terminal (45), and the source of the field effect transistor FET is connected to the common output terminal (9) via a diode (47). N pieces are provided, and the common output terminal is connected to a constant potential via a current source (49),
A signal inputted from any one of the N input terminals is selected by a combination of low and high voltage levels applied to any one of the N voltage control terminals and the other voltage control terminals. A switch circuit characterized by outputting from an output terminal. 5. A switch circuit that selects one of the signals input from each of N input terminals (N is 2 or an integer exceeding 2) and outputs it from a common output terminal, which has one input terminal. (44) is connected to the input terminal of the amplifier circuit (C), the output terminal of the amplifier circuit is connected to the gate of the field effect transistor FET (46), and the drain terminal of the field effect transistor FET is connected to the diode (48). ) is shared with the power supply terminal of the amplifier circuit and connected to one voltage control terminal (45), and the source of the field effect transistor FET is connected to the common output terminal (9). The common output terminal is connected to a constant potential via a current source (49), and the voltage level applied to any one of the N voltage control terminals and the other is low, A switch circuit characterized in that a signal inputted from any one of the N input terminals is selected and outputted from the common output terminal based on a combination of high signals. 6. A switch circuit that selects one of the signals input from each of N input terminals (N is 2 or an integer exceeding 2) and outputs it from a common output terminal, which has one input terminal. (44) is connected to the input terminal of the amplifier circuit (C), the output terminal of the amplifier circuit is connected to the gate of the field effect transistor FET (46), and the power supply terminal of the amplifier circuit is connected to one voltage control terminal ( 45), the drain terminal of the field effect transistor FET is connected to a common power supply voltage terminal (41), and the source of the field effect transistor FET is connected to a common output terminal (9). The common output terminal is connected to a constant potential via a current source (49), and the low voltage level applied to any one of the N voltage control terminals and the other is connected to the common output terminal via a current source (49). , high, selects a signal input from any one of the N input terminals and outputs it from the common output terminal. 7. The switch circuit according to claim 3, wherein the first
A switch circuit characterized in that the drain terminal of the field effect transistor FET (4) and the drain terminal of the second field effect transistor FET (6) are connected and shared. 8. The switch circuit according to claim 5, wherein drain terminals of the N field effect transistors FETs are interconnected and shared.