JPH02238709A - Driver - Google Patents

Abstract

PURPOSE:To increase the output current without changing a power voltage at the rising of an output circuit by controlling the output current through the addition of a delay circuit and the use of capacitance coupling. CONSTITUTION:A signal transmission line 10 connects in series with an output terminal of a switching element 1 passing an applied voltage in one-way and a delay circuit 2 whose output terminal connects to a capacitor 7 in series is connected in parallel with the signal transmission line 10 and an input terminal of an output switching element 3 connects to the signal transmission line 10. Then the output voltage is boosted by using the capacitive coupling. Thus, a drive circuit increasing its output current at rising of the output circuit 6 without varying the power voltage is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a drive device that boosts an output voltage using capacitive coupling.

(Prior Art) As shown in FIG. 5, a conventional drive device uses a complementary MOS transistor (
The P-channel type (1a) and N-channel type (lb) MO8 transistors are switched on or off by applying a true or non-true voltage to the respective gates of the C-MOS transistors (hereinafter referred to as C-MOS transistors). The above P-channel type MOS transistor (
The charge applied to the drain of the P-channel MOS transistor (la) is input to the gate of the high voltage output N-channel MOS transistor (3a) connected to the source of the transistor 1a). Then, depending on whether the input charge is true or non-true, the high voltage output N-channel type MOS transistor (3a) is turned on or off.
This is to drive the output circuit (6) connected to its drain.

The operation of the conventional drive device described above is shown in FIGS. 6(a) to (C).
) This will be explained with reference to the timing chart.

The above P channel type (1a) and the above N channel type (
true (VDD) voltage on the gate of lb) (Figure 6(a))
When inputted, the P-channel type MOS transistor (la) turns OFF, and the N-channel type MO8 transistor (lb) turns ON. As a result, the gate potential of the high-voltage output N-channel MOS transistor (3a) is lower than that of the N-channel MOS transistor (3a).
Since the source of lb) is grounded, it becomes zero (Fig. 6(b)).

Therefore, since a non-true (zero) signal is input to the gate of the Taka-Kameda output N-channel type MOS transistor (3a), it cannot be turned off, and no current flows between the source and drain (Fig. 6(C) )). Next, when a non-true (zero) voltage (FIG. 6(a)) is input to the gate of the C-MOS transistor, the P-channel MOS transistor (l
a) is ONL, and the N-channel type MO8} range resistor (lb) is turned off. Then, the gate potential of the high voltage output N-channel MOS transistor (3a) is the same as that of the power supply V at the drain of the P-channel MOS transistor (la) of the C-MOS transistor.
Since D D (5) is connected, it becomes VDD, but
Since the operating speed of the MOS transistor is not very fast, there is a slight time delay (FIG. 6(b)). Therefore, the high voltage output N-channel type MO8 transistor (3a) is inputted with a true voltage (Vos) to the gate, so it is turned on, and a current IDD flows between the source and drain (FIG. 6(C)).

(Problem to be Solved by the Invention) When a drive device is used to drive a circuit connected to its output leakage, a large current () I
However, the above-mentioned higher voltage output N-channel type MO
In order to cause a large current to flow between the source and drain of the S transistor (3a), a large voltage (>VDD) must be applied to the gate. To do so, K increases the output voltage of the C-MOS transistor connected to the gate of the high voltage output N-channel type MOS transistor (3a). That is, the voltage of the power supply VDD (5) connected to the drain of the C-MO8 transistor must be increased. Alternatively, the area of the source and drain of the high voltage output N-channel type MOS transistor (3a) must be increased. However, a problem arises in that increasing the voltage of the power supply also increases current consumption.

In addition, there is also a problem in increasing the power supply voltage because the voltage rating of the power supply is fixed and it is often impossible to increase the power supply voltage by more than one level. Furthermore, if the area of the source and drain of the high voltage output N-channel MOS transistor (3a) is increased, the area of the semiconductor chip will be increased, leading to a decrease in the degree of integration and an increase in manufacturing cost.

In this way, in the past, a large current sometimes flowed when starting up the circuit connected to the drive power supply, but increasing the power supply voltage, which increases the current consumption,
There were problems such as a large area of the semiconductor chip, a decrease in the degree of integration, and an increase in manufacturing costs.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a drive circuit that increases the output current when starting up the output circuit without changing the power supply voltage.

[Structure of the Invention] (Means for Solving the Problems) In the drive device of the present invention, a signal transmission path is connected in series to the output end of a switching element that applies voltage in one direction, and a signal transmission path is connected in parallel to this signal transmission path. A delay circuit having a capacitor connected in series is connected to the output terminal thereof, and an input terminal of the output switching element is connected to the signal transmission path.

(Function) In the device configured as described above, the voltage output from the switching element is transmitted between the signal transmission path and the delay circuit.
The voltage applied to the delay circuit reaches the capacitor connected in series to the delay circuit with a slight delay from the voltage applied to the signal transmission path. Also,
At this time, the capacitor is already charged, so the voltage output from the delay circuit K is added to it.
By applying these two voltages to the input terminal of the output switching element, a large output current can flow.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings. 1st
The figure shows an example of a drive device according to the present invention. In this figure, an input (4) and an external power supply (5) are connected to the switching element (1), and by inputting a control signal from the input (4), the switching element +
1) Turn ON and OFF. Further, one end of a signal transmission line 4 is connected in series to the output end of the switching element (1), and the other end is manually connected to the gate of the output switching element (3). Then, this signal transmission path (1
A delay circuit (2) for delaying the voltage output from the switching element and a capacitor (7) connected in series with the delay circuit (2) are connected in parallel with G. Then, the voltage that has passed through the signal transmission path a1 and the delay circuit (power) is manually applied to the output switching element (3) to turn this output switching element ON and OFF, resulting in an output connected to its output terminal. Turn on and off the circuit (6).

Next, a case where the above-mentioned drive circuit is constructed using MO8 transistors will be explained using FIG. 3. In this figure, the switching element shown in FIG.
The cathode of the diode (8) and the N-channel MO
The drain of S transistor (b) is connected, and the source is grounded. In addition, the gates κ of the P-channel type (la) and N-channel type (b) MO8 transistors are inputted separately (4a) and (4b), respectively.
The drain of the P-channel type MOS transistor is connected to an external power supply V DD (5). The delay circuit shown in FIG. 1 includes C-MOS transistors (2) * (2b)e (zc), (2d
) are connected in series, and the drain of each P-channel type MOS transistor is connected to a power supply ■GS (
9a), (9b), (9C), and (9d) are connected, and the source of the N-channel type MOS transistor is grounded. Further, a capacitor (7) for boosting the voltage is connected in series to the C-MO8 transistor. Furthermore, a high voltage output N-channel type transistor (3a) is connected to the output switching element (3) shown in Fig. 1, and its source is grounded and its drain is connected to the output circuit (6). has been done.

Next, the operation of the drive device described above will be explained in FIGS. 4(a) to 4(d).
) Explain using a timing chart.

The above P channel type (1a) and the above N channel type (
The true (VDD) voltage (Figure 4(a)
) is input, the P-channel MOS transistor (t a ) is turned off, and the N-channel MOS transistor
The OS transistor (lb) is turned on (0).Then, the output voltage of the switching element (1) becomes zero because the source of the N-channel type MO8 transistor (lb) is grounded. In addition, the above C- which is a delay circuit
MOS transistor (2a)s (2b)e (2
C)-(2d) performs inverter operation, so its output voltage becomes 0K (Fig. 4(C)). As a result, the above-mentioned ``high voltage output N-channel type MO8 transistor (3
The gate potential of a) becomes zero (FIG. 4(b)). Since the gate potential is not truly increasing, the high voltage output N-channel type MO8 transistor (3a) is turned off and the output current becomes zero (FIG. 4(d)). Next, when a non-magnetic voltage (Fig. 4(a)) is input to the gates of the P-channel type (la) and N-channel type (lb), the P-channel type MOS transistor (la) is turned on, The N-channel MOS transistor (lb) is turned off.

Then, the output voltage of the switching element (1) becomes VDD because the external power supply VDD (5) is connected to the drain of the P-channel type MOS transistor (la). In addition, the above C-MO which is a delay circuit
S transistor (2aL (2b)t (2C),
(2d) performs an inverter operation and is delayed. and,
Its output voltage is connected to the final stage of the delay circuit.
-MOS transistor (2d) P-channel type MO8
The drain of the transistor is connected to an external power supply Yes (9d
) is connected, so it becomes VGS (Figure 4 (C))
. As a result, the gate potential of the high voltage output N-channel type MO8 transistor (3a) is initially equal to VDD which has passed through the power transmission path.

At this time, the capacitor (power) is also charged. Then, just when it is charged, the delay circuit outputs Yes with a delay, and due to the capacitive coupling of the capacitor (7), the high voltage output N-channel type The gate potential of the MOS transistor (3a) becomes VDD+Yes (Fig. 4(b)).Furthermore, the gate potential mentioned above becomes VDv+Va.
When it becomes s, the above P-channel type MOS transistor (
Since the potential is lower in la), the potential is also applied to this source side, which may destroy the source. Therefore, by inserting the diode, this reverse voltage is prevented from being applied to the source. In addition, the high voltage output N-channel MOS transistor (3
The voltage VDD+VGS applied to the gate of a) is discharged and, as a result, becomes constant at vDD (the fourth
Figure (b)). Also, the output current at this time is proportional to the increase/decrease in the gate potential, so that the gate potential is VDD+VG3.
When the voltage becomes , the output current increases and becomes IDD+IGS, and when the gate t becomes VDD, the output current also increases to ID
become. Figure 4(d). Next, when the human power voltage becomes VDD, all the voltages become zero K as in the first state.

When configured as in this embodiment, the output current, which was conventionally controlled by increasing or decreasing the power supply voltage, can be controlled by adding a delay circuit and using capacitive coupling. The output current can be increased without increasing the output current. Furthermore, since a diode is inserted into the switching element, the element will not be destroyed even if a voltage is applied in the opposite direction.

In the embodiments detailed above, C-MOS transistors were used for the switching elements and delay circuits, but these may also be constructed from bibolar K as shown in FIGS. 2(a) to (C). MOS transistors and bibolar transistors may be mixed.

〔Effect of the invention〕

As explained above, the present invention inserts a rectifying element that applies voltage in one direction to a switching element, and connects a delay circuit and a capacitor connected in series between the switching element and the output switching element. By configuring the signal transmission lines K to be connected in parallel, it is possible to increase the output current without changing the power supply voltage when starting up the output circuit.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a driving device showing a first embodiment of the present invention, FIGS. 2(a) to (C) are circuit diagrams of switching elements in the device, and FIG. 3 is a MOS A circuit diagram of a case configured with transistors, Fig. 4 is a timing chart thereof, Fig. 5 is a circuit diagram of a conventional drive device, and Fig. 6 (
a) to (C) are timing charts thereof. l...Switching element 1 1a...P channel type MO8 transistor, lb.
...N-channel type MOS transistor, 2...Delay circuit, 2a, 2b, 2c, 2a...c-MO8 transistor, 3...Output switching element 1 3a...High voltage output N-channel type MOS Transistor, 7... Capacitor, 8... Diode, 10... Signal transmission path. Agent Patent Attorney Ken Nori Chika Kikuo Takehana C (1) Daisen (b) (C) Fuguchi Daizu

Claims (3)

[Claims] (1) A switching element that applies voltage in one direction, a signal transmission line connected in series to the output end of this switching element, and a capacitor connected in parallel to the signal transmission line and connected in series to the output end of the switching element. What is claimed is: 1. A drive device comprising: a delay circuit configured to provide a signal transmission path; and an output switching element having an input end connected to the signal transmission path. (2) The first transistor means that the switching element conducts by applying a positive or negative input voltage, the second transistor means having the opposite characteristics, and the first and second transistor means are connected in series. 2. A drive device according to claim 1, further comprising an output connected to the connecting point thereof, and rectifying means connected between said first and second transistor means. (3) The drive device according to claim 1, wherein the delay circuit is at least one C-MOS transistor connected in series.