JPH02238598A - Multi-channel analog input processor - Google Patents

Abstract

PURPOSE:To shorten the processing time per channel by sending the channel address of an analog multiplexer side before the channel address of a data processing circuit side and starting the input of the analog input signal of a next channel during the processing of digital data. CONSTITUTION:An address latch circuit 9 which latches a channel address is interposed between an address generating circuit 8 and the data processing circuit 7 and an address control circuit 10 which performs timing control between the address latch circuit 9 and address generating circuit 8 is provided. The address latch circuit 9 enables a multiplexer 5 to start selecting the analog signal of a next channel during the processing period of the digital data of the channel by the data processing circuit 7 by generating a shift in timing between the channel address of the side of the analog multiplexer 5 and the channel address of the side of the data processing circuit 7. Consequently, the processing time per channel can be shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multi-channel analog input processing device in an analog measurement system.

[Conventional technology]

FIG. 3 is a block diagram showing a conventional multi-channel analog input processing device. In the figure, 1 to 4 are analog buffer amplifier circuits that input analog input signals CH1 to CH4, respectively, and 5 is a plurality of analog input signals CI{i to 1 of CH4 from the analog buffer amplifier circuits 1 to 4 according to channel address A. An analog multiplexer that selects and outputs a point; 6 is an analog-to-digital conversion circuit (hereinafter referred to as an A/D conversion circuit) that converts the analog output signal B from the analog multiplexer 5 into digital data C; T;
8 is a data processing circuit that processes the digital data C from the AD conversion circuit 6 using the channel address A, and 8 is an address generation circuit that provides the channel address A to the analog multiplexer 5 and the data processing circuit 7.

Next, the operation will be explained. Here, FIG. 4 is a timing chart showing the operation. Address generation circuit 8
switches the channel address A to be output at time to and supplies it to the analog multiplexer 5 and the data processing circuit 7. The analog multiplexer 5 converts the analog vanofer amplifier circuit 1 according to the received channel address A.
.about.4 are selected from among the analog input signals CH1 to CHd and output to the A/D conversion circuit 6. The analog output signal B from the analog multiplexer 5 is determined at time t1 after the period T1 has elapsed. The A/D conversion circuit 6 converts this analog output signal B into digital data C during a period T2 up to time t2, and sends it to the data processing circuit 7. The data processing circuit 7 converts the digital data C from the A/D conversion circuit 6 into the channel address A from the address generation circuit 8.
Process according to the following. Here, the data processing circuit 7 requires a period T3 from time t2 to time t for this processing.

Therefore, the processing time per channel is TI+T2
+T3.

[Problem to be solved by the invention]

Since the conventional multi-channel analog input processing device is configured as described above, in order to increase the processing speed, each of the periods TI, T2, and T3 must be shortened.
Therefore, it is necessary to increase the response speed of the analog multi-flexor 5 and the A/D conversion circuit 6, as well as the processing speed of the data processing circuit 7, leading to an increase in the cost of the entire device, and furthermore, the circuit becomes complicated and oscillations occur. There were problems such as it could cause problems such as

Incidentally, as a prior art, there is a technique described in Japanese Patent Publication No. 59-2967.

This invention was made to solve the above-mentioned problems, and includes an analog multiplexer, an A/D conversion circuit,
The response speed and processing speed of the data processing circuit, etc. remain the same,
An object of the present invention is to obtain a multi-channel analog input processing device that can shorten the processing time per channel.

[Means to solve the problem]

The multi-channel analog input processing device according to the present invention includes:
An address launch circuit for searching a channel address is inserted between an address generation circuit and a data processing circuit, and an address control circuit is provided for controlling the timing of the address launch circuit and the address generation circuit.

[For production]

The address latitude circuit of the present invention shifts the timing of the channel address on the analog multiplexer side and the channel address on the data processing circuit side, so that the multiplexer selects the next channel while the data processing circuit is processing digital data of the channel. Allows selection of analog input signals to be initiated, reducing apparent data processing time.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, 1 to 4 are analog Vanoffer amplifier circuits, 5 is an analog multiplexer, 6 is an A/D conversion circuit, 7 is a data processing circuit, and 8 is an address generation circuit, and the same symbols are used in Figure 3. The detailed explanation will be omitted since it is the same or equivalent to the conventional one. Reference numeral 9 indicates an address latch circuit which launches the channel address A from the address generation circuit 8 and outputs it as a channel address D to the data processing circuit 7. Reference numeral 10 indicates the generation timing of the channel address A in the address generation circuit 8 and the address launch circuit 9. This is an address control circuit that controls the launch timing of channel address A.

Next, the operation will be explained. Here, FIG. 2 is a timing chart showing the operation. Address generation circuit 8
outputs the channel address A switched at time to to the analog multiplexer 5. The analog multiplexer 5 selects one point from the analog input signals CH1 to CHJ according to the channel address A and sends it to the A/D conversion circuit 6, which converts it into digital data C. It is sent to the data processing circuit 7. At this time, the analog output signal B from the analog multiplexer 5 is determined at time t1 after the elapse of period T1, and the A/D conversion circuit 6 executes the conversion process during period T2 from time t1 to time t2. , up to this point is the same as the conventional case.

Here, the channel address A generated by the address generation circuit 80 is also given to the address launch circuit 9. Under the control of the address control circuit 10, the address latch circuit 9 latches the channel address A at almost the same time as the A/D conversion circuit 6 outputs the digital data C at time t2. Thereafter, at time t1l, the address generation circuit 8 switches the channel address A being sent out to the address value of the next channel under the control of the address control circuit 10. This channel address A is sent to analog multiplexer 5 and address latch circuit 9. The data processing circuit 7 processes the digital data C from the A/D conversion circuit 6 according to the channel address D latched by the address latch circuit 9. The data processing circuit 7 also performs this processing at time t2 as in the conventional case.
Therefore, a period T3 is required until time t3.

During the processing of this digital data C, the address generation circuit 8
According to the channel address A of the next channel from
In the analog multiplexer 5, selection of the next channel analog input signals CH1 to CH2 is started in parallel.

Here, the address latch circuit 9 selects the channel address A.
If timing control is performed by the address control circuit 10 so that the address generation circuit 8 immediately generates the address value of the next channel after the initialization, the period T4 from time t2 to time t4 can be made almost "0". can. Therefore, the processing time per channel is approximately TI
It becomes possible to shorten the time to +T2.

〔Effect of the invention〕

As described above, according to the present invention, the channel address on the analog multiplexer side is sent out before the channel address on the data processing circuit side, and the input of the analog input signal of the next channel is started during the processing of digital data. Therefore, with the addition of a small circuit, analog multiplexers and A/Ds with fast response and processing speeds can be created.
Processing time per channel can be shortened without using conversion circuits, data processing circuits, etc., the circuit configuration is simple, there is no need to worry about oscillation, etc., and an inexpensive multi-channel analog input processing device can be obtained. .

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a multi-channel analog input processing device according to an embodiment of the present invention, FIG. 2 is a timing chart showing its operation, and FIG. 3 is a block diagram showing a conventional multi-channel analog input processing device. FIG. 4 is a timing chart showing the operation. 5 is an analog multiplexer, 6 is an A/D conversion circuit, 7
8 is a data processing circuit, 8 is an address generation circuit, 9 is an address latch circuit, and 10 is an address control circuit. In addition, the same symbols in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] an analog multiplexer that selects one of a plurality of analog input signals according to a channel address; an analog-to-digital conversion circuit that converts the analog output signal from the analog multiplexer into digital data; and a digital output signal from the analog-to-digital conversion circuit. a data processing circuit that processes data according to the channel address; an address generation circuit that generates the channel address for the analog multiplexer and the data processing circuit; and an address generation circuit that generates the channel address sent from the address generation circuit to the data processing circuit. A multi-channel analog input processing device comprising: an address latch circuit that latches; and an address control circuit that controls channel address generation timing of the address generation circuit and latching timing of the channel address by the address latch circuit.