JPH02237150A - Manufacture of complementary-type mos transistor - Google Patents

Abstract

PURPOSE:To eliminate a disconnection of each electrode wiring part and to lower a contact resistance and a diffusion resistance by a method wherein impurities of opposite conductivity types are introduced into a p-type active region and an n-type active region, an impurity diffusion layer for a source and a drain is formed and etched back and a high-melting-point metal silicide film is formed on the diffusion layer, a gate electrode, a source electrode and a drain electrode. CONSTITUTION:A gate oxide film 4 is formed selectively on a p-type active region and an n-type active region 1, 2; a polycrystalline silicon film is etched selectively; a gate electrode 5, a source electrode and a drain electrode 5 are formed so as to come into contact with one part of the individual active regions. Impurities 7 of opposite conductivity types are introduced into the individual p-type and n-type active regions 1, 2 coming into contact with the source electrode and the drain electrode; an impurity diffusion layer 8 for the source and the drain is formed. In addition, an oxide film is etched back by an anisotropic etching operation; after that, a high- melting-point metal silicide film 11 is formed on the impurity diffusion layer 8, the gate electrode, the source electrode and the drain electrode 5. Thereby, a diffusion resistance and a contact resistance in each part can be made low; it is possible to prevent a disconnection in a contact hole part and a crack from being caused.

Description

[Detailed Description of the Invention] [Field of Application of Industry-F] The present invention relates to a method for manufacturing a complementary MOS transistor, and more specifically, to a method for manufacturing a complementary MOS transistor integrated circuit device. - This relates to an improvement in the manufacturing method that can simultaneously reduce the diffusion resistance of the drain impurity diffusion layer and the contact resistance of each gate and source/drain electrode wiring.

(Prior Art) The main manufacturing steps for different examples of conventional complementary MOS transistor integrated circuit devices of this type are shown in FIGS. 3 and 4, respectively.

That is, in one of the conventional methods shown in FIGS. 3(a) to 3(e), first, the active regions 1 and 2 of the p-type conductivity type and the n-type conductivity type are A thick field oxide film 3 is formed to separate the forming regions of each transistor (PMOS, NMOS), and a thin silicon oxide film 4a is formed by thermally oxidizing the forming region of each transistor (first step). 3(a)), a polycrystalline silicon film is further deposited on these entire surfaces and patterned to form respective gate electrodes 5 and polycrystalline silicon wirings corresponding to each active region 1.2. 5a
((b) of the same figure).

Next, by selectively covering the n-type active region 2 side with a resist pattern 6 and using this as a mask, n-type impurity 7 is introduced only into the p-type active region l side, forming an n''' type source/drain. Each impurity diffusion layer 8 is formed separately (FIG. 1C), and after removing the resist pattern 6 used for this mask, in the same way, although not shown in this S, this time, n A p-type impurity is selectively introduced only to the type active region 2 side, and p+ type source/drain impurity diffusion layers 9 are formed.
After forming each of these, an oxide film is formed on the entire surface of these, and one of them is etched back by anisotropic etching to diffuse each impurity of the stiff B1 type and P+ type source/drain. The surfaces of the layers 8 and 9 as well as the surfaces of the gate electrodes 5 and polycrystalline silicon wiring 5a are selectively exposed, thereby forming the gate oxide film 4 which has been gently formed. , third wall 10 on the side surface of each gate electrode 5 and polycrystalline silicon wiring 5a.
are obtained for each ((d) in the same figure).

Furthermore, a high melting point metal film is formed on the entire surface of these and silicided by heat treatment to form 1 liter of high melting point metal silicide film on each corresponding part, and the remaining high melting point metal film that has not been silicided is appropriately removed. (see figure (e)
)) As a result, a complementary MOS transistor including PMOS and NMOS transistors as expected was obtained.
In the complementary MOSh transistor having the structure shown in FIG. 3, each of the high melting point metal silicide films l1 connects each source/drain impurity diffusion layer 8, 9, each gate electrode 5, and a polycrystalline silicon wiring. This achieves low contact resistance with 5a.

Next, in the other conventional method shown in FIGS. 4(a) to 4(e), first, in each active region 1.2F of the p-type conductivity type and the n-type conductivity type of the silicon substrate, ,P
After forming a thick field oxide film 3 to isolate the forming regions of each MOS and NMOS transistor, and thermally oxidizing the forming region of each transistor to form a thin silicon oxide film, is selectively removed to expose a portion of each active region 1.2, and a required thin gate oxide film 4 is formed on each of these portions (FIG. 4(a)). , a polycrystalline silicon film is deposited on these entire surfaces, and a high melting point metal silicide film 11 is formed by depositing a Jh film to form a two-layer structure film, and then this two-layer structure film is selectively etched. Removal 1. / and a high melting point metal silicide film l1 corresponding to the outer active region 1.2.
Each gate electrode 5 having a high melting point metal silicide film I1 and at least a part of a polycrystalline silicon wiring 5a having a high melting point metal silicide film I1 are formed (FIG. 2(b)).

Next, @￥e. By covering the n-type active region 2 side with a resist pattern 6 and using this as a mask, the n-type impurity 7 is selectively introduced only into the p-type active region 1 side, and the n+
After forming the respective impurity diffusion layers 8 for the type source and drain respectively 17 (FIG. (C)) and removing the resist pattern 6 used for this mask, the same process is performed for this S, and this time p
By covering the resist pattern 6 on the D-type active region 1 side and using this as a mask, p
A type impurity 12 is selectively introduced to form each p+ type source/drain impurity diffusion layer 9 (FIG. 1(d)).
), and by removing the resist pattern 6 used as a mask ((e) in the same figure), the expected Q/7)
A complementary MOS+- transistor including pfOS and NMOS transistors is obtained, and the complementary MOS+- transistor of the configuration shown in FIG. In the transistor, each J
1, each high melting point metal silicide film 11.7 Therefore, the famous game:
The contact resistance of the electrode 5 and the polycrystalline silicon wiring 5.1 has been reduced, and at the same time, the resistance can be reduced from each source/drain impurity diffusion layer 8.9 without going through a contact hole. This makes it possible to draw out the electrode wiring.

[Problem to be solved by the invention]

However, in the case of the complementary MOS transistor to which the conventional manufacturing method described above is applied, in the case of the method shown in FIG. It is necessary to form an electrode wiring through a hole, and when forming an electrode wiring through such a contact hole, a local level difference is formed due to the contact hole, so each electrode wiring of source and drain must be formed. In addition, in the case of the configuration shown in Figure 4, the diffusion resistance of the source and drain is large (generally about 50Ω/hole to 100Ω/hole), so the high speed of the transistor This was detrimental to the operation.

This invention was made to solve these conventional problems, and its purpose is to form electrode wiring to each source/drain impurity diffusion layer and connect it through a contact hole. At the same time, gate electrode wiring and source/drain 'N. It is an object of the present invention to provide a method for manufacturing a complementary MOS transistor of this type, which can simultaneously reduce the contact resistance of the pole wiring and the diffusion resistance of the source and drain.

[Means to solve the problem]

In order to achieve the above object, the present invention provides a complementary MOS
In manufacturing a transistor, an oxide film is formed on each of the p-type and n-type conductivity type active regions separated from each other on a silicon substrate, and this is selectively etched away to form a gate oxide film on each. , and a step of exposing required parts of each active region, and after depositing a polycrystalline silicon film on the entire surface thereof, selectively etching it away to form a gate electrode on the gate oxide film. , at the same time, a source contacting a portion of each exposed active region.
a step of forming drain electrodes respectively; a step of introducing impurities of opposite conductivity type into each of the p-type and n-type active regions to form impurity diffusion layers of source and drain; After forming an oxide film on the entire surface, Nisai 1 is etched back by anisotropic etching to selectively remove the impurity diffusion layer of each source/drain, and the surfaces of each gate and source/drain electrode. After the exposing process and the formation of a high melting point metal film on the entire surface, the stiffness is selectively silicided by heat treatment to form a high melting point metal silicide film on each corresponding part, and the remaining unsilicided parts are The method is characterized in that it includes at least a step of removing the high melting point metal film of the reaction.

[For production]

That is, in the method of the present invention, first, on each active region of p-type and n-type conductivity type, which are separated from each other,
By selectively etching the polycrystalline silicon film, a gate electrode is formed on each gate oxide film, and a source/drain electrode is formed in contact with a part of each active region. Because they are formed separately, it is possible to precisely control the dimensions of each electrode, and impurities of opposite conductivity types are introduced into the p-type and n-type active regions in contact with each source and drain electrode. Since the impurity diffusion layers for each source and drain are formed, there is no need to take out each electrode through a contact hole, and furthermore, it is not necessary to take out each electrode through a contact hole. After etchback using anisotropic etching. Each sauce
A refractory metal silicide film, which is a refractory metal film silicided, is formed on the drain impurity diffusion layer, as well as on each gate electrode and source/drain electrode. As for the impurity diffusion layer, high-speed operation is achieved by coating it with a high-melting point metal silicide film, and the gate electrode and source layer are made of a two-layer structure of a polycrystalline silicon film and a high-melting point metal silicide film.
In the drain electrode, abnormal operation due to the pn junction inside the polycrystalline silicon film can be eliminated by the ohmic contact of the high melting point metal silicide film of the F layer.

(Embodiment) Hereinafter, an embodiment of the method for manufacturing a complementary MOS transistor according to the present invention will be described in detail with reference to FIGS. 1 and 2.

1(a) to 1(f) are cross-sectional views schematically showing the main steps of the manufacturing method of a complementary MOS transistor integrated circuit device to which this embodiment is applied, and FIG. FIG. 3 is a planar pattern diagram showing the main part configuration of the complementary MOS transistor as above, and in each of these embodiment figures,
The same reference numerals as in the prior art shown in FIGS. 3 and 4 represent the same or corresponding parts.

That is, in these FIGS. 1 and 2, the manufacturing method according to this embodiment first includes the following steps:
A thick field oxide film 3 is formed to separate the formation regions of each PMOS and NMOS transistor,
Further, the forming regions of each of these transistors are thermally oxidized to form a thin silicon oxide film, and this is selectively etched to form a gate oxide film 4 for each, and required portions of each active region 1.2 are etched. Expose (Fig. 1(a)
), then a polycrystalline silicon film is deposited on the entire surface of these using a CVD method, etc., and this is patterned so as to extend outside the device area, as shown in FIG. Each gate oxide film 4 corresponds to the region 1.2.
A gate electrode 5 is selectively formed on each active region 1.2, and at the same time, a source electrode 5 is formed in contact with a part of each active region 1.2.
selectively forming at least a portion of the drain electrode 5 (
Figure (b)).

Next, by covering the n-type active region 2 side with a resist pattern 6 and using the resist pattern 6 as a mask, only on the p-type active region l side of the exposed machining plate where the source/drain electrodes 5 are arranged, Mouth-type impurities 7 are selectively introduced by ion implantation or the like to form each n-type source/drain impurity diffusion layer 8 (see figure (C)). After removing the resist pattern 6 on the region 2 side, in the same way, although not shown in this step, the p-type active region l side is covered with a resist pattern 6, and this is used as a mask. P-type impurities are selectively introduced only on the side of the n-type active region 2 of the exposed Sawatama S where the source/drain electrodes 5 are arranged, and p+-type source/drain impurity diffusion layers 9 are formed respectively. After removing the resist pattern 6 on the p-type active region l side used for this mask,
An oxide film 10a is deposited on these entire surfaces by CVD or the like (FIG. 4(d)). Then, this is etched back by anisotropic etching to form the surface of each impurity diffusion layer 8.9 of these 03 type and p type source/drain, and
The surfaces of the navigation gate and the source/drain electrodes 5 are selectively exposed, thereby forming sidewall IOs on the side surfaces of the respective gates and source/drain electrodes 5 (as shown in the figure). (e))
.

Further, after forming a high melting point metal film on the entire surface of these, the stiffness is locally silicided by heat treatment, and a high melting point metal silicide film 11 is selectively formed in each corresponding part, and In addition, the remaining unreacted high-melting point metal film that has not been silicided is removed appropriately (Figure 4 (f)), thereby producing the desired PMOS shown in Figures 1 and 2. ．． A complementary MOS transistor including each NMOS transistor is obtained.

Therefore, in the complementary MOS transistor having the structure of this embodiment manufactured as described above, each of the gate and source/drain electrodes 5 is formed of a polycrystalline silicon film, and the polycrystalline silicon film is Since the film has a two-layer structure by overlaying high-melting point metal silicide rAu on the upper layer, it is possible to connect the gate electrodes 5 of PMOS and NMOS transistors in common, or similarly connect the source and drain electrodes 5 in common. p, which occurs inside the polycrystalline silicon film when
Abnormal operation caused by the n-junction can be eliminated by ohmic contact of the high-melting point metal silicide film 1L to this polycrystalline silicon film 2, allowing normal operation to occur, and impurity diffusion in the source and drain. Since the layer 8.9 is also covered with the high melting point metal silicide film l1, even higher speed operation is possible.

Further, for each source/drain electrode 5, each corresponding portion, that is, the impurity diffusion layer 8 of each source/drain,
Since it is formed by buttering the polycrystalline silicon film that is in contact with a part of 9, it is not possible to connect it through a contact hole made in the insulating oxide film as in the normal case. In contrast, it is possible to prevent disconnection of the electrode wiring and the occurrence of cracks in the contact hole area, which generally results in localized steps, thereby improving manufacturing yields and ensuring long-term reliability. Since this is a two-layer structure film consisting of a polycrystalline silicon film and a high melting point metal silicide film l1, a low contact resistance and a thermally stable electrode structure can be obtained.

Furthermore, when patterning each gate and each source/drain electrode 5, each of these electrodes 5 is made of only one layer of polycrystalline silicon film at this point, and when exposing the resist for patterning. Since the surface reflectance is smaller than that of the high melting point metal silicide Hq++, it is easy to control the dimensions of the resist pattern, and the etching can be performed accurately, and the dimensions of the electrode pattern can also be easily controlled. Become.

In addition, in the above embodiment method, the case of a p-type silicon substrate and an n-well structure was described, but this also applies to the case of an n-type silicon substrate, a p-well structure, or a p-type silicon substrate. Both the substrate and pn well structures may be used, and the same effect may be obtained for each. Effects can be obtained.

Furthermore, in the method of this embodiment, each impurity diffusion layer 9 of the P3 type source/drain is formed after each impurity diffusion layer 8 of the N1 type source/drain is formed, but even if this formation order is reversed, no This is similar, and furthermore, similar actions and effects can be obtained when an LDD structure is formed by using the sidewalls IO of the gate electrode 5.

〔Effect of the invention〕

As detailed above, according to the method of the present invention, gate oxide films are first selectively formed on each of the p-type and n-type conductivity type active regions that are separated from each other, and then, By selectively etching the polycrystalline silicon film, a gate electrode is formed on each gate oxide film, and a source/drain electrode is formed in contact with a part of each active region. In the case of the polycrystalline silicon film used as the material, the surface reflectance when the resist is exposed is smaller than that of the high melting point metal silicide film, and as a result, it is difficult to control the dimensions of this resist pattern. It has the advantage that etching can be performed accurately, electrode pattern dimensions can be easily controlled, and each of these electrodes can be formed with high characteristics.

In addition, impurities of opposite conductivity types are introduced into each of the p-type and n-type active regions adjacent to each source/drain electrode,
Since the impurity diffusion layer for each source and drain is formed, each source and drain electrode can be taken out without using a contact hole, which is different from the conventional method. Unlike the connection made through a contact hole made in a general insulating oxide film, this method prevents disconnection of the electrode wiring and the occurrence of cracks at the contact hole area, which causes local steps. This will improve the manufacturing yield of the device. F and long-term reliability can be ensured.

Furthermore, after etchback by anisotropic etching of the oxide film. In each source/drain impurity diffusion layer 1, and each gate electrode and source/drain electrode -L,
A high melting point metal silicide film, which is a high melting point metal film silicided, is formed on each part, and the diffusion resistance of each part is increased. By reducing the contact resistance, the high-speed operation of the device configuration can be improved.On the other hand, the source and drain impurity diffusion layers are coated with a high melting point metal silicide film to further improve the high-speed operation of the device configuration. High-speed operation is possible, and the gate electrode and source/drain electrode have a two-layer structure of a polycrystalline silicon film and a high melting point metal silicide film.
This is to prevent abnormal operation due to the pn junction that occurs inside the polycrystalline silicon film when the gate electrodes of MOS transistors are commonly connected, or similarly when the source and drain electrodes are commonly connected. Each of them has excellent features, such as being able to solve the problem by ohmic contact of the high-melting point metal silicide film on the polycrystalline silicon film and allowing normal operation.

[Brief explanation of drawings]

FIGS. 1(a) to 1(f) show complementary MOs according to the present invention.
2 is a cross-sectional view schematically showing the main manufacturing steps in sequence in which an embodiment of the method for manufacturing an S transistor is applied, and FIG. 2 is a plan pattern diagram showing the arrangement of main parts in the complementary MOS transistor, In addition, FIGS. 3(a) to (e) and FIGS. 4(a) to (e) schematically show the main steps of the conventional method for manufacturing complementary MoS transistors according to different examples, respectively. FIG. 1... p-type conductivity type active region of silicon substrate, 2...
... n-type conductivity type active region of silicon substrate, 3 ... field oxide film, 4 ... gate oxide film, 5 ...
Gate, source and drain electrodes, 6... resist pattern, 7... n-type impurity, 8... n''
Type source/drain impurity diffusion layers, 9...p+
Each type source/drain impurity diffusion layer, 10a...
Oxide film, lO... sidewall, 11... high melting point gold silicide film. Agent Masuo Oiwa

Claims (1)

[Claims] An oxide film is formed on each of p-type and n-type conductivity type active regions separated from each other on a silicon substrate, and this is selectively etched away to form a gate oxide film on each active region. After depositing a polycrystalline silicon film on the entire surface of the polycrystalline silicon film, the polycrystalline silicon film is selectively etched away to form a gate electrode on the gate oxide film. A step of forming source/drain electrodes in contact with a part of each active region, and introducing impurities of opposite conductivity type into each of the p-type and n-type active regions to form source/drain impurities. After forming a diffusion layer and forming an oxide film on the entire surface thereof, this is etched back by anisotropic etching to form the impurity diffusion layer of each source/drain, and each gate and source/drain. After selectively exposing each electrode surface and forming a high melting point metal film on the entire surface, this is selectively silicided by heat treatment to form a high melting point metal silicide film on each corresponding part. , and removing an unreacted high melting point metal film that has not been silicided.