JPH02237050A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a U-shaped groove isolation formation method, by which a crystal defect is never generated by a method wherein a groove is formed between an element region of the surface of a semiconductor substrate and other element region of the surface, the interior of the groove is filled with a polycrystalline or amorphous silicon layer insulated electrically from the substrate and the surface of the groove is coated with an insulating material film adhered by deposition. CONSTITUTION:A mask is formed on a P-type single crystal Si substrate 1 by a photolithography, an isolation groove is made by a selective ion etching(RIE) method and the surface of this groove is thermally oxidized to form an SiO2 film 2. When a polycrystalline silicon layer 3 is grown by deposition by a reduced CVD method, the deposition is completely proceeded isotropically. Therefore, the groove not only is completely filled but also the final surface of the layer 3 also becomes almost flat. When this layer 3 is etched back by an RIE method, a state that the layer 3 is left only in the groove is obtained. Moreover, an SiO2 layer 4 is applied on the whole surface of the substrate by a CVD method, subsequently, a selective etching is performed by a normal photolithography and an RIE method and an SiO2 layer 4' is left only on the upper part of the groove. Thereby, a U-shaped groove isolation structure is realized.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to isolation between elements in a semiconductor integrated circuit board, particularly isolation between elements in which a U-shaped groove is filled with an insulated material. Aiming at avoiding distortion in the substrate crystal during insulation treatment, the method for manufacturing a semiconductor device of the present invention includes a step of forming a groove between an element region and another element region on the surface of the semiconductor substrate; The method includes the steps of filling the inside of the groove with polycrystalline or amorphous silicon that is electrically insulated from the substrate, and covering the surface of the silicon filled in the groove with a deposited insulating material film. Ru. [Industrial Application Field] The present invention is applied to isolation between elements in a semiconductor integrated circuit board.
It involves isolation between elements in the form of filling a U-shaped trench with an insulating material or an equivalent material.

When forming an integrated circuit by fabricating various elements on a semiconductor substrate, it is necessary to electrically insulate the elements. Regarding the isolation structure between the element forming layer and the substrate provided on the bottom surface, there are not very strict restrictions on the thickness occupied by the isolation region, but for isolation between element regions, that is, isolation between elements, it is necessary to have a sufficient isolation function. In addition to being required to be of great value, it is also necessary that the area occupied be small.
Among element isolation methods, those using pn junctions are less commonly used because the undesirable effects of junction capacitance become more significant as integration density increases, and instead,
Inter-element insulation isolation, in which trenches are dug between element regions and filled with insulating material, is increasingly used.

In recent years, with the development of etching techniques that proceed in only one direction, such as reactive ion etching (RIE), it has become possible to dig trenches with a U-shaped cross section that are deeper than the opening width. Inter-element isolation is now performed by filling this with an insulating material. This type of element isolation is U
This is called groove separation.

On the other hand, techniques for filling trenches with insulating materials initially included methods such as oxidizing the substrate itself and depositing oxides, but later, low-pressure CVD methods were used to fill the trenches with insulating materials. A technique for depositing crystalline silicon (Si) has been developed, and it has been considered to use this technique to fill isolation trenches. In other words, it is not necessary to fill the entire isolation trench with only an insulating material, and even with a conductive material such as St.
Based on the idea that if it is surrounded by an insulating material, it can be used as a filling material, so the inner wall of the trench is oxidized to form an insulating film, filled with poly-Si, and then the surface is oxidized to enclose the poly-Si. It was started. ? Prior Art and Problems to be Solved by the Invention] One of the most widely used insulation isolation technologies today is the use of an etching method that progresses in only one direction, such as reactive ion etching (RIE), to After digging a trench in the shape of a letter and oxidizing the inner wall of the trench to form an insulating film, the trench is filled with silicon deposited using a method with excellent coverage such as low-pressure CVD, and the surface is oxidized. This is used to insulate poly-Si. FIG. 5 schematically shows the cross-sectional structure of the insulation isolation region. 1 is a Si substrate, 2 is a SiOz film formed on the inner wall surface of the groove, 3 is polySt, and 5 is an SiO2 layer covering the surface of polySi. S on the surface of this body St
The iO2 layer 5 is formed by thermal oxidation, but due to the increase in volume due to the oxidation of Si, stress is generated in the element region and crystal defects are generated.

Since defects occurring in the element region deteriorate the characteristics of the element and lower the manufacturing yield of integrated circuits, a processing method that does not generate defects is required.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming U-groove isolation that does not cause crystal defects, thereby providing a method for forming integrated circuits with high yield.

? Means for Solving the Problem] In order to achieve the above object, the method for manufacturing a semiconductor device of the present invention includes a step of forming a groove between an element region and another element region on the surface of a semiconductor substrate, and a step of forming a groove in the groove. The steps include a step of filling the groove with polycrystalline or amorphous Si that is electrically insulated from the substrate, and a step of covering the surface of the St filled in the groove with a deposited insulating material film.

FIG. 1 schematically shows the cross-sectional structure of the U-groove isolation formed by the method of the present invention.

In the cough diagram, 1 is the Si substrate, 2 is the SiO film, and 3 is the poly-Si
, and 4 is SiO■ formed adhesively by a deposition method.
It is a layer.

Further, in the second aspect of the present invention, as the step of covering the surface of the St filling the groove with a deposited insulating material film, etching back is performed to such an extent that the surface of the Si sinks into the groove, and then the step of An insulating material film is deposited on the entire surface, and an anisotropic etching process is performed to leave the insulating material film only on the silicon in the groove.

[For production]

In the method of the present invention, since the poly-Si in the trench is not thermally oxidized, strain due to volume expansion does not occur, and crystal defects do not occur in the element region.

Therefore, an element formed on a substrate subjected to insulation isolation by the method of the present invention has good characteristics, and the manufacturing yield of integrated circuits is improved.

〔Example〕

FIGS. 2(a) to 2(d) are schematic cross-sectional views showing steps of an embodiment of the present invention corresponding to claim (1). Hereinafter, the steps of this embodiment will be explained with reference to the drawings.

(a) As shown in the figure, is it a p-type single crystal with a resistivity of 10Ωcm? Forming a mask on the i-substrate 1 by photolithography,
A trench with a width of 1 μm and a depth of 5 μm is dug by RIE. This is thermally oxidized to form a SiO2 film 2 with a thickness of 1000 wafers.

When poly-SiN is deposited and grown to a thickness of 1 μm using the low-pressure CVD method, the deposition progresses completely isotropically, so
Not only is the groove completely filled, but the final polySt surface is also almost flat.

When this is etched back at tE, a state is obtained in which poly-Si3 remains only in the grooves, as shown in figure Φ).

Thereon, a Sing layer 4 is deposited over the entire surface of the substrate by CVD. This state is shown in figure (C).

Next, selective etching is performed using conventional photolithography and RIE, and S is etched only on the upper part of the groove, as shown in (d).
The iO layer 4' is left.

Through the above processing, the U-groove isolation structure shown in FIG. 1 is realized.

Moreover, FIGS. 3(a) to 3(C) are schematic cross-sectional views showing the steps of the second embodiment of the present invention corresponding to claim (2).

? Below, the steps of the second embodiment will be explained with reference to the drawings. (a) The figure shows a state where poly-Si3 is left only in the groove by the same process as in the first embodiment, l is the Si substrate, 2 is the S
It is an iOz film. In this embodiment, strong etch-back is performed so that the surface of the burr St is sunk into the groove.

Figure (b) shows a state in which a SiOt layer 4 is deposited on this by the CVD method, and when etched back to the substrate surface, the top surface of the poly-Si in the groove is removed as shown in figure (c). is Si
A state covered with the O2 layer 4' is achieved.

In this second invention, since the process of leaving SiOzll4' is performed in a self-aligned manner without relying on photolithography, it is possible to realize a U-groove isolation structure in a narrower area.

FIGS. 4(a) to 4(e) are schematic cross-sectional views showing the steps of another embodiment of the second invention, that is, the third embodiment. below,
This will be explained with reference to the drawings.

In this embodiment, before digging a trench, a SiN film 11 of 1000 layers, 2000 to 30
00 large? A second Si layer 12, a second SiN film 13 with a thickness of 1000, and a PSG layer 14 with a thickness of 1 μm are sequentially deposited. Among these deposited layers, the two SiN films were provided as stoppers for the RIE process in the etch-back process, and although their explanation is omitted in each of the above embodiments, they are necessary. It is used depending on the situation. In this embodiment, the grooves are formed by the following process.

First, the PSG layer 14 is selectively etched by RIE using a resist pattern (not shown) formed by photolithography as a mask, and a window is opened in the SiN film 13 using the remaining PSG layer as a mask.

Furthermore, windows are similarly opened in the polySt layer 12 and the SiN film 11, and RIE processing is selectively performed through these windows to expose the substrate 1.
dig a trench. This situation is shown in the figure.

After removing the PSGjl, the substrate is thermally oxidized to cover the inner wall of the groove with a SiO film, and polyS is coated by low pressure CVD.
Deposit the i-layer. The thickness of the poly-Si layer is usually 172 to 1 times the width of the groove.

This is etched back by RIH to leave a bulge Sil6 inside the groove, but at this time the height of the poly-Si surface is made to match the height of the Si surface of the substrate.

This state is shown in figure (C).

Subsequently, a SiOz layer 16 is deposited by CVD and etched back. In this process, the second SiN film 13 functions as a stopper, so that S i O z on the SiN film
If the etching is stopped when all is removed, (
d) The state shown in the figure is reached.

Furthermore, if the SiN film is removed and the poly-Si layer is removed by performing RIE under conditions that preferentially etch poly-Si, (
e) As shown in the figure, the poly in the groove is completely covered with Sing, and a U-groove isolation structure is completed.

According to the process of the embodiment shown in FIG.
Since the necessary thickness of nt can be reliably left, the effect of isolation between elements becomes more reliable.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to form a U-groove isolation structure without causing stress in the element formation region of a semiconductor substrate, so that the deterioration of the characteristics of integrated circuit elements can be significantly reduced. , the manufacturing yield of integrated circuits is improved.

[Brief explanation of drawings]

FIG. 1 is a schematic cross-sectional diagram showing the structure of an element isolation region according to the present invention, FIG. 2 is a schematic cross-sectional diagram showing the steps of the first embodiment of the present invention, and FIG. 3 is a schematic cross-sectional diagram showing the process of the first embodiment of the present invention. 4 is a schematic cross-sectional view showing the process of the third embodiment of the present invention. FIG. 5 is a schematic cross-sectional view showing the structure of a conventional element isolation region. At? is a Si substrate, 2 is a SiO film, 3 is a poly Si14.4' is a CVD-SiOz layer, 5 is a thermally oxidized SiO film, 10 is an St substrate, l1 is a StN film, 12 is a poly-Si layer, and 13 is a poly-Si layer. 2 is a SiN film, 14 is a PSG layer, 15 is a thermally oxidized SiCh, 16 is a poly-Si layer, and 17 is a C V D Si O z layer. FIG. 1 is a schematic cross-sectional view showing a conventional device isolation structure. FIG. Schematic cross-sectional diagram showing the steps of the third embodiment (Part 1) Schematic cross-sectional diagram showing the steps of the second embodiment of the present invention Schematic cross-sectional diagram showing the steps of the third embodiment of the present invention Figure (Part 2)

Claims (2)

[Claims] (1) A step of forming a groove between an element region and another element region on the surface of a semiconductor substrate, a step of filling the groove with polycrystalline or amorphous silicon electrically insulated from the substrate, and the groove 1. A method for manufacturing a semiconductor device, comprising the step of: coating the surface of silicon filled with silicon with a deposited insulating material film. (2) A method for manufacturing a semiconductor device according to claim (1), comprising:
After filling the trench with polycrystalline or amorphous silicon, the surface of the silicon in the trench is submerged below the surface of the semiconductor substrate or a layer of material deposited on the surface forming the edge of the trench. Then, by depositing an insulating material film on the entire surface of the substrate and leaving the insulating material film only on the silicon in the groove by anisotropic etching treatment, the surface of the silicon filling the groove is 1. A method of manufacturing a semiconductor device, comprising: covering the semiconductor device with an insulating material film.