JPH02235374A - Testing method of nonvolatile semiconductor memory - Google Patents

Abstract

PURPOSE:To improve test capability by judging whether a device is acceptable, based on the difference of the upper limit value and the lower limit value in a power supply operation region before and after stress acceleration test. CONSTITUTION:For example, in the case of measuring an EPROM, the upper limit value and the lower limit value of a power supply voltage at an access time Ta for testing are written on an EPROM. The upper limit value and the lower limit value in a power supply operation region after stress acceleration test are compared with those values before stress acceleration test. When the difference is larger than a certain judgement value, the tested PROM is judged as a defective unit. Thereby, the screening of defective units is enabled by short period stress acceleration test, so that the testing cost is reduced by shortening the test time, and test capability can be increased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application in Industry 5] The present invention relates to a data retention characteristic test of a nonvolatile semiconductor memory.

[Conventional technology]

FIG. 4 is a flowchart showing a data retention characteristic test of an EPROM as an example of a conventional data retention characteristic test of a nonvolatile semiconductor memory. In the figure, (81)
．． (83) and (84) are steps.

The EPROMIc will be explained below as an example.

Next, the effect will be explained. Step (S1) in Figure 4
We conducted a write test and a read test at
Test whether the EPROM under test is writable and readable.

Next, a stress acceleration test in step (S3) is performed, and stress is applied to the EPROM to be measured. The accelerated stress test in step (S3) refers to burn-in and high-temperature storage.Finally, a readout test is performed in step (S4), and the data read in step (81) is confirmed in step (83).
A stress acceleration test is performed to check whether bits are volatile or bits are not standing.

Here, bit volatilization and bit rising will be described in detail using FIG. FIG. 5 is a characteristic diagram showing changes in the power supply operating range due to the accelerated stress test in step (83). The upper limit value in the power supply operation region when written to the EPROM under test in step (81)
．． The lower limit value is set to Vca minφ.

good! The device has the maximum power supply operating range Mac in the readout test of the accelerated stress test in step (S3).
max 1 is the same as or hardly different from Vcc maxφ, but when the bit volatilizes due to the accelerated stress test in step (S3), that is, the electrons in the 7 rotating gates of the memory cell of the bit of data 1'0'' are extracted. Defective product 1 and defective product 2 shown in Figure 5 have Vcc
max l decreases by Vca mawφEshi - 1ru〇Also,
In a non-defective device, the 'source movement f\. Lower limit value of @ area ¥cc min l is Vcc m
The step (S
When electrons enter the floating gate of the memory cell of the bit with data 91'' in the accelerated stress test of 3), a defective product 3 (as shown in the defective product number, Vcc min l is Vcominφ) is generated. To increase.

In order to screen for such defective products that cause bit volatilization and pit formation, in the readout test in step (S4), the "adjustment test" in step (S4) was performed with a certain power supply '4 EE Vcc max▲ and Vacmin^. , devices that could not be read at this voltage are considered memorial items.

[Problem to be solved by the invention]

Conventional testing methods for non-volatile semiconductor memories only test at certain points as described above, so severe bit volatility defects such as defective product 1 shown in Figure 6 or severe defects such as defective product 3 can occur. The bit failures of 2 can be screened by stress acceleration test at time t1, but in order to screen for mild bit volatile defects such as defective product 2 or mild bit failures such as defective product 4, it is necessary to perform a stress test at time t2.
There were problems such as a long test time because the accelerated stress test was required.

This invention was made in order to solve the problems described above, and its purpose is to shorten the stress acceleration test time without impairing the screening effect for bit volatile failures and bit rising failures.

[Means to solve the problem]

The nonvolatile semiconductor memory testing method according to the present invention includes:
It measures the first and lower limits of the power supply operating range before and after the accelerated stress test, and writes the upper and lower limits of the power supply operating range before the accelerated stress test to each nonvolatile semiconductor memory under test. .

[Effect]

In this invention, the first limit value and the lower limit value of the power supply operating range before and after the accelerated stress test are measured, the difference between them is determined, and it is determined whether the difference is smaller than a certain judgment value, and the To determine whether a nonvolatile semiconductor memory is a good product or a defective product.

(Embodiment) An embodiment of the present invention will be described below with reference to the drawings.Here, an EFROM will be explained as an example. FIG. 1 is a flowchart showing a data retention characteristic test of a nonvolatile semiconductor memory. , (81) ~
(S8) is a step. In step (S1), a write test and a read test are performed to test whether the w11NlII fixed EPROM can be written to and read from. Next, in step (82), the first limit value and lower limit value of the power supply operating range are measured and the values are written into the EPROM to be measured.

Figure 2 (11). (t)) is a characteristic diagram showing an example of the distribution of the power supply operating region of the EFROM under test; (a) is before the stress acceleration test in step (S3);
) after accelerated stress testing. In Figure K, the horizontal axis is the access time, and the vertical axis is the power supply voltage Vac. Then, T. The upper and lower limits of the power supply voltage Vca at are respectively Vca maxφ
．． At step 0 (82) where Vca winφ is set, Vca mazφ and Vaa mi
Insert nφ.

In step (S3), an accelerated stress test is performed.

A read test is performed in step (84), and step (
The data written in step 82) is tested to see if it has been destroyed by the accelerated stress test in step (S3). In step (85), the first limit value and lower limit value of the power supply operating region written in step (82) are read from the EFROM under test.In step (S6), the calculation source operating region after the stress acceleration test in step (83) is read. An example of the distribution of the power supply operating range at this time is shown in Figure 2 (b).The upper and lower limits of the power supply voltage Vaa at the access time 'raK to be tested are respectively Vcc. ma
If Il, Vco min l, step (8
6) Mac max l and Voc win
Measure l.

In step (S7), the difference ΔVac between the upper limit values of electric power 8Evca before and after the stress acceleration test in step (S3) is determined.
Find the difference ΔVcc win between the max and lower limit value. In step (8B), ΔVcc max, ΔVcc min
However, a certain judgment value VcO llmX ``e'/cozin
Determine whether it is smaller than m. If there is a large difference between these judgment values, the EPROM to be measured is determined to be a defective product.

Hereinafter, the test method according to the present invention will be explained in detail. Here, burn-in K will be explained as an example of the accelerated stress test in step (S3).

At step ($2) in Figure 1, the upper limit value V of the power supply operating region
cc maxφ. Measure the lower limit value Vac minφ,
At the same time, the measured value is written into the memory cell of the EFROM to be measured.

Regarding this memory cell, FIG. 3 shows an example of 2 Bytes.
Indicates when used. FIG. 3 is a conceptual diagram of the memory looking at the first limit value and lower limit value of the power supply operating range before the stress acceleration test in step (83). That is, 1 limit value Vcc
For maxφ, a certain f! It is ranked into 16 levels based on width, and the data in each rank is made to correspond. Next, the data of the corresponding rank is I By
Write to the teth lower 4 bits. FIG. 3 shows, as an example, a case where the rank of Vcc muxφ corresponds to the illustrated "E". Also, l Byte's throne 4 b
It looks at the inverted data of the lower 4 bits, and even if these wandering data change due to burn-in, it can be checked. In this level 1, wAE“
The inverted data ``E'', ie, ``1'' is written. In FIG. 3, VcamaX▲ is the maximum power source Kameda of the read test in step (S1).

Similarly, for the lower limit value Vac minφ, vtti is entered using the 2nd Byte. In the example in Figure 3, 2 B
Data 'R3#' is written into the y-th lower 4t)it, and inverted data 13 of the lower 4 bits, that is, 1C" is written into the 1st 4 bits. Note that in FIG.
win A is the minimum power supply voltage for the read test in step (S1).

In step (S5), the rank of the voltage value written in step ($2) is read out. At this time, for the 2 bytes of the upper limit and lower limit of the voltage value, 5th place 4 1
) it is the inverted data of the lower 4 t) it. Here, if the upper 4 m) it is not the inverted data of the lower 41) it, the measured EPROM is determined to be a defective product.

In step (S6), Vca wax l and Vac
min 1 is measured and made to correspond to the data of the corresponding rank according to the rank classification shown in the tjX3 diagram.

In step (S7), Vac maxφ and Vccminφ read from the fixed EFROM and step (S
Vac mawl and Vcomi determined in 6)
Using n l, the difference between the upper limit values ΔVcam&X and the difference between the lower limit values ΔVcc min are omitted. The value obtained here is not the difference between the measured values, but the difference when the measured values are ranked.

In step (88), ΔVca max, ΔVco
min is a certain judgment value Vac wax B , Vcc
Determine whether it is smaller than min l. Here, if either the difference between the voltage value and the limit value or the difference between the lower limit value is larger than the judgment value, the upper limit value Vca max l of the power supply operating region after the stress acceleration test in step (S3) is determined in step (S4). Maximum power supply voltage for read test of Vca ma
xh, and the lower limit value Vca min 1 of the snow source operating head area after the stress acceleration test in step (S3) is 9 in step (S4)! Minimum power supply voltage EV for protrusion test
Even though it is smaller than ac min s, the rate of change of the upper limit or lower limit of the power supply operating range due to the accelerated stress test at the fixed time step (S3) is larger than the judgment value, so the EPROM under test is judged to be defective. Ru.

Therefore, in addition to the conventional step (S4) read test, since the judgment is based on the degree of change in the upper and lower limit values of the power supply # production area, mild defective products such as the conventional example 2 shown in Fig. 5K are tested. In order to screen for bit volatile defects and bit failures that change rapidly such as defective product 4, an accelerated stress test at step (S3) at time t2 is necessary, but for example, a short step (S3) at time t1 is necessary. The accelerated stress test in S3) also makes it possible to screen for defects by measuring changes in the first and lower limits of the power supply operating range.

In the above embodiment, burn-in was described as an example of the accelerated stress test in step (S3), but the same effect can be obtained even in high-temperature storage K.

Furthermore, in the embodiment L, the upper limit value Vco mawφ. In order to write the lower limit value Vco minφ, the measured EPR
Although OM memory cells are used, a redundant memory such as Ili:FROM may also be used, and the same effect as in the above embodiment can be obtained. In that case, Mac maxφ, Vcc mi in step (82) and step (S5)
Writing and reading of nφ is performed on the EFROMIC under test.
This is done by providing a test mode.

In addition, the embodiment described in t can also obtain similar effects in the data retention characteristic test of EEFROM.

Furthermore, the above-mentioned embodiment has the effect of screening for bit loss in the data retention characteristic test in the blank state of the OTFROM.

〔Effect of the invention〕

As described above, according to the present invention, by writing the upper and lower limit values of the power supply operating range before the accelerated stress test into the non-volatile semiconductor memory under test 17K, changes in the power supply operating range before the accelerated stress test can be detected. Since K is set to be measurable, it becomes possible to screen for defects through a shorter accelerated stress test, which has the effect of reducing test costs and increasing testing ability by shortening the time.

[Brief explanation of the drawing]

1 to 3 relate to an embodiment of the nonvolatile semiconductor memory testing method according to the present invention, in which FIG. 1 is a 7-row chart diagram showing a data retention characteristic test, and
l3 (a) and (b) are characteristic diagrams showing distribution examples of the power supply operating range before and after the stress acceleration test, and Figure 3 is a conceptual diagram of the memory in which the upper and lower limit values of the power supply operating range before the stress acceleration test are written. It is. FIG. 4 is a flowchart showing a conventional data retention characteristic test of non-volatile semiconductor memory;
FIG. 5 is a characteristic diagram showing changes in the power supply operating range due to a conventional stress acceleration test. In the figure, (81) to (SB) are steps. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. Figure 1

Claims (1)

[Claims] In a data retention characteristic test of a nonvolatile semiconductor memory that has a floating gate and a control gate on a semiconductor substrate, the upper and lower limits of the power supply operating region were measured and compared before and after the stress acceleration test during the data retention characteristic test. , a nonvolatile semiconductor memory testing method characterized by determining pass/fail based on the difference.