JPH02234467A - Dynamic semiconductor storage device - Google Patents

Abstract

PURPOSE:To reduce short-circuits of bit lines and improve the fraction nonfefective by a method wherein the window-shaped apertures of connection electrodes of the bit lines are provided in a facing electrode and the apertures of the connection electrodes are eliminated from the circumference of the facing electrode so as to provided the flat shape of the facing electrode. CONSTITUTION:A common facing electrode 14 is provided for a plurality of capacitors which respective transfer gate elements have. A plurality of the window-shaped apertures of connection electrodes 2 of bit lines 1A-1E are provided in the facing electrode 14. The apertures of the connection electrodes 2 are eliminated from the circumference F of the facing electrode 14 so as to provide the flat shape of the facing electrode. Therefore, a minimum punched pattern allowable dimension, which is a gap between the side edge of the connection electrode 2 and the side edge of the adjoining bit line 1C, can be avoided and, further, the circumference of the facing electrode does not cross the parts near the connection electrodes 2 where large differences in level exist. With this constitution, short-circuits of the bit lines can be reduced and the fraction nondefective can be improved.

Description

[Detailed Description of the Invention] [Summary] Regarding the electrode shape of a capacitor in a DRAM, the causes related to the counter electrode that reduce the non-defective product rate are removed,
In order to improve the quality of products, the bit line and word line are perpendicular to each other, a transfer gate element having a channel perpendicular to the bit line is provided, and a capacitor is placed below the bit line. A dynamic, square type semiconductor memory device, wherein a counter electrode is provided in common to a plurality of capacitors included in each of the transfer gate elements, and the counter electrode has an opening of the connection electrode of the focus line formed in the inside thereof. The opening of the connection electrode has a planar shape of the counter electrode that does not exist at the periphery of the counter electrode.

[Industrial Field of Application] The present invention relates to a dynamic semiconductor memory device, particularly to improving the electrode shape of a capacitor.

D R A M (Dynamic Rando)
m Access Memory) is the mainstay of LSI memory and has an extremely large capacity, but 64
It is predicted that it will be extremely highly integrated with M bint 256M. In such large-capacity DRAMs, further increasing the density is an important issue, and the rate of good products (manufacturing yield)
There is a need to maintain or improve this.

[Conventional technology]

FIG. 2 shows a transparent plan view of a conventional DRAM cell section, and this figure is a transparent plan view showing a bit line and a counter electrode of a capacitor provided in each transfer gate element. Five bit lines IA, IB. IC,
The LD and IE are arranged parallel to the X direction, and the connection electrodes 2 connected to each bint line are arranged in a zigzag pattern with the adjacent bint lines, and this connection electrode is connected to the lower connection electrode contact part. 3 (Illustrated transparently)
It has a connected structure. In this way, the connection electrode 2
The reason why the bit lines are provided in a zigzag shape is to increase the density of the bit lines and to prevent the bit lines from shorting each other, which was devised from the viewpoint of lithography technology.

The other symbol 4 in FIG. 2 is a counter electrode, and F indicates the periphery of the counter electrode. In this DRAM, since the counter electrode 4 serves as a common electrode connected to a power supply or grounded, the memory cell section is divided into a plurality of blocks, and a common electrode is used for a large number of transfer gate elements as shown in the figure. The electrodes are made using Moreover, the example DRAM
Since the structure is such that the bit line is disposed above the capacitor, the counter electrode has a shape in which a number of windows opening the connection electrode 2 of the bit line are scattered.

FIG. 3 shows the AA cross section of FIG. 2, in which ID is a bit line, 3 is a connection electrode contact part. 4 is a counter electrode of capacitor CP, 5 is a P-type silicon substrate, 6 is an n-type impurity region (source region or train region). 7 is a field insulating film, 8 is an insulating film including other cover insulating films (the insulating films are shown in matte finish), and FIG. 3 is a cross section showing two transfer gate element parts.

As mentioned above, the DRAM of this example has a structure in which the word line tag 7 bit line BL is perpendicular to the word line, the bit line BL is provided at the top, and the capacitor CP is arranged at the bottom. This structure has the advantage that there is no need to finely pattern the scratches 4 individually within the cell array, and that the focus lines can prevent mutual interference such as coupling.

[Problem to be solved by the invention]

By the way, a DRAM with such a structure has a capacitor CP.
Since it is a stack type, it is possible to increase the storage capacity by stacking it three-dimensionally, but on the other hand, the aspect ratio (the ratio of the bottom area to the height) becomes poor, which increases bit line short circuits and reduces the yield rate. .

Figure 4(a). (b) is a diagram illustrating the conventional problem (I), and (a) is a plan view of the Q portion including the periphery F of the counter electrode surrounded by the broken line in Figure 2. is that B
This is a cross-sectional view of B, and the same parts as in FIG. 2 are given the same symbols, but the other IOBs and IOCs are resist film patterns. That is, FIG. 4 is a diagram in the middle of the manufacturing process just before depositing the bit line 1, coating it with the resist film pattern 10B, IOC, and patterning the bit lines IB and IC. The width n portion is the minimum permissible punching pattern dimension based on phosphorography technology, and this portion is the gap between the side edge of the connection electrode 2 and the adjacent bit line lCO side edge. However, since this part is close to the connection electrode 2 with a large depression and a large step difference, a residual resist film r is likely to be formed in that part, and if this happens, the bit line IB and the peripheral edge F of the counter electrode 4 are easily formed. A short circuit with the bit line IC occurs, reducing the yield rate.

Next, FIG. 5 is a diagram explaining the conventional problem (n), and this figure shows the next process diagram of the manufacturing process shown in FIG. 4(b) of the same Q part as FIG. FIG. 6 is a diagram showing a step in the process of vertically dry etching a bit line using the resist film pattern as a mask. For example, if the bit line is made of polycrystalline silicon/
When creating a two-layer structure made of tungsten silicide, fluorine-based gas or active ion etching (R
Patterning is performed by the IE) method, but at that time,
Etching residue d is likely to be formed at the illustrated position of the periphery F, and this is also because this portion is close to the connection electrode 2, which has a large depression and a large step difference. This etching residue d
occurs along the periphery F of the counter electrode 4 (a part of which is indicated by a thick line in FIG. 2), which has a large step, and the focus line IB and the bit line IC are short-circuited in the same way as in the previous step. ,
This will reduce the rate of non-defective products.

In this way, if the connection electrode exists on the peripheral edge F of the counter electrode 4, the above-mentioned resist film remains and etching residue are likely to be generated, which will reduce the yield rate. The present invention aims to eliminate the causes related to the counter electrode that reduce the rate of non-defective products, and improve the rate of non-defective products.
We propose AM.

[Means to solve the problem]

The problem is that, as shown in the embodiment of FIG. 1, the bit line and the word line are orthogonal to each other, a transfer gate element having a channel perpendicular to the bit line is provided, and a capacitor is disposed below the bit line. A dynamic semiconductor memory device having a structure in which a counter electrode 14 is provided in common to a plurality of capacitors included in each of the transfer gate elements, and the counter electrode 14 is provided with an inner surface of the focus lines IA to IE. Connection electrode 2
This problem is solved by a DRAM having a planar shape of the counter electrode, which has a plurality of window-shaped openings, and the opening of the connection electrode does not exist on the periphery of the counter electrode.

[Function] That is, in the present invention, the openings (connection openings) of the connection electrodes do not coincide with the peripheral edge F of the counter electrode, and all the connection openings are provided inside the counter electrode in the form of windows. that way,
It is possible to avoid the gap between the side edge of the connection electrode 2 and the side edge of the adjacent bisotholine IC, which is the minimum permissible dimension of the punching pattern. It does not cross adjacent parts, so
It is possible to reduce bit line short circuits and improve the non-defective product rate.

〔Example〕

Examples will be explained in detail below with reference to the drawings.

FIG. 1 is a transparent plan view of the DRAM cell section according to the present invention, showing the same part as in FIG. The bit line LA. IB, IC, 10, and IE are arranged in parallel to the X direction, and connection electrodes 2 connected to each bit line are arranged in a zigzag pattern with the adjacent bit line. In addition, the counter electrode 14 is one block of counter electrodes (
common counter electrode of the capacitor), the counter electrode 1
There is no connection electrode 2 on the peripheral edge F of 4, and all the connection electrodes 2 form window-like openings inside the counter electrode 14.

In this way, it is possible to avoid a part where the peripheral edge F of the counter electrode 14 has a large step and the bit line gap is the minimum permissible punching pattern dimension n, and the peripheral edge F can be patterned in a straight line. be able to.

Therefore, the above-mentioned resist film residue r and etching residue d can be removed from the periphery of the counter electrode 14 to reduce bit line short circuits. Note that the etching residue d is also formed on the periphery of the internal window-shaped opening (partially shown by the bold line in Figure 1), but this part cannot be short-circuited with the adjacent bint wire. Therefore, the problem of lowering the non-defective product rate does not occur.

In addition, the peripheral edge shape of the conventional counter electrode is often determined by automatic design, but by adding the restriction conditions for the peripheral edge part to the design data of the counter electrode, the position of the peripheral edge of the counter electrode according to the present invention can be easily determined. It is possible to control the shape and the shape, thereby easily reducing short circuits of the focus wire without changing the manufacturing method.

[Effects of the Invention] As is clear from the above description, if the semiconductor device according to the present invention is configured, short circuits in bit lines can be easily reduced without changing the manufacturing method, and the yield rate of non-defective products can be improved. There is an effect that can be done.

[Brief explanation of the drawing]

FIG. 1 is a transparent plan view of a DRAM cell section according to the present invention, FIG. 2 is a transparent plan view of a conventional DRAM cell section, FIG. 3 is a cross-sectional view along line AA of FIG. 2, and FIG. 4 is a conventional problem. FIG. 5 is a diagram explaining the conventional problem (II). In the figure, IA, IB, IC, 10, IE, 1 is a bit line 2 is a connection electrode, 3 is a connection electrode contact part, 4 is a counter electrode, 5 is a p-type silicon substrate, 6 is an n-type impurity region (source region or drain region)
, 7 is a field insulating film, 8 is an insulating film, 10B, IOC is a resist 1/film pattern, l4 is a counter electrode (a counter electrode according to the present invention), F is a periphery of the counter electrode, and a hole is a word line (gate electrode). cp is the capacitor n is the minimum permissible punching pattern dimension, r is the remainder of the resist film, and d is the etching residue. Figure 2 Figure 1 Figure 3

Claims (1)

[Claims] A dynamic semiconductor memory having a structure in which a bit line and a word line are orthogonal to each other, a transfer gate element having a channel perpendicular to the bit line is provided, and a capacitor is disposed below the bit line. The apparatus includes a common counter electrode for a plurality of capacitors included in each of the transfer gate elements, and the counter electrode has a window-like opening for the connection electrode of the bit line inside, and the connection electrode 1. A dynamic semiconductor memory device characterized in that a counter electrode has a planar shape in which an opening of the electrode does not exist at a periphery of the counter electrode.