JPH02234464A - Semiconductor memory element - Google Patents

Abstract

PURPOSE:To eliminate the possibility of open-circuits and short-circuits and improve the accuracy of patterns by a method wherein wirings are made of the same material as one of the electrodes of a capacitor and formed in the same process as the electrode. CONSTITUTION:A film made of the same material as one of the column-shaped electrodes of a capacitor is formed in the same process as the electrode and wirings 12, 13, 112, 113, 12D and 112D between memory cell parts and peripheral circuits are made from the film. Therefore, the difference in level between the memory cell parts and the peripheral circuits produced by the film thickness of the one of the electrodes is eliminated and the substrate surface becomes almost flat, so that, in an electrode forming process, the pattern transcription accuracy of photolithography can be improved compared with with case when the difference in level exists. Further, one wiring layer is added to each wiring layer in the peripheral circuits. With this constitution, the possibility of short- circuits and open-circuits in the metal wirings can be eliminated and the pattern accuracy can be improved and, further, the degree of freedom of wiring design can be improved.

Description

[Detailed Description of the Invention] Industrial Application Field> The present invention relates to a semiconductor memory device, and more specifically, to a dynamic random access memory (hereinafter referred to as rD).
It is called RAMJ. ) regarding the wiring structure.

BACKGROUND ART In DRAMs, the degree of integration is being improved in order to increase storage capacity. For this purpose, it is necessary to reduce the size of memory cells, which are the storage units of DRAM.

However, in order to prevent soft errors caused by radiation and to ensure a sufficient S/N ratio, it is necessary that the capacitance for storing charges in the memory cell be at least a certain minimum value. For this reason, it is becoming increasingly difficult to form the above-mentioned charge-accumulating capacitive element on the surface of a semiconductor substrate, and it is becoming increasingly difficult to form a capacitive element on the surface of a semiconductor substrate. Memory cells with three-dimensional structures are becoming more common.

And, prior to filing this patent application, the present applicant
In order to obtain a large storage capacity in a small area in a so-called stacked memory cell in which the above-mentioned capacitive element is formed on a transistor, we proposed a semiconductor memory element having a memory cell portion with a structure as shown in FIGS. 13 and 14. (Patent Application No. 63-227945). In FIG. 13, the area surrounded by a broken line M indicates the area occupied by one memory cell, and FIG. 14 shows a cross section thereof along line XIV-X. The semiconductor memory element is functionally composed of a transistor T and a capacitive element C, and is an AQ-S with a film thickness of 05 μm.
A bit line 25 made of i-alloy is provided at the top. The transistor T has a P-type silicon substrate l as a channel, and a word line I8 made of phosphorus-doped polysilicon having a thickness of 0.4 μl is provided on the channel l as a gate electrode via a gate oxide film l7. It also includes a drain region l9 formed by diffusing arsenic, and a source region 20 connected to the capacitive element C and formed by diffusing arsenic. Further, the capacitive element C is the transistor T.
A storage electrode (first electrode) 21 made of phosphorus-doped polysilicon connected to the source region 20 of the phosphorus-doped polysilicon, an insulating film 23 made of SiOx, and a plate electrode (second The electrodes 24 are formed so as to partially cover the word lines 18 and 118. Then, the film thickness of the storage electrode 2l is ~lμ
The shoulders are made thicker so that the cross section becomes columnar, and the ratio of the side surface to the electrode surface is increased, so that a large storage capacity can be obtained in a small memory cell area M. On the other hand, in the peripheral circuit provided on the surface of the P-type silicon substrate 1 and connected to the memory cell by wiring, the wiring is connected to the word line 18 and the bit line 25 without using the material of the storage electrode 21. Two-layer wiring, consisting of a gate wiring and a metal wiring, each formed using the same material and the same process, is used.

Problems to be Solved by the Invention> However, since the semiconductor memory element uses the two-layer wiring in the peripheral circuit section, the storage electrode 2l is placed at the boundary between the memory cell section and the peripheral circuit section. Since a step is created due to the thick film thickness, there is a risk that the metal wiring may be disconnected or shorted at this boundary. Further, due to the step difference, there is a problem that the pattern transfer accuracy of photolithography deteriorates in a step after forming the storage electrode 2I. Furthermore, since two-layer wiring is used, there is a problem that the degree of freedom in design is small.

Therefore, an object of the present invention is to eliminate the level difference between the memory cell and the peripheral circuit section, eliminate the risk of disconnection or short circuit of the metal wiring, improve pattern accuracy, and increase the degree of freedom in wiring design. An object of the present invention is to provide an improved semiconductor memory device.

<Means for Solving the Problems> In order to achieve the above object, the present invention includes a transistor and a capacitor formed on the surface of a semiconductor substrate, and at least one electrode of the capacitor having a columnar cross section. In the semiconductor memory element, the wiring includes a memory cell portion provided on the transistor, and a peripheral circuit portion connected to the memory cell portion on the surface of the semiconductor substrate by a wiring. It is characterized by being made of the same material as one electrode and formed in the same process.

Effect> Since the film made of the same material and formed in the same process as one electrode having a columnar cross section of the capacitor is used as the material for the wiring between the memory cell part and the peripheral circuit part, the above memory cell part There is no difference in level between the electrode and the peripheral circuit due to the film thickness of one of the electrodes. Further, since the base surface becomes substantially flat due to the elimination of the step, the pattern transfer accuracy of photolithography is improved in the step after the electrode formation, compared to the case where the step is present.

Furthermore, since the number of wiring layers is increased by one layer in the peripheral circuit section, the degree of freedom in design is increased.

Examples> The semiconductor memory device of the present invention will be described in detail below using examples. The semiconductor memory device of the present invention includes a memory cell portion formed on the surface of a P-type semiconductor substrate, and an Aiura type peripheral circuit of a so-called folded bit line type connected to the memory cell portion on the surface of the substrate by wiring. It has a section.

Since the memory cell section has the same structure as the memory cell section of the conventional semiconductor memory device shown in FIGS. 13 and 14, the explanation will be omitted, and the peripheral circuit section will be explained below.

FIG. 1 is a plan view showing a peripheral circuit section of a semiconductor memory device of the present invention, and FIGS. 2 and 3 are respectively ! 1111-11I! It is an IA sectional view. The area between broken line A and broken line B in FIG. 1 indicates the area occupied by one sense amplifier connected to a pair of bit lines 15 and 16 included in this peripheral circuit section.

This sense amplifier has the equivalent circuit shown in Figure 4.
Source regions 9.10 are connected in common and drain regions 7.
．． 8 are respectively connected to the bit lines 15.16, and the gate electrodes 5.6 are connected to the bit lines 1, 6.1 and 5, respectively, two n-channel transistors TI, T2, similar to TI, T2, Source area 109, llO
are connected in common, drain regions 107 and 108 are connected to the bit lines 1 5.1 6, respectively, and gate electrodes 105 and 106 are connected to the bit lines 1 6.1, respectively.
Two P-channel transistors connected to 5'r+
o+. It is composed of Ttot.

As shown in FIGS. 2 and 3, the n-channel transistors TI and T2 have a P-type well region 3 formed by diffusing boron in a P-type silicon substrate 1 as a channel, and
A gate electrode 5.6 made of arsenic-doped borin silicon is provided on each channel with a gate oxide film 4 interposed therebetween.

Further, the source region 9.10 and the drain region 7.8 connected to the bit line 15.16 are formed by diffusing arsenic, and the source region 9.10 is integrally formed as an arsenic diffusion layer. .

On the other hand, p-channel transistor T + o + + T
rot is an n-type well region 103 formed in a p-type substrate.
is a channel, and a gate oxide film 4 is formed on each channel.
Gate electrode 1 made of arsenic-doped polysilicon through
05,106. In addition, the source region 109,
Drain regions 107 and 108 connected to pit lines 110 and pit lines 15.16, respectively, are formed by diffusing boron, and the source regions 109 and 110 are integrally formed as boron diffusion layers.

Note: The drain regions 7.8 of the two n-channel transistors TIT2 and the bit line 15.16 are connected to a polysilicon film made of phosphorus-doped polysilicon with a film thickness of 1 μl through contact holes 11a and 1lb made in the first interlayer insulating film 11. The silicon wiring 12.13 and the drain region 7.8 are respectively connected, and the polysilicon wiring 12, 13 is connected to the second
The connection is made by connecting to the bit lines 15 and 16 through contact holes 14a and 14b formed in the interlayer insulating film l4.

On the other hand, the two p-channel transistors T Ial
*Ttoz drain regions 107 and 108 and bit line 1
5.1 6 connects the drain regions 107 and 108 to the polysilicon wirings 112 and 113 made of boron-doped polysilicon through the contact holes 11c and lld formed in the first interlayer insulating film 11, respectively, and The interconnections l12 and 1'l3 are connected to the bit lines 15 and 16 through contact holes 14c and 14d formed in the second interlayer insulating film l4.

The gate electrodes 5 and 6 of the n-channel transistors Tl and T2 and the bit line 16.15 are connected to the first interlayer insulating film 11.
The gate electrode 5.6 and the polysilicon wiring 13.12 are respectively connected through the contact holes 11ellr formed in the contact holes 14b, 14.
They are connected by connecting each through a.

On the other hand, the p-channel transistor T1.1T lo
The gate electrodes 105, 106 and the bit lines 16, 15 of t are connected to the contact holes 11g,
The gate electrodes 105 and 106 are connected to the polysilicon wirings 113 and 112 through Ilh, and the polysilicon wirings 113112 and the bit lines 16.15 are connected through the contact holes 14d and 14c, respectively.

Dummy polysilicon wires 12D and 112D made of boron-doped polysilicon are provided in the region between the memory cell portion and the peripheral circuit portion where the intervals between the polysilicon wires 12, 13, 112, and 113 are wide.

The peripheral circuit section is formed as follows.

■ First, as shown in Figures 6 and 7, a trench with a depth of 1.6 μm is formed in the P-type silicon substrate l, and boron is shallowly implanted into the bottom of this trench by ion implantation. Next, 100% SiS film was formed by thermal oxidation method, and then Si was deposited by LPGVD (low pressure chemical vapor deposition) method.
After depositing the ft film, the substrate surface is planarized by an edge-back method to form element isolation regions 2 (so-called BO
X method).

(2) In order to form an n-channel transistor TIT2 and a p-channel transistor T+o+rT+ot, a boron-doped p-type well region and a phosphorus-doped n-type well region 103 are formed by ion implantation. next,
After removing the masks of the active regions of the n-channel and p-channel parts forming each of the transistors and performing sacrificial oxidation, a gate insulating film 4 with a thickness of 150 layers is formed by thermal oxidation.

■ Next, deposit polysilicon with a thickness of 0.4 μm using the LPCVD method, and then deposit a layer of polysilicon with a thickness of 0.3 μm using the CVD method.
Deposit μI of SiOz. This two-layer film is patterned to form gate electrodes 5, 6, 105, and 106.

■ Phosphorus is dosed fi2X10l3ci-' into the n-channel part using the ion implantation method at an acceleration energy of 80KeV.
While implanting boron into the p-channel part, the acceleration energy I
A dose of ffil x l O "cc" is implanted at OKeV, and then the film thickness is reduced to 0.5 cm using the LPCVD method. A SiO film of 1Jix is deposited, and a spacer is formed on the side of each gate electrode by an etch-back method.

■Furthermore, arsenic is implanted into the n-channel part by ion implantation at 80 KeV, while B Ft is implanted into the p-channel part by 3 at 40 KeV.
Inject ×1015cF'. As a result, the n-channel section and the p-channel section can be
Transistors T I , T 2 , T having a DopedDrain structure (lightly doped drain)
+o+. Source region of T+ot 9, 1 0, 1 0 9
, 1 1 0 and drain regions 7, 8, 1 0 7,
Form 1 0 8. Note that the source regions 9 and 10
, 109 and 110 are each integrally formed.

(2) Further, as the first interlayer insulating film 1l, a Siot film is deposited to a thickness of 2000 by the LPCVD method.

As shown in FIG. 5, the n-channel transistors TI, T2 and the p-channel transistor T
Druin region 7, 8, 107, 1 of Hot, Tl (1;
Polysilicon wirings 12, 13, which are upper wirings,
, 1. Contact hole 1 for connecting to 12, 113
1a, 1 lb, l lc, I Id and contact hole 1
1i11j and contact hole 1 1f', 1 1e, 1
Open 1h, 1 1g.

Note that the first interlayer insulating film 11 is made of the same material as the first interlayer insulating film 11 of the memory cell shown in FIG.
form at the same time.

■ At this stage, the film thickness is 1.0μl in the memory cell part.
A storage electrode 2l is formed by depositing phosphorus-doped polysilicon and etching it into a predetermined pattern. At the same time, in this peripheral circuit section, as shown in FIGS. 9 and 10, n-channel transistor TI. Phosphorus-doped polysilicon wiring 12 in the n-channel portion including T2.
13 and dummy polysilicon wiring 12D are formed.

■ Next, as shown in FIG. 8, boron-doped polysilicon with a thickness of 1.0 μm was deposited on the p-channel portion.
It is etched and processed into a predetermined pattern to form boron-doped polysilicon interconnects 112, 113 and dummy polysilicon interconnects 112D.

■Finally, a SiO film with a thickness of 0.5μ is deposited as the second interlayer insulating film I4 by LPCVD and CVD, and after flattening by etchback, the polysilicon wirings 12, 13, 112, 113 Contact holes 14a, 14bl4c, and 14d are opened at predetermined locations on the top for connecting these to bit lines 15, 16. and,
An AQ-Si alloy having a thickness of 0.5 .mu.m is deposited, etched and processed into a predetermined pattern to form bit lines 15.16, resulting in the structure shown in FIGS. 1 to 3.

In this way, the storage electrode 2 of the memory cell is placed in the peripheral circuit section.
When polysilicon wirings 1 2, 1 3, 1 1 2, 1 1 3 and dummy polysilicon wirings 12D and 112D made of the same material as 1 and formed in the same process are provided, the difference is due to the film thickness of the storage electrode 21. There is no difference in level between the memory cell section and the peripheral circuit section. Furthermore, since the surface of the substrate becomes substantially flat due to the elimination of the step, the pattern transfer accuracy of photolithography is improved in the process after forming the storage electrode 2l, compared to the case where the step is present, and the pattern accuracy is improved. improves. Furthermore, since the number of wiring layers is increased by one layer in the peripheral circuit section, the degree of freedom in design is increased.

Further, as in another embodiment shown in FIGS. 11 and 12, contact holes L la, 1 lb, I lc,
IId, l le, I If', l Ig. 1 1h
, I fi. A film thickness of 0.1 is applied to IIj by sputtering.
When a barrier metal ll made of μl of TiN is provided,
As in the semiconductor memory device shown in FIGS. 1 to 3, P
It is no longer necessary to dope the polysilicon wirings 112, 113 and dummy polysilicon 112D in the channel portion with boron, and the polysilicon wirings 12, 13, 212, 21
3 and the dummy polysilicon wiring 212D can all be formed of phosphorus-doped borinsilicon.

Although each of the polysilicon wirings described above is doped with phosphorus, it is not limited to this, and may be doped with arsenic.

Effects of the Invention> As is clear from the above, the present invention includes a transnostar and a capacitor formed on the surface of a semiconductor substrate, and at least a part of one electrode forming a columnar cross section of the cavantor is connected to the transistor. In a semiconductor memory element comprising a memory cell portion provided above and a peripheral circuit connected to the memory cell portion by wiring on the surface of the semiconductor substrate, the wiring is connected to the one electrode of the capacitor. Since they are made of the same material and formed in the same process, it is possible to eliminate the difference in level between the memory cell section and the peripheral circuit section. Therefore, it is possible to eliminate the risk of disconnection or short-circuiting of the metal wiring, improve pattern accuracy, and increase the degree of freedom in designing the wiring.

[Brief explanation of the drawing]

FIG. 1 is a plan view showing an embodiment of the peripheral circuit of a semiconductor memory element of the present invention, and FIGS. 2 and 3 are a sectional view taken along the line ■-■ and FIG. FIG. 4 is a circuit diagram showing an equivalent circuit of the peripheral circuit section, FIGS. 5 and 8 are plan views showing the state of the peripheral circuit section in the middle of the process, and FIGS. 6 and 7 are respectively FIG. '1111-Vl line sectional view and ■-■ line sectional view, No. 9
Figure and Figure 10 are IX-IX in Figure 8, respectively.
Line sectional view and X-X line sectional view, Figures 11 and 12
13 is a cross-sectional view showing another embodiment of the peripheral circuit portion of the semiconductor memory device of the present invention, FIG. 13 is a plan view showing the memory cell portion of the semiconductor memory device of the present invention and a conventional semiconductor memory device, and FIG. is XI'/-XI in Figure 13
It is a sectional view taken along the line 1.
... n-type well region, 103 ... p-type well region,
4...Gate insulating film, 5.6...Gate electrode made of arsenic-doped borinolicon, 105,106...Gate electrode made of boron-doped borinolicon, 7.8-drain of n-channel transistor, 107
, 108... Drain of p-channel transistor, 9, IO... Source of n-channel transistor, 1
09,110... Source of p-channel transistor, ■G... Ith interlayer insulating film, l 1a, 1 lb, 1 1c, l ld, l le,
1 1f, l Ig, 1 1h, l li, l lj・
・・Contact hole, 12 13 212.213・
...Polysilicon wiring made of phosphorus-doped polysilicon, 12D 2+2D...Dummy polysilicon wiring made of phosphorus-doped polysilicon, 112,113...Polysilicon wiring made of boron-doped polysilicon, 112D...Boron-doped polysilicon Dummy polysilicon wiring made of silicon, l4... second interlayer insulating film, 14a, l4b, l4c, 14d--.
+ Contact hole, 15, 16.25...l! - Bit line made of Si alloy, 27...Barrier metal, TI, T2...n channel transistor, T. ．． ．．
,T,. ,... p-channel transistor, l7...
- Gate insulating film of memory cell, 18, 118... word line, l9... drain region of memory cell, 20... source region of memory cell, 2I... storage electrode, 22... columnar spacer , 23・
...Insulating film, 24...Plate electrode, C...Content element, M...Memory cell region, T...Transistor.

Claims (1)

[Claims] (1) A memory cell portion having a transistor and a capacitor formed on a surface of a semiconductor substrate, wherein at least a portion of one electrode having a columnar cross section of the capacitor is provided on the transistor, and a surface of the semiconductor substrate. In the semiconductor memory element described above, which includes a peripheral circuit section connected to the memory cell section by wiring, the wiring is made of the same material as the one electrode of the capacitor and formed in the same process. Characteristic semiconductor memory devices.