JPH02232962A - Integrated circuit - Google Patents

Integrated circuit

Info

Publication number
JPH02232962A
JPH02232962A JP5290589A JP5290589A JPH02232962A JP H02232962 A JPH02232962 A JP H02232962A JP 5290589 A JP5290589 A JP 5290589A JP 5290589 A JP5290589 A JP 5290589A JP H02232962 A JPH02232962 A JP H02232962A
Authority
JP
Japan
Prior art keywords
inductor
integrated
magnetic flux
winding
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5290589A
Other languages
Japanese (ja)
Inventor
Shinichi Uramoto
浦本 紳一
Masao Nakaya
中屋 雅夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Institute of Advanced Industrial Science and Technology AIST
Original Assignee
Agency of Industrial Science and Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agency of Industrial Science and Technology filed Critical Agency of Industrial Science and Technology
Priority to JP5290589A priority Critical patent/JPH02232962A/en
Publication of JPH02232962A publication Critical patent/JPH02232962A/en
Pending legal-status Critical Current

Links

Landscapes

  • Parts Printed On Printed Circuit Boards (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To make an integrated circuit of this design large in inductance per unit area by a method wherein the direction of magnetic flux is made parallel with a semiconductor board by the three-dimensional arrangement of a coil. CONSTITUTION:An integrated inductor is constituted so as to make the direction of magnetic flux parallel with the faces of active layers 1a and 1b using planes 3a and 3b and an interlaminar wiring 4 formed inside the active layers 1a and 1b which are provided through the intermediary of an interlaminar insulating film 2. When a winding is increased in number of turns, the length of the inductor in a lengthwise direction becomes larger than that in a crosssectional direction and the magnetic flux grows small in leakage, and the inductor is restrained from decreasing in effective inductance. When area required for the winding is taken into consideration, only a single wiring can do with a turn of the winding from the viewpoint vertical to the face of the active layer, so that the inductor of this design is remarkably increased in inductance per unit parallel to the active layer.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は集積回路に関し、特にインダクタ及びトランス
の集積化を行い、それらを回路素子として同時に集積し
て用いる半導体集積回路に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an integrated circuit, and more particularly to a semiconductor integrated circuit in which an inductor and a transformer are integrated, and these are simultaneously integrated and used as circuit elements.

〔従来の技術〕[Conventional technology]

インダクタは電子回路においてLC共振回路やLCフィ
ルタに不可欠な素子として、あるいは高周波での高イン
ピーダンスを利用する用途等に用いられ、一方トランス
は小信号あるいは電力の伝達用等に広く用いられている
。どちらも一般的な素子であるが、トランジスタのよう
に集積化が進んではいない。
Inductors are used in electronic circuits as essential elements for LC resonant circuits and LC filters, or for applications that utilize high impedance at high frequencies, while transformers are widely used for transmitting small signals or power. Both are common elements, but they are not as integrated as transistors.

第5図は従来の集積回路に用いられているインダクタの
例を示す図で、図a)が見取図、図b)が回路図である
FIG. 5 is a diagram showing an example of an inductor used in a conventional integrated circuit, in which figure a) is a sketch and figure b) is a circuit diagram.

半導体基板7の上にらせん状に形成された巻線8によっ
て所要のインダクタンスを実現するインダクタにおいて
は、そのインダクタンス値は一般に磁束の通過する面積
と、磁束の通過する部分の透磁率とで決定される。従っ
て、第5図に示した集積化インダクタにおいては半導体
基板の材質が決定すれば、磁束の方向が半導体基板に直
交する方向であるため、配線に用いられる面積が磁束の
通過する面積に等しく、インダクタンスは巻線のターン
数と、配線面積とに依有する。
In an inductor that achieves a required inductance using a winding 8 spirally formed on a semiconductor substrate 7, the inductance value is generally determined by the area through which the magnetic flux passes and the magnetic permeability of the portion through which the magnetic flux passes. Ru. Therefore, in the integrated inductor shown in FIG. 5, once the material of the semiconductor substrate is determined, since the direction of the magnetic flux is perpendicular to the semiconductor substrate, the area used for wiring is equal to the area through which the magnetic flux passes. Inductance depends on the number of turns of the winding and the wiring area.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上記のような従来のインダクタにおいては磁束の方向が
半導体基板の法線方向になるため、単位面積当りのイン
ダクタンスを太き《できない問題点があった。理由は2
つあり、1つは一定の設計ルールの下で巻線を配置する
と、ターン数の増加に伴い、配線面積も増大してしまう
ことであり、もう1つは単一平面上に巻線を形成するた
めに生じる磁束の漏れに起因する実効インダクタンスの
低下である。又、後者の理由から結合度がとれないため
にトランスが構成できない問題点があった。
In the conventional inductor as described above, the direction of the magnetic flux is the normal direction of the semiconductor substrate, so there is a problem that the inductance per unit area cannot be increased. The reason is 2
One is that if the windings are arranged under certain design rules, the wiring area will increase as the number of turns increases, and the other is that the windings are formed on a single plane. This is a decrease in effective inductance due to magnetic flux leakage caused by Further, due to the latter reason, there was a problem that a transformer could not be constructed because the degree of coupling could not be maintained.

本発明は上記のような問題点を解消するためなされたも
ので、単位面積当りのインダクタンスの大きなインダク
タを構成でき、あるいは結合度が十分大きなトランスを
形成できる集積回路を得ることを目的とする。
The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide an integrated circuit that can form an inductor with a large inductance per unit area or a transformer with a sufficiently large degree of coupling.

〔課題を解決するための手段〕[Means to solve the problem]

本発明に係る集積回路は、2層の平面配線とそれに直交
する層間配線とを用いて立体的に巻線を施し、磁束の方
向が半導体基板に平行になるようにすることにより、単
位面積当りのインダクタンスの大きな、また磁束の漏れ
の少ない集積化インダクタを、あるいはまた結合度が大
きな集積化トランスを構成したものである。
The integrated circuit according to the present invention has three-dimensional winding using two-layer planar wiring and interlayer wiring perpendicular to it, so that the direction of magnetic flux is parallel to the semiconductor substrate. An integrated inductor with a large inductance and a small leakage of magnetic flux, or an integrated transformer with a large degree of coupling.

〔作用〕[Effect]

本発明の集積化インダクタにおいては磁束の方向が半導
体基板と平行なため、単位面積当りのインダクタンスを
大きくすることができる。又、磁束の通る断面に比べて
インダクタの長手方向の長さを大きくすることにより磁
束の漏れを少なくすることができる。
In the integrated inductor of the present invention, since the direction of magnetic flux is parallel to the semiconductor substrate, the inductance per unit area can be increased. Further, leakage of magnetic flux can be reduced by making the length of the inductor in the longitudinal direction larger than the cross section through which the magnetic flux passes.

又、上記形状に加えて2線を極めて隣接させて磁束漏れ
の少ない巻線形状を構成することによって大きな結合度
を有する集積化トランスを構成することができる。
Furthermore, in addition to the above-mentioned shape, an integrated transformer having a large degree of coupling can be constructed by arranging two wires very close to each other to construct a winding shape with little magnetic flux leakage.

〔実施例〕〔Example〕

以下、本発明の一実施例を図について詳述する。 Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

第1図a)は本発明の一実施例による集積化インダクタ
の構造を示す見取図、図b)は図a》中の半導体基板と
平行な方向(S方向)から見た図、図C)は集積化イン
ダクタの回路図である。第1図a)において、la*1
bは活性層、2は層間絶縁膜で3 8t  a bは平
面配線、4は層間配線である。
Fig. 1 a) is a sketch showing the structure of an integrated inductor according to an embodiment of the present invention, Fig. 1 b) is a view seen from the direction parallel to the semiconductor substrate in Fig. 1 (S direction), and Fig. 1 C) is a diagram showing the structure of an integrated inductor according to an embodiment of the present invention. FIG. 2 is a circuit diagram of an integrated inductor. In Figure 1 a), la*1
b is an active layer, 2 is an interlayer insulating film, 38t a b is a planar wiring, and 4 is an interlayer wiring.

本発明の集積化インダクタは層間絶縁膜2を介した2層
の活性層1a.ll)内に形成された平面配線aa*s
bと、層間配線4とを用いて、磁束の方向が活性層の面
と平行になるよう構成されている。巻線のターン数を大
きくするとインダクタの長手方向の長さが断面方向より
も長くなり、磁束の漏れは少なくなり、実効インダクタ
ンスの低下が抑えられる。又、巻線に必要な面積を考え
た場合、活性層の面に垂直な方向から見桑と巻線1ター
ン当り1本の配線ですむため、上方からみた単位面積当
りのインダクタンスが大幅に増大する。
The integrated inductor of the present invention has two active layers 1a. ll) Planar wiring aa*s formed in
b and interlayer wiring 4 so that the direction of magnetic flux is parallel to the surface of the active layer. When the number of turns of the winding is increased, the length of the inductor in the longitudinal direction becomes longer than the cross-sectional direction, which reduces leakage of magnetic flux and suppresses a decrease in effective inductance. In addition, when considering the area required for the winding, since only one wire is required per turn of the winding from the direction perpendicular to the surface of the active layer, the inductance per unit area seen from above is greatly increased. do.

第2図は第1図の集積化インダクタの平面配線3a*3
bの配線形状をトロイダル状にした本発明の他の実施例
を示す見取図である。平面配線3a,3bをこの形状に
することにより磁路が閉じるため、漏れ磁束を極めて少
なくすることができる。
Figure 2 shows the planar wiring 3a*3 of the integrated inductor in Figure 1.
FIG. 7 is a sketch showing another embodiment of the present invention in which the wiring shape of FIG. By making the planar wirings 3a and 3b into this shape, the magnetic path is closed, so that leakage magnetic flux can be extremely reduced.

第3図は本発明の他の実施例による集積化トランスを示
す図である。第1図と同様に図a)が見取図、図b》が
回路図である。図a)においてθas9bは各々第1,
第2の配線であり、第1図に示した集積化インダクタン
スと同様に、層間絶縁膜2を介する2層の活性層1a.
ib内に形成された平面配線3 al  3 bと、層
間配線4とで構成されており、十分な結合度をもつよう
隣接して配置されている。この集積化トランスを構成す
るにおいても、当然第2図に示したトロイダル形吠を用
いることが可能である。
FIG. 3 is a diagram showing an integrated transformer according to another embodiment of the present invention. Similar to FIG. 1, Figure a) is a sketch, and Figure b) is a circuit diagram. In figure a), θas9b is the first,
This is the second wiring, and similarly to the integrated inductance shown in FIG. 1, the active layer 1a.
It is composed of a planar wiring 3 al 3 b formed in ib and an interlayer wiring 4, which are arranged adjacent to each other so as to have a sufficient degree of coupling. Naturally, in constructing this integrated transformer, the toroidal type shown in FIG. 2 can be used.

第4図は第3図に示した集積化トランスを能動素子と同
時に集積して使用した本発明の他の実施例を示し、半導
体基板上に集積された第1の回路ブロック5aと第2の
回路ブロック5bとの間にある集積化トランス8によっ
て、第1の回路ブロック5aの出力信号が第1の回路ブ
ロック5aとは絶縁された第2の回路ブロック5bに伝
達される。本構成により、従来は分割されていた回路ブ
ロック5 al  5 bを一体化することにより第4
図に示した各回路部分の小型化,軽量化を図ることがで
きる。
FIG. 4 shows another embodiment of the present invention in which the integrated transformer shown in FIG. 3 is integrated at the same time as an active element, and the first circuit block 5a and the second circuit block 5a integrated on the semiconductor substrate are used. The output signal of the first circuit block 5a is transmitted to the second circuit block 5b, which is insulated from the first circuit block 5a, by the integrated transformer 8 located between the first circuit block 5a and the first circuit block 5b. With this configuration, the fourth
Each of the circuit parts shown in the figure can be made smaller and lighter.

〔発明の効果〕〔Effect of the invention〕

以上のように本発明によれば、立体的な巻線の配置によ
り磁束の方向を半導体基板に平行にすることにより、単
位面積当りのインダクタンスの大きなインダクタを構成
することができる。又、該インダクタを隣接して配置す
ることによりトランスを構成することもでき、さらに他
の回路素子と同時に集積することにより、インダクタや
トランスを必要とする回路システムの小型化,軽量化を
図れる効果がある。
As described above, according to the present invention, an inductor with large inductance per unit area can be constructed by making the direction of magnetic flux parallel to the semiconductor substrate by arranging the windings three-dimensionally. Furthermore, by arranging the inductors adjacent to each other, a transformer can be formed, and by integrating other circuit elements at the same time, it is possible to reduce the size and weight of circuit systems that require inductors and transformers. There is.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例による集積化インダクタの構
成を示す図で、図a)が見取図、図b)が断面図、図C
)が回路図、第2図は本発明の第2の実施例による集積
化インダクタの構成を示す図、第3図は本発明の他の実
施例による集積化トランスの構成を示す図で、図a》が
見取図、図b)が断面図、図C)が回路図、第4図は第
3図に示した本発明の集積化トランスを用いて電子回路
を集積した本発明の他の実施例による集積回路を示す図
、第5図は従来の集積回路に用いられるインダクタを示
す図で、図a)が見取図、図b)が回路図である。 図において、la+1bは第1,第2の活性層、2は層
間絶縁膜、3as3bは第1,第2の平面配線、4は層
間配線、5 a#  5 bは第1,第2の回路ブロッ
ク、6は集積化トランス、7は半導体基板、8は巻線、
9 al  9 bは第1,第2の配線である。 なお図中同一符号は同一又は相当部分を示す。 特許出願人  工業技術院長 飯 塚 幸 三1図 第2図 第 図 第 図
Figure 1 is a diagram showing the configuration of an integrated inductor according to an embodiment of the present invention, in which Figure a) is a sketch, Figure b) is a sectional view, and Figure C
) is a circuit diagram, FIG. 2 is a diagram showing the configuration of an integrated inductor according to a second embodiment of the present invention, and FIG. 3 is a diagram showing the configuration of an integrated transformer according to another embodiment of the present invention. Figure a) is a sketch, Figure b) is a sectional view, Figure C) is a circuit diagram, and Figure 4 is another embodiment of the present invention in which electronic circuits are integrated using the integrated transformer of the present invention shown in Figure 3. FIG. 5 is a diagram showing an inductor used in a conventional integrated circuit, in which figure a) is a sketch and figure b) is a circuit diagram. In the figure, la+1b are the first and second active layers, 2 is an interlayer insulating film, 3as3b is the first and second plane wiring, 4 is the interlayer wiring, 5a# 5b is the first and second circuit block , 6 is an integrated transformer, 7 is a semiconductor substrate, 8 is a winding wire,
9 al 9 b are first and second wirings. Note that the same reference numerals in the figures indicate the same or equivalent parts. Patent applicant: Director of the Agency of Industrial Science and Technology Yuki Iizuka 31 Figure 2 Figure 2

Claims (1)

【特許請求の範囲】 1)層間絶縁膜を介する2層あるいはそれ以上の活性層
を有する集積回路において、 2層の平面配線と層間配線とを用いて磁束の向く方向が
活性層に平行になるよう立体的に構成される集積化され
たインダクタまたは集積化されたトランスを備えたこと
を特徴とする集積回路。
[Claims] 1) In an integrated circuit having two or more active layers with an interlayer insulating film interposed therebetween, the direction of magnetic flux is parallel to the active layer using two layers of planar wiring and interlayer wiring. What is claimed is: 1. An integrated circuit comprising an integrated inductor or an integrated transformer configured three-dimensionally.
JP5290589A 1989-03-07 1989-03-07 Integrated circuit Pending JPH02232962A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5290589A JPH02232962A (en) 1989-03-07 1989-03-07 Integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5290589A JPH02232962A (en) 1989-03-07 1989-03-07 Integrated circuit

Publications (1)

Publication Number Publication Date
JPH02232962A true JPH02232962A (en) 1990-09-14

Family

ID=12927857

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5290589A Pending JPH02232962A (en) 1989-03-07 1989-03-07 Integrated circuit

Country Status (1)

Country Link
JP (1) JPH02232962A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2766006A1 (en) * 1997-06-26 1999-01-15 Innotech Corp Miniature semiconductor device for mobile telephone set
US7410894B2 (en) 2005-07-27 2008-08-12 International Business Machines Corporation Post last wiring level inductor using patterned plate process
WO2010052839A1 (en) * 2008-11-06 2010-05-14 パナソニック株式会社 Semiconductor device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60138954A (en) * 1983-12-27 1985-07-23 Toshiba Corp Semiconductor device
JPS6367264B2 (en) * 1980-07-23 1988-12-23 Mitsubishi Electric Corp
JPS64308B2 (en) * 1981-06-02 1989-01-06 Kotsu Seisakusho Kk

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6367264B2 (en) * 1980-07-23 1988-12-23 Mitsubishi Electric Corp
JPS64308B2 (en) * 1981-06-02 1989-01-06 Kotsu Seisakusho Kk
JPS60138954A (en) * 1983-12-27 1985-07-23 Toshiba Corp Semiconductor device

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2766006A1 (en) * 1997-06-26 1999-01-15 Innotech Corp Miniature semiconductor device for mobile telephone set
US7410894B2 (en) 2005-07-27 2008-08-12 International Business Machines Corporation Post last wiring level inductor using patterned plate process
US7573117B2 (en) 2005-07-27 2009-08-11 International Business Machines Corporation Post last wiring level inductor using patterned plate process
US7732295B2 (en) 2005-07-27 2010-06-08 International Business Machines Corporation Post last wiring level inductor using patterned plate process
US7732294B2 (en) 2005-07-27 2010-06-08 International Business Machines Corporation Post last wiring level inductor using patterned plate process
US7741698B2 (en) 2005-07-27 2010-06-22 International Business Machines Corporation Post last wiring level inductor using patterned plate process
US7763954B2 (en) 2005-07-27 2010-07-27 International Business Machines Corporation Post last wiring level inductor using patterned plate process
WO2010052839A1 (en) * 2008-11-06 2010-05-14 パナソニック株式会社 Semiconductor device
US7978043B2 (en) 2008-11-06 2011-07-12 Panasonic Corporation Semiconductor device
JPWO2010052839A1 (en) * 2008-11-06 2012-03-29 パナソニック株式会社 Semiconductor device

Similar Documents

Publication Publication Date Title
JP3127792B2 (en) LC resonator and LC filter
JPH03262313A (en) Band pass filter
JPH0319358A (en) Semiconductor integrated circuit
JP2007259026A (en) Multilayer noise filter
JP2020025046A (en) Common mode choke coil
JPH04237106A (en) Integrated inductance element and integrated transformer
JPH08148354A (en) Laminated common-mode choke coil
JPH08335517A (en) Lamination common mode choke coil
JPH02232962A (en) Integrated circuit
JP5585605B2 (en) Filter element
KR940000432B1 (en) Line filter
JP2009088329A (en) Coil component
JP2003087074A (en) Laminated filter
JPS60136363A (en) Semiconductor device
JPS58188108A (en) Transmission device
JPH0950916A (en) Thin-film magnetic element
JPH0521244A (en) Thin transformer
JP2000252124A (en) Common mode filter
JPH04245410A (en) Printed coil for double-tuned circuit use
JP3142060B2 (en) Noise filter
CN116248071B (en) Filter, filter design method and communication equipment
JPS62142395A (en) Multi-function circuit board
JPH03280409A (en) Flat transformer
JP2810812B2 (en) Branch circuit
JPS6042917A (en) Filter device