JPH02232897A - Semiconductor memory cell and semiconductor memory - Google Patents

Abstract

PURPOSE:To obtain a memory, which can execute an access at high speed, by providing first and second transistors, whose bases are respectively connected to first and second nodes of an FF, and a third transistor, of which a base is connected to a word line and an emitter is connected to a bit line, in a memory cell composed of the FF. CONSTITUTION:The FF composed of bipolar transistors QC1 and QC2 is defined as the basic constitution of the memory cell and the bases of transistors Q1 and Q2 are respectively connected to the bases of the QC1 and QC2. Then, the collector of a transistor Q3 is commonly connected to the emitters of the Q1 and Q2 and the base is connected to a word line W2. Afterwards, the emitter is connected to a bit line IR and the memory cell is constituted. At the time of reading, when a reading current is supplied to the bit line IR, the Q3 to be connected to the bit line IR constitutes one current switch. The switching voltage, namely, the voltage amplitude of a base input for the Q can be 0.4V at maximum and the potential of the bit line IR is lower than that of a word line W2 only by VBE. The relation is established concerning other plural bit lines IWL and IWR. Namely, the potentials of all the bit lines are made equal and the voltage amplitude is O. Then, the charging and discharging time of the word line and bit line can be made small.

Description

[Detailed description of the invention]

INDUSTRIAL APPLICATION FIELD 1 The present invention relates to semiconductor memories, and in particular to memory cells and memory circuit technology suitable for semiconductor memories that require high integration and high speed. 2. Description of the Related Art Conventionally, in semiconductor memories, a method has often been used in which a voltage signal is applied to a word line to select a memory cell, and information stored in the memory cell is read out as a voltage signal to a bit line. For example, CMOS-SRAM (Static Ran
dom Access Memory) and BiCM
In the OS-SRAM, the amplitudes of the voltage signals mentioned above are approximately equal to the power supply voltage, and are as large as approximately 5V. Further, even in a high-speed bipolar RAM, the voltage amplitude is approximately 1V. Furthermore, as memories have recently become more highly integrated, the number of cells connected to word lines and bit lines has increased, and the stray capacitance of word lines and bit lines has increased. Therefore, memory access time has come to be regulated by these charging and discharging times. For this reason, many high-speed discharge circuits have been proposed for bipolar RAM, such as the one described in Japanese Patent Laid-Open No. 188884/1984. However, there is an upper limit to the discharge current that can flow through the word line and bit line due to an increase in wiring resistance due to the miniaturization of the wiring width and migration restrictions, and therefore there is a limit to the speeding up of access time using such a discharge circuit. There is,

[Problem to be solved by the invention 1 As mentioned above. In conventional memories, there was a limit to speeding up the access time because the number of cells connected to the word line and bit line increased, and the memory access time was determined by the charging and discharging time of the word line and bit line. This is because it has become more common. Therefore, by reducing the voltage amplitude of the word line and bit line, charging and discharging time can be reduced, and access time can be increased. For example, in the extreme, if the voltage amplitude of the word line and bit line is made zero, the charge/discharge time mentioned above becomes zero. An object of the present invention is to provide a semiconductor memory that reduces the charging/discharging time of word lines and bit lines by reducing the voltage amplitude of word lines and bit lines based on the above reasoning, and achieves faster access times. The aim is to provide cells and memory. [Means for Solving the Problems] In order to achieve the above object, the present invention is configured as described in the claims. That is, in the memory cells according to the first and third claims, by providing a memory cell configured with a flip-flop with a transistor switch that supplies current to the cell only when selected, the selected cell can be switched as in the conventional case. This eliminates the need to drive the cell to a high potential, thereby reducing the voltage amplitude of the word line and bit line, increasing speed and expanding the operating margin of the cell. Note that the first claim corresponds to the embodiments of FIGS. 1, 2, 5, and 6, and the third claim corresponds to the embodiments of FIGS.
The claims correspond to the embodiments of FIGS. 3 and 4, for example. Further, the memory cell according to the second and fourth claims retains information in the memory cell by using a vertically structured transistor as the transistor in the memory cell according to the first or third K* claim. The node is separated from the substrate, which is the source of α-ray noise current, and is configured to prevent information destruction due to the incidence of α-rays. Note that the second and fourth claims correspond to the embodiments of FIGS. 7 and 8, for example. Further, the semiconductor memory according to the fifth aspect is provided with a pre-sense circuit that is activated by the word line or bit line selection signal only when the corresponding word line or bit line is selected by the selection signal. This achieves low power consumption. In addition, the fifth
The claims correspond to the embodiment shown in FIG. 9, for example. Further, a semiconductor memory according to a sixth aspect is provided in which a memory cell array is formed using the semiconductor memory cells according to the first to fourth aspects, an emitter is connected to the bit line, and a base is a dummy. A transistor connected to the word line is provided, and by applying a voltage equal to that of the selected word line to the dummy word line, the current supplied to the memory cell and the discharge current of the bit line can be set independently. , which speeds up bit line discharge.
Note that the sixth claim corresponds to the embodiment shown in FIG. 10, for example. 1. When a cell array is constructed of memory cells as described in the first or third claim, the bit lines formed include the third bit line of each cell.
The emitters of the transistors are connected in common. When a constant current source is connected to this pit line, these become 1
This constitutes two current switches. The voltage amplitude of the signal necessary to switch this current switch, that is, the voltage amplitude of the signal input to the base of the third transistor is at most 0.4V.
A certain degree is sufficient. In other words, the voltage amplitude of the word line may be about 0.4V. Further, at this time, the potential of the bit line is lower than the potential of the high potential word line by the base-emitter voltage of the third transistor. This relationship holds true for all other multiple bit lines. In other words, the potentials of all bit lines are approximately equal, and the voltage amplitude of the bit lines is approximately OV.
becomes. Therefore, the charging/discharging time of the word line and bit line becomes extremely short, and the access time can be increased accordingly.

[Embodiment] FIG. 1 is a diagram showing a first embodiment of a memory cell according to the present invention, and shows a circuit diagram of one cell. In FIG. 1, bipolar transistors QCl, QC
The basic structure of the memory cell is a flip-flop consisting of two transistors, a first transistor Q1 whose base is connected to the base of the transistor QCI, a second transistor Q2 whose base is connected to the base of the transistor QC2, and a collector. is commonly connected to the emitters of transistors Q1 and Q2, has a base connected to word liW2, and has an emitter connected to bit line IR. In addition, the word line W1
A constant voltage is applied to . A constant current source that supplies information retention current is connected to Igt. Also. IWL and IWR are bit lines that supply write current, and CSL and CSR are common sense lines that output memory cell information. Reading of information in the above memory cell is performed on the word line W
This is done by driving bit line IR to a high potential and supplying a read current to bit line IR. At this time, either transistor Q1 or Q2 is turned on depending on the information in the memory cell, and a read current flows to either common sense line CSL or CSH. By sensing this current, the information of the selected cell can be read. In addition, writing of information to the memory cell is performed on the word line W2.
Bit II is driven to a high potential, and depending on the information to be written, bit II
This is done by supplying a write current to either AIWL or IWR. What should be noted here is that when a cell array is configured with this memory cell, the emitter of transistor Q3 is connected to bit iIR, the emitter of transistor QWL is connected to bit line IWL, and the emitter of transistor QWR is connected to bit line IWR. The number of connections is equal to the number of cells. When a read current is supplied to the bit line IR during reading, the transistor Q3 of each cell connected to the bit line IH constitutes one current switch. The voltage required to switch this current switch, that is, the voltage amplitude of the signal input to the base of transistor Q3, is at most 0.
．． Approximately 4v is sufficient. Also, when writing, the bit line I
When a write current is supplied to either WL or IWR, the plurality of transistors QWL or QWR connected to bit line IWL or IWR constitute one current switch. It is sufficient that the voltage required to switch this current switch, that is, the voltage amplitude of the signal input to the base of the transistor QWL or QWR, is about 0.4 V at most. Therefore, the voltage amplitude of the word line W2 may be approximately 0.4V. In addition, the bit lines IR, IWL. The potential of IWR is . Transistors Q3, QWL, Q than the potential of the high potential word line.
The potential becomes lower by the voltage between the base and emitter of WR,
This relationship holds true for all other multiple bit lines. In other words, the potential of all bit lines is almost the same regardless of whether they are selected or not, and therefore the voltage amplitude of the bit lines is approximately Ov. Therefore, the charging and discharging time of the word line and bit line is extremely short, and access is reduced accordingly. It can speed up time. Furthermore, since there is no need to drive the selected cell to a high potential as in the conventional case, the potential of the node holding information in the memory cell hardly changes between selected and non-selected states. When a selected cell is driven to a high potential, the low potential node in the cell rises more rapidly than the high potential node due to the difference in the time constant of the nodes that hold information in the memory cell. This solves the problem of reduced cell operating margin. In this embodiment, resistors RL and RR and Schottky barrier diodes SBDL and SBDR are used as loads on the collectors of transistors QCI and QC2;
Any conventionally known load may be used, such as inserting a resistor in series with L and SBDR. Next, FIG. 2 is a diagram showing a second embodiment of the memory cell of the present invention, and shows a circuit diagram of one cell. The difference between FIG. 2 and FIG. 1 is that the emitter of transistor Q3 and the emitters of transistors QWL and QWR are commonly connected to bit line IR. Further, a constant voltage is applied to the word line W1, and a constant current source that supplies an information holding current is connected to Ist. Further, word lines W3 and W4 are word lines for supplying write signals, and CSL. CSR is a common sense line that outputs memory cell information. To read information in the above memory cell, the word $W
This is done by driving bit line IR to a high potential and supplying a read current to bit line IR. At this time, either transistor Q1 or Q2 is turned on depending on the information in the memory cell, and a read current flows to either common sense line CSL or CSH. By sensing this current, the information of the selected cell can be read. Furthermore, information is written into the memory cell by driving either the word line W3 or W4 to a high potential and supplying a write current to the bit line IR, depending on the information to be written. What should be noted here is that when a cell array is configured with these memory cells, transistors Q3 and Q3 are connected to the bit line IR.
The emitters of WL and QWR are connected as many times as there are cells. When a read or write current is supplied to the bit line IR during read or write, a plurality of transistors Q3 and QW connected to the bit line IR
L and QWR constitute one current switch. The voltage required to switch this current switch, that is, transistors Q3 and QWL
It is sufficient that the voltage amplitude of the signal input to the base of the QWR is about 0.4V at most. That is, word line W2. The voltage amplitude of W3 and W4 is 0.
Approximately 4v is sufficient. Further, the potential of the bit line IR is lower than the potential of the high potential word line by the base-emitter voltage of the transistor Q3, QWL, or QWR, and this relationship holds true for all of the other multiple bit lines. . That is, the potentials of all bit lines are approximately equal regardless of whether they are selected or not, and therefore the voltage amplitude of the bit lines is approximately Ov. Therefore, the charging and discharging time of word lines and bit lines becomes extremely short, and the access time can be increased accordingly. Further, for the same reason as described in FIG. 1 above, it is possible to solve the problem of the conventional problem that the operating margin of the cell decreases during selection. In this embodiment as well, as in the embodiment shown in FIG. As, Schottky barrier diode SBDL, SBD
Any conventionally known load may be used, such as inserting a resistor in series with R. Next, FIG. 3 is a diagram showing a third embodiment of the memory cell of the present invention, and shows a circuit diagram of one cell. In Figure 3,
A flip-flop consisting of bipolar transistors QCl and QC2 is the basic structure of the memory cell, and the collector is commonly connected to the emitters of transistors QCI and QC2, the base is connected to the word line W2, and the emitter is connected to the bit MIH. It has a third transistor Q3. Further, a constant voltage is applied to the word line W1, and a constant current source that supplies an information holding current is connected to Ist. Also,.
IWL and IWR are bit lines that supply write current, and CSL and CSR are common sense lines that output memory cell information. Reading and writing information in this cell can be performed in the same manner as described in the embodiment of FIG. 1 above. Also, based on the same argument as described in FIG. 1, the word line W2
The voltage amplitude of the bit line is approximately 0.4V, and the voltage amplitude of the bit line is approximately Ov. Therefore, the charging/discharging time of the word line and bit line becomes extremely short, and the access time can be increased accordingly. Further, for the same reason as described in FIG. 1, it is possible to solve the conventional problem that the operating margin of the cell decreases during selection. Furthermore, in this embodiment, the 11i! Compared to
The cell area can be reduced by the absence of transistors Q1 and Q2. In this embodiment as well, resistors RL and RR and Schottky barrier diodes SBDL and SBDR are used as loads on the collectors of transistors QC1 and QC2. Inserting a resistor in series, etc.
Any conventionally known load may be used.
Next, FIG. 4 is a diagram showing a fourth embodiment of the memory cell of the present invention, and shows a circuit diagram of one cell. In Figure 4,
The difference from FIG. 3 is that the emitter of transistor Q3 and the emitters of transistors QWL and QWR are commonly connected to bit line IR. Further, a constant voltage is applied to the word line W1, and a constant current source that supplies an information holding current is connected to Ist. Furthermore, word lines W3 and W4 are word lines for supplying write signals, and CSL and CSR are common sense lines that output information of memory cells. Reading and writing of information in this cell can be performed in the same manner as described in the embodiment of FIG. 2 above. Also, from the same discussion as described in FIG. 2, the word line W2
, W3, and W4 are approximately 0.4V, and the voltage amplitude of the bit line is approximately O■. Therefore, the charging/discharging time of the word line and bit line becomes extremely short, and the access time can be increased accordingly. Furthermore, for the same reason as described in FIG. 1, it is possible to solve the conventional problem that the operating margin of the cell decreases during selection. Furthermore, compared to the embodiment shown in FIG. 1, the cell area can be made smaller due to the absence of transistors Ql and Q2. In this embodiment as well, resistors RL and RR and Schottky barrier diodes SBDL and SBDR are used as loads on the collectors of transistors QC1 and QC2. Inserting a resistor in series, etc.
Any conventionally known load may be used. Next, FIG. 5 is a diagram showing a fifth embodiment of the memory cell of the present invention, and shows a circuit diagram of one cell. In FIG. 5, a flip-flop consisting of n-type MoS transistors MN1 and MN2 is the basic structure of the memory cell, and further includes a first transistor Q1 whose base is connected to the drain of transistor MNI, and a first transistor Q1 whose base is connected to the drain of transistor MN2. A second transistor Q2 is connected, its collector is commonly connected to the emitters of transistors Q1 and Q2, and its base is connected to the word line W.
2, and a third transistor Q3 whose emitter is connected to the bit line IR. Further, a constant voltage is applied to WH and WL. Also, IW
L and IWR are bit lines that supply a write current, and CSL and CSR are common sense lines that output memory cell information. Reading and writing of information in this cell can be performed in the same manner as described in the embodiment of FIG. 1 above. Also, based on the same argument as described in FIG. 1, the word line W2
The voltage amplitude of the bit line is approximately 0.4V, and the voltage amplitude of the bit line is approximately Ov. Therefore, the charging/discharging time of the word line and bit line becomes extremely short, and the access time can be increased accordingly. Note that in this embodiment, transistors MNI and MN2
As a load on the drain of the p-type MOS transistor M
Although PI and MP2 are used, any conventionally known load such as a resistor may be used as the load. 'Next, FIG. 6 is a diagram showing a sixth embodiment of the memory cell of the present invention, and shows a circuit diagram of one cell. The difference between FIG. 6 and FIG. 5 is that the emitter of transistor Q3 and the emitters of transistors QWL and QWR are commonly connected to bit line IR.
Also, WH. A constant voltage is applied to WL. Also, W3
, W4 are word lines for supplying write signals, and CSL and CSR are common sense lines that output memory cell information. Reading and writing of information in this cell can be performed in the same manner as described in the embodiment of FIG. 2 above. Also, based on the same argument as mentioned in Fig. 2, word line W2
, W3 and W4 are approximately 0.4V, and the voltage amplitude of the bit line is approximately Ov. Therefore, the charging/discharging time of the word line and bit line becomes extremely short, and the access time can be increased accordingly. In this embodiment as well, P-type MOS transistors MPI and MP2 are used as loads on the drains of transistors MN1 and MN2, but this load may be any conventionally known type such as a resistor. Load may also be used. Next, FIG. 7 is a diagram showing a seventh embodiment of the memory cell of the present invention, and shows a cross-sectional view of a bipolar transistor. This embodiment applies, for example, to the transistors QCI, QC2, QWI, QWR in the circuit of FIG. 3 or 4.
It is used as a. In addition, in FIG. 7, Ep
i is the epitaxial layer, n+BL is the n+ embedded Jfj.
poly-Si indicates polysilicon N. As shown in the figure, in this embodiment, transistors QCl, Q
C2, QWL, and QWR are formed inside the semiconductor substrate and on its surface, and from the inside (bottom) to the surface (top) of the semiconductor substrate, an emitter of a first conductivity type (n type),
Base of second conductivity type (p type), first conductivity type (n type)
The transistor has a vertical structure in which the collector is arranged in the order of the collector. By using such a vertically structured transistor, it is possible to separate the node that holds information in the memory cell from the p-substrate that is the source of α-ray noise current. Therefore,
Even if alpha rays are incident on the transistors that make up the memory cell, information will not be destroyed, making it possible to reduce soft errors in semiconductor memory. Next, FIG. 8 is a diagram showing an eighth embodiment of the memory cell of the present invention, and shows a cross-sectional view of a device in which a plurality of bipolar transistors are formed on one substrate. In this embodiment, for example, the transistors QCI, QC2, and Q3 in the circuit shown in FIG. 3 or 4 are formed on one substrate, and has a vertical structure similar to that in FIG. 7. In this embodiment, similar to the embodiment shown in FIG.
In addition to being effective in preventing information destruction caused by alpha rays,
Emitter Ei of QCI, emitter E2 and Q of QC2
3 collector C. are connected in common by the n1 embedded calendar BL, that is, the point P in FIG. 3 or 4 is easily connected inside the board, so the structure is simple and compact. Next, FIG. 9 is a circuit diagram of an embodiment of the semiconductor memory of the present invention. This semiconductor memory shows a case where a cell array is constructed using the memory cells shown in FIG. 3 (however, a resistor is inserted in series with the Schottky barrier diode). In FIG. 9, MCOO-MCII are the memory cells shown in FIG. 3, and YDO and YDI are the bit lines IR and IWL.
, Y supplying read current or write current to IWR
Driver, PSO, Psi are common sense icsL
, CSR is a pre-sense circuit that detects the read current flowing through the CSR. In this semiconductor memory, for example, memory cell MC
To read information from OO, it is sufficient to drive the word line W20 to a high potential, set the bit line selection signal VY I No to a high potential, and drive VR of the write control signals to a high potential. . At this time, read current IRR flows to either common sense line CSL or CSR according to the information in cell MCOO, and either pre-sense circuit output SO or S1 becomes high potential and information is read out. Ru. Also, information is written to cell MCOO on word line W.
20 to a high potential, bit line selection signal VY I N
o is driven to a high potential, and one of the write control signals VWO and VWI is shifted to a high potential depending on the information to be written. At this time, depending on the information to be written, the bit line IW
IRR is supplied as a write current to either L or 1 to IWR, and information is written to cell MCOO.
Note that the constant currents IBR, IBWL,
IBWR is the base voltage of transistor Q3, QWL or QWR when current IRR is not supplied to the bit line.
This is added to prevent the voltage amplitude of the bit line from increasing due to a decrease in the emitter voltage and an increase in the potential of the bit line. Further, the pre-sense circuits PSO and Psi are activated by the selection signal only when the corresponding word line is selected by the word line selection signal W20 and W21. For this reason, the current source IPS for the pre-sense circuit is one current source for multiple pre-sense circuits.
It is only necessary to provide only one, and the power consumption can be reduced accordingly. Note that it is also possible to make the bit line active only when it is selected. Next, FIG. 10 is a circuit diagram of another embodiment of the semiconductor memory of the present invention. This embodiment differs from the embodiment of FIG. 9 in that it includes a dummy word line WD, a transistor Q3D. QWLD and QWRD
The only difference is that . In this embodiment, if the potential of the dummy word line WD is made equal to the potential (high potential) of the selected word line, the current IRR will be equal to the transistor Q3 of the selected cell, Transistor Q3 connected to QWL or QWR and dummy word line WD
D. The current is divided between QWLD and QWRD. This shunt ratio is determined by transistor Q3D. QWLD or QW
It can be set arbitrarily by changing the emitter area of RD. In other words, the current flowing through the memory cell and the IRR can be designed independently. Therefore, in order to reduce power consumption, constant current IB supplied to the bit line
When R, IBWL, and IBWR are several orders of magnitude smaller than the current IRR. Although the fluctuation in the base-emitter voltage of transistor Q3, QWL, or QWR becomes large and the voltage amplitude of the bit line increases, since the IRR can be made sufficiently large, the bit line can be discharged at an extremely high speed. ■Effects of the Invention As described above, when the present invention is used, the voltage amplitude of the word line is approximately 0.4V, and the voltage amplitude of the bit line is approximately 0.
It can be set to an extremely low value of v. Therefore, the charging and discharging time of word lines and bit lines becomes extremely short, and the access time can be increased accordingly.
Furthermore, since there is no need to drive the selected cell to a high potential, the operating margin of the cell can be expanded. Furthermore, since the memory cell according to the third claim gg has fewer transistors than the memory cell according to the first claim, the cell can be made smaller. Furthermore, when the vertically structured transistors according to the second and fourth claims are used, in addition to the above-mentioned effects, an effect of preventing information destruction due to alpha rays can be obtained. Further, in the semiconductor memory according to the fifth aspect, lower power consumption can be achieved. !
In the semiconductor memory described in item W, the current supplied to the memory cell and the discharge current of the bit line can be set independently, so it is possible to discharge the bit line extremely quickly. Excellent effects can be obtained.

[Brief explanation of the drawing]

1 to 6 are circuit diagrams of embodiments of the memory cell of the present invention, FIGS. 7 and 8 are sectional views of the embodiment of the memory cell of the present invention, and FIGS. 9 and 10 are circuit diagrams of embodiments of the memory cell of the present invention, respectively. FIG. 3 is a circuit diagram of an embodiment of a semiconductor memory according to the present invention; FIG. <Explanation of symbols> Q, L, Q2, Q3 ... QCI, QC2, ... QWL, QWR ... MNI, MN2 ... MPI, MP2 ... RL, RR ... SBDL, SBDR ・... Transistor Transistor Transistor NMO S PMOS Resistance Schottky barrier diode Word line Word line Wl, W2, W3, W4 ... W20, W21 IR, IWL, IWR CSL, CSR VYINI, VYIN2 MCOO~MCII YDO, YDI PSO, Psi

Claims (1)

[Claims] 1. In a memory cell configured with a flip-flop, a first transistor having a base connected to a first node of the flip-flop, and a base connected to a second node of the flip-flop. a second transistor having a collector connected in common to the emitters of the first and second transistors, and a base connected to a word line;
A semiconductor memory cell comprising: a third transistor having an emitter connected to a bit line. 2. In the semiconductor memory cell according to claim 1, the flip-flop is composed of two bipolar transistors, and these transistors and the first and second transistors are arranged inside the semiconductor substrate and inside the semiconductor substrate. formed on the surface, at least one of which is
The transistor is characterized by having a vertical structure in which the emitter of the first conductivity type, the base of the second conductivity type, and the collector of the first conductivity type are arranged in this order from the inside of the semiconductor substrate toward the surface. semiconductor memory cell. 3. In a memory cell configured with a flip-flop consisting of a first transistor and a second transistor, the collector is commonly connected to the emitters of the first and second transistors, the base is connected to the word line, and the emitter is connected to the word line. A semiconductor memory cell comprising a third transistor connected to a bit line. 4. In the semiconductor memory cell according to claim 3, the first and second transistors are formed inside the semiconductor substrate and on the surface thereof, and at least one of them is formed from the inside of the semiconductor substrate to the surface thereof. A semiconductor memory cell characterized in that it is a transistor having a vertical structure in which an emitter of a first conductivity type, a base of a second conductivity type, and a collector of the first conductivity type are arranged in this order. 5. The number of word lines or bit lines forming a memory cell array using the semiconductor memory cells according to any one of claims 1 to 4 and having a function of amplifying information signals read from the memory cells. The number of pre-prints corresponding to
A semiconductor memory comprising a sense circuit, wherein the pre-sense circuit is activated by a word line or bit line selection signal only when a corresponding word line or bit line is selected by the selection signal. . 6. A memory cell array is formed using the semiconductor memory cells according to any one of claims 1 to 4, and includes a transistor whose emitter is connected to the bit line and whose base is connected to the dummy word line, A semiconductor memory characterized in that a voltage equal to that of a selected word line is applied to a dummy word line.