JPH0223098B2 - - Google Patents
Info
- Publication number
- JPH0223098B2 JPH0223098B2 JP58099456A JP9945683A JPH0223098B2 JP H0223098 B2 JPH0223098 B2 JP H0223098B2 JP 58099456 A JP58099456 A JP 58099456A JP 9945683 A JP9945683 A JP 9945683A JP H0223098 B2 JPH0223098 B2 JP H0223098B2
- Authority
- JP
- Japan
- Prior art keywords
- agc
- reference voltage
- event
- circuit
- comparator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000010586 diagram Methods 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers
- H03G3/20—Automatic control
- H03G3/30—Automatic control in amplifiers having semiconductor devices
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers
- H03G3/20—Automatic control
- H03G3/30—Automatic control in amplifiers having semiconductor devices
- H03G3/3036—Automatic control in amplifiers having semiconductor devices in high-frequency amplifiers or in frequency-changers
Landscapes
- Control Of Amplification And Gain Control (AREA)
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
Description
【発明の詳細な説明】
(1) 発明の技術分野
本発明はデイジタル制御形AGC（Automatic
Gain Control）回路に関する。[Detailed Description of the Invention] (1) Technical Field of the Invention The present invention relates to a digitally controlled AGC (Automatic
(Gain Control) circuit.
(2) 技術の背景
AGC回路は広汎な分野で利用され、受信レベ
ルを自動的に所定の定レベルに維持するものであ
る。例えばPCM通信の中継伝送路中に挿入され
る等化器（equalizer）においてもその前段回路
として重要な役割を果す。一般的にはこのAGC
回路は殆どアナログ部品で構成されていたが、近
年はデイジタル制御形AGC回路が用いられてい
る。これは、デイジタル制御とすることにより、
回路部品のLSI化が容易になり、信頼性向上、小
形化に有利となるからである。なお、本発明にお
けるデイジタル制御形AGC回路（以下単にAGC
回路とも称す）は、離散的な受信信号、すなわち
“１”，“０”のデータを情報媒体とする受信信号
に対し、AGCをかけるものとする。(2) Technical background AGC circuits are used in a wide range of fields and automatically maintain the reception level at a predetermined level. For example, it plays an important role as a pre-stage circuit in an equalizer inserted into a relay transmission path for PCM communication. Generally this AGC
Most of the circuits were made up of analog parts, but in recent years digitally controlled AGC circuits have been used. By using digital control, this
This is because circuit components can be easily integrated into LSI, which is advantageous for improving reliability and downsizing. Note that the digitally controlled AGC circuit (hereinafter simply referred to as AGC) in the present invention
(also referred to as a circuit) performs AGC on a discrete received signal, that is, a received signal whose information medium is data of "1" and "0".
(3) 従来技術と問題点
第１図はデイジタル制御形AGC回路の第１の
従来例を示す回路図である。本図において、この
第１の従来例はいわゆるアナログ形ピーク検出回
路を備えたAGC回路であり、ピークホールド
を行つているためどうしてもAGCの初期引込み
が遅くなり、そのピークホールドのためのコン
デンサ（μFオーダとなることがある）はLSIに対
し外付けとなり不便であり、そのためにAGC
特性の安定化に欠ける、等の諸問題点を有する。
その動作は次のとおりである。(3) Prior Art and Problems FIG. 1 is a circuit diagram showing a first conventional example of a digitally controlled AGC circuit. In this figure, the first conventional example is an AGC circuit equipped with a so-called analog peak detection circuit, and since it performs peak hold, the initial pull-in of the AGC is inevitably slow, and the capacitor for peak hold (μF ) is inconvenient as it is external to the LSI, so the AGC
It has various problems such as lack of stabilization of characteristics.
Its operation is as follows.
AGCをかけるべき入力信号Sinは先ず可変利得
増幅器１１に入力される。この可変利得増幅器１
１は増幅回路１１−１とデイジタル利得制御部１
１−２とからなる。増幅回路１１−１の出力は、
外付けのコンデンサ１３と協働するピーク検出回
路１２に入力され、前記のピークホールドが行わ
れる。 The input signal Sin to be subjected to AGC is first input to the variable gain amplifier 11. This variable gain amplifier 1
1 is an amplifier circuit 11-1 and a digital gain control section 1
It consists of 1-2. The output of the amplifier circuit 11-1 is
The signal is input to a peak detection circuit 12 that cooperates with an external capacitor 13, and the peak hold described above is performed.
ホールドされたピーク値Vpはコンパレータ１
４において、所定の定レベル（基準電圧Vr）と
大小比較される。大なら（Vp＞Vr）“１”、小な
ら（Vp＜Vr）“０”がアツプ／ダウン・カウン
タ１５に印加され、カウンタ１５はクロツク
CLKに同期して、ダウンカウント（“１”の場
合）、又はアツプカウント（“０”の場合）を行
う。カウンタ１５のカウント値はスイツチデコー
ダ１６に印加され、該スイツチデコーダ１６はそ
のカウント値に応じた１つたのスイツチSWをオ
ンにし、該スイツチSWはそのカウント値に対応
した利得を設定する。かくしてAGC制御が実行
される。なお、AGC制御を受けた本来の出力信
号は図中のＳ outとして取り出される。 The held peak value Vp is the comparator 1
4, it is compared in magnitude with a predetermined constant level (reference voltage Vr). If it is large (Vp>Vr), "1" is applied, and if it is small (Vp<Vr), "0" is applied to the up/down counter 15, and the counter 15 is clocked.
In synchronization with CLK, down-counting (in the case of "1") or up-counting (in the case of "0") is performed. The count value of the counter 15 is applied to a switch decoder 16, and the switch decoder 16 turns on one switch SW corresponding to the count value, and the switch SW sets a gain corresponding to the count value. AGC control is thus executed. Note that the original output signal subjected to AGC control is taken out as S out in the figure.
第２図はデイジタル制御形AGC回路の第２の
従来例を示す回路図である。この第２の従来例
は、いわばピークサーチ形のAGC回路であり、
既述の諸問題点からの連続番号を付すると、別
途高速のクロツクが必要となる、という問題点が
ある。その動作は次のとおりである。なお、第１
図と同様の構成要素には同一の参照番号又は記号
を付して示す（以下の図面についても同じ）。
AGC動作の基本は第１の従来例（第１図）と変
わらないが、この第２の従来例では、入力信号の
レベル変化をクロツクで打ち抜き、打ち抜かれた
レベルのピークを探り出す（ピークサーチ）とい
うものである。このピークサーチは制御回路２１
が行う。この場合、入力信号Sioのデータの
“１”，“０”に同期したクロツクを用いることが
考えられるが、AGCの初期引込み時に含まれる
ジツタ（位相のゆらぎ）を考慮すると、そのよう
なクロツクに代えて高速のクロツクCLK′を用い
なければならない。 FIG. 2 is a circuit diagram showing a second conventional example of a digitally controlled AGC circuit. This second conventional example is a so-called peak search type AGC circuit,
Given the problems already mentioned, if consecutive numbers are assigned, a separate high-speed clock is required. Its operation is as follows. In addition, the first
Components similar to those in the figures are designated by the same reference numbers or symbols (the same applies to the following figures).
The basics of AGC operation are the same as the first conventional example (Figure 1), but in this second conventional example, level changes in the input signal are punched out using a clock, and the peak of the punched level is found (peak search). That is what it is. This peak search is performed by the control circuit 21
will do. In this case, it is conceivable to use a clock synchronized with the data "1" and "0" of the input signal S io , but considering the jitter (phase fluctuation) included at the initial pull-in of the AGC, such a clock is A fast clock CLK' must be used instead.
(4) 発明の目的
本発明は上記諸問題点〜を同時に解決する
ことのできるデイジタル制御形AGC回路を提供
することを目的とするものである。(4) Object of the Invention The object of the present invention is to provide a digitally controlled AGC circuit that can simultaneously solve the above-mentioned problems.
(5) 発明の構成
上記目的を達成するために本発明は、前記のコ
ンパレータを２種設け、すなわち第１の基準電圧
Vr1を有する第１のコンパレータと第２の基準電
圧Vr2を有する第２のコンパレータとを設け、該
第１および第２のコンパレータは共通に前記可変
利得増幅器の出力を入力とし、これら第１および
第２のコンパレータからの第１の出力パルスおよ
び第２の出力パルスのパルスモードから最適
AGCレベルをサーチするようにしたことを特徴
とするものである。(5) Structure of the Invention In order to achieve the above object, the present invention provides two types of comparators, namely, the first reference voltage
A first comparator having a reference voltage V r1 and a second comparator having a second reference voltage V r2 are provided, the first and second comparators commonly receive the output of the variable gain amplifier, and the first comparator has a second reference voltage V r2 . and the pulse mode of the first output pulse and the second output pulse from the second comparator.
The feature is that the AGC level is searched.
(6) 発明の実施例 以下本発明を説明する。(6) Examples of the invention The present invention will be explained below.
第３図は本発明に基づくデイジタル制御形
AGC回路の一実施例を示す回路図である。本図
に示す如く、第１および第２図に示したコンパレ
ータ１４は、第１のコンパレータ１４−１および
第２のコンパレータ１４−２に分割されており、
各々は共通にAGC制御出力信号Sputを受信する一
方、第１の基準電圧Vr1および第２の基準電圧
Vr2それぞれ比較基準レベルに持つ。 Figure 3 shows a digital control type based on the present invention.
FIG. 2 is a circuit diagram showing an example of an AGC circuit. As shown in this figure, the comparator 14 shown in FIGS. 1 and 2 is divided into a first comparator 14-1 and a second comparator 14-2,
each receives the AGC control output signal S put in common, while the first reference voltage V r1 and the second reference voltage
V r2 each has a comparison reference level.
第４図は第３図における要部の信号を表わす波
形図である。本図において第(1)欄はAGC制御出
力信号Sputと第１および第２の基準電圧Vr1，Vr2
の関連を示す波形図であり、信号Sputのレベルが
Vr1を超える期間中、第１の出力パルスＣ１が得
られ（同図第(2)欄）、Vr2を超える期間中、第２
の出力パルスＣ２が得られる（同図第(3)欄）。な
お、同図の最上段の“１”“０”“１”……は
“１”“０”のデータパターンを例示している。デ
ータ“０”のときは出力パルスＣ１もＣ２もな
い。一方データ“１”のときは、同図中最下段に
記した○ FIG. 4 is a waveform diagram showing the main signals in FIG. 3. In this figure, column (1) shows the AGC control output signal S put and the first and second reference voltages V r1 and V r2
This is a waveform diagram showing the relationship between
During the period exceeding V r1 , the first output pulse C1 is obtained (column (2) in the same figure), and during the period exceeding V r2 , the second output pulse C1 is obtained.
An output pulse C2 is obtained (column (3) in the figure). Note that "1", "0", "1", . . . in the top row of the figure exemplifies a data pattern of "1" and "0". When the data is "0", there is no output pulse C1 or C2. On the other hand, when the data is “1”, the circle marked at the bottom of the figure
Claims (1)
データの“１”，“０”をそのままアナログレベル
で表した入力信号を受信する可変利得増幅器と、 該可変利得増幅器からの出力信号と第１の基準
電圧とを入力として比較する第１のコンパレータ
と、 該可変利得増幅器からの出力信号と第２の基準
電圧とを入力として比較する第２のコンパレータ
と、 該第１のコンパレータからの第１の出力パルス
および該第２のコンパレータからの第２の出力パ
ルスを入力とし、該第１の出力パルスおよび該第
２の出力パルスが共に存在する第１事象および該
第２の出力パルスのみが存在する第２事象を識別
して、該第１事象の識別時にあつては前記可変利
得増幅器の利得を低減し、引続く該第２事象の識
別時において該利得の低減を停止する制御回路と
からなることを特徴とするデイジタル制御形
AGC回路。 ２ 前記第１事象の生起回数が所定値を超えるこ
とを検出する毎に前記利得を徐々に低減する特許
請求の範囲第１項記載のデイジタル制御形AGC
回路。 ３ 前記第２事象の生起回数が所定値を超えるこ
とを検出して前記利得の低減を停止する特許請求
の範囲第２項記載のデイジタル制御形AGC回路。 ４ 前記第１の基準電圧から前記第２の基準電圧
を設定する分圧回路を備える特許請求の範囲第３
項記載のデイジタル制御形AGC回路。 ５ 前記第１の基準電圧のレベルを100％とする
と、前記第２の基準電圧のレベルが約50％である
特許請求の範囲第４項記載のデイジタル制御形
AGC回路。[Scope of Claims] 1. A variable gain amplifier that receives an input signal to which AGC is applied and that represents data "1" and "0" as they are at an analog level; a first comparator that compares an output signal with a first reference voltage as an input; a second comparator that compares an output signal from the variable gain amplifier with a second reference voltage as an input; a first output pulse from a comparator and a second output pulse from the second comparator; a first event and a second event in which the first output pulse and the second output pulse both exist; identifying a second event in which only an output pulse is present, reducing the gain of the variable gain amplifier upon identification of the first event, and stopping the reduction of the gain upon subsequent identification of the second event; A digital control type characterized by consisting of a control circuit that
AGC circuit. 2. The digitally controlled AGC according to claim 1, wherein the gain is gradually reduced each time it is detected that the number of occurrences of the first event exceeds a predetermined value.
circuit. 3. The digitally controlled AGC circuit according to claim 2, which stops reducing the gain upon detecting that the number of occurrences of the second event exceeds a predetermined value. 4. Claim 3, comprising a voltage dividing circuit that sets the second reference voltage from the first reference voltage.
The digitally controlled AGC circuit described in . 5. The digital control type according to claim 4, wherein the level of the second reference voltage is approximately 50% when the level of the first reference voltage is 100%.
AGC circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9945683A JPS59224907A (en) | 1983-06-06 | 1983-06-06 | Digital control type agc circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9945683A JPS59224907A (en) | 1983-06-06 | 1983-06-06 | Digital control type agc circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59224907A JPS59224907A (en) | 1984-12-17 |
| JPH0223098B2 true JPH0223098B2 (en) | 1990-05-22 |
Family
ID=14247820
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9945683A Granted JPS59224907A (en) | 1983-06-06 | 1983-06-06 | Digital control type agc circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59224907A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| ES2048221T3 (en) * | 1989-02-27 | 1994-03-16 | Siemens Nixdorf Inf Syst | CIRCUIT PROVISION FOR DIGITAL ADJUSTMENT OF THE AMPLIFICATION FACTOR OF A DIGITAL ADJUSTABLE RECEPTION AMPLIFIER. |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5877311A (en) * | 1981-11-02 | 1983-05-10 | Toshiba Corp | Automatic gain controlling circuit |
-
1983
- 1983-06-06 JP JP9945683A patent/JPS59224907A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5877311A (en) * | 1981-11-02 | 1983-05-10 | Toshiba Corp | Automatic gain controlling circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59224907A (en) | 1984-12-17 |
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