JPH02228897A - Vertical deflection circuit - Google Patents

Vertical deflection circuit

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Publication number
JPH02228897A
JPH02228897A JP1050583A JP5058389A JPH02228897A JP H02228897 A JPH02228897 A JP H02228897A JP 1050583 A JP1050583 A JP 1050583A JP 5058389 A JP5058389 A JP 5058389A JP H02228897 A JPH02228897 A JP H02228897A
Authority
JP
Japan
Prior art keywords
vertical
deflection
switch
circuit
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1050583A
Other languages
Japanese (ja)
Other versions
JPH0759043B2 (en
Inventor
Hideyuki Yasuda
秀幸 安田
Hiroshi Osawa
大沢 弘
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP1050583A priority Critical patent/JPH0759043B2/en
Publication of JPH02228897A publication Critical patent/JPH02228897A/en
Publication of JPH0759043B2 publication Critical patent/JPH0759043B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Testing, Inspecting, Measuring Of Stereoscopic Televisions And Televisions (AREA)
  • Details Of Television Scanning (AREA)

Abstract

PURPOSE:To prevent distortion from being generated on a picture by switching the crest value of a vertical deflecting voltage during a vertical fly-back interval in correspondence to the frequency of a vertical synchronizing signal. CONSTITUTION:A pump-up switch SW2 is turned on between terminals (d)-(e) during the fly-back interval according to the detection signal of a detection circuit 6 and a voltage is applied from a terminal (g) of a 60/120Hz switch SW1 to a terminal (j). During a time excepting for the fly-back interval, the switch is turned on and a voltage V1 is applied to the terminal (j) of a vertical output circuit 3. When vertical deflection is 60Hz, the 60/120Hz switch SW1 is turned on between the terminals (g)-(i) and when the deflection is 120Hz, the switch is turned on between the terminals (g)-(h) by manual operation. Thus, when the frequency of the vertical synchronizing signal reproduces the video signal of 120Hz, the vertical fly-back is made early since the deflecting voltage of the vertical fly-back period is higher in comparison with the case of 60Hz. Then, a display period is prolonged and the distortion is not generated on the picture.

Description

【発明の詳細な説明】 童呈上■科■公国 本発明は時分割シャッタ一方式による立体テレビジョン
受像機等に利用される垂直偏向回路に関するものである
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a vertical deflection circuit used in a stereoscopic television receiver or the like using a time-sharing shutter system.

従来■茨徂 従来の時分割シャッタ一方式による立体テレビジョンの
原理は第9図〜第11図に示すようなものである。これ
は人間の目の両眼視差を利用したものであり、左右の目
100及び101の網膜には、異なった角度から見た物
体の像が投影されており、それらは融合して1つの立体
像として見える。
2. Conventional Principles The principle of conventional stereoscopic television using one type of time-sharing shutter is as shown in FIGS. 9 to 11. This takes advantage of the binocular parallax of the human eye, and images of objects seen from different angles are projected onto the retinas of the left and right eyes 100 and 101, and these are fused into one three-dimensional image. visible as a statue.

まず、第9図(イ)はあ゛る水平面に存在する2点P、
Qがy4膜に結像する梯子を模式的に表わしている。こ
れを立体カメラの撮影の場合に当てはめると第9図(ロ
)のようになる。同図において、左カメラ102は左目
100に、右カメラ103は右目101に対応する。左
カメラ102で撮像した像(P’L)が右カメラ103
で撮像した像(p’R)の左に結像する場合と、左カメ
ラ102で撮像した像(0”L)が右カメラ103で撮
像した像(Q”、)に結像される場合に分かれる。これ
は第9図(ハ)のようにテレビのブラウン管面104を
考えると、Qはテレビの手前に見え、Pは奥まって見え
ることになる。そこで第10図に時分割シャッタ一方式
による立体テレビジョンシステムの構成例を示す。左カ
メラ102゜右カメラ103は第9図(ロ)と同様な関
係にあり、左カメラ102によって憑像されたフレーム
単位の情報LI+ Lt+ L31 ・・・+ll+1
、右カメラ103によし って撮像されたフレーム単位の情報RI+ R1+ R
3t・・・I R3++を出力する。左カメラ102か
らの情報は交互に切換ねるスイッチ105の端子すへ、
右カメラ103からの情報は端子aへ入力される。各情
報は図中に示す様にL I+ L!+ L3+ ”’r
 L□1+ R1+Rt+ R3+”’+ R*++ 
と601(zの垂直同期信号周期で出力される。スイッ
チ105は60Hzの垂直同期信号周期で端子b−c間
、端子a−c間と切換るので端子CからはLl+ RZ
+ L;l+ R4+ ・・・となる立体映像信号が出
力される。つまりここで言う立体映像信号とは、60H
z垂直同期信号周期(lフレーム単位)の左右情報1組
を1フイールドとする映像信号になる。そこで該立体映
像信号を第11図の立体テレビ106に入力すると1フ
レーム毎に左右の情報がl/60周期で表示される。そ
の表示画面を立体スコープ107を通して両眼で見ると
する。該立体スコープ107は左シャッター108と右
シャッター109から成り、立体映像信号と同じ垂直同
期周期で相反する開閉動作をする0例えば第10図に示
す立体映像信号のし、フレームの信号(左カメラからの
情報)が第11図の立体テレビ106に表示されている
時は、立体スコープ107の左シャッター108は開、
右シャッター109は閉になり、左iI!iooから左
シャッター108を通して左カメラ102からの情報の
みを見ることになる。次にR2フレームの信号(右カメ
ラからの情報)が表示されている時は立体スコープ10
7の左シャッター108は閉、右シャッター109は開
になり、右眼101から右シャッター109を通して右
カメラ103からの情報のみを見ることになる0以上の
各動作を60Hzの垂直同期信号周期で繰り返すと人間
の目の残像効果と相まって第9図(ハ)に示した両眼視
差の映像情報を見ているのと等価になり、立体映像が実
現出来る。
First, Figure 9(a) shows two points P existing on a horizontal plane,
Q schematically represents a ladder where images are formed on the y4 membrane. If this is applied to the case of photographing with a three-dimensional camera, the result will be as shown in Fig. 9 (b). In the figure, the left camera 102 corresponds to the left eye 100 and the right camera 103 corresponds to the right eye 101. The image (P'L) captured by the left camera 102 is the right camera 103
When an image is formed to the left of the image (p'R) taken by the left camera 102, and when an image (0''L) taken by the left camera 102 is formed to the image (Q'',) taken by the right camera 103, Divided. This means that if we consider the cathode ray tube surface 104 of the television as shown in FIG. 9(c), Q will appear in front of the television, and P will appear in the back. Therefore, FIG. 10 shows an example of the configuration of a stereoscopic television system using one type of time-sharing shutter. The left camera 102 and the right camera 103 have the same relationship as in FIG.
, frame-by-frame information RI+ R1+ R captured by the right camera 103
3t...I Output R3++. Information from the left camera 102 is sent to a terminal of a switch 105 that switches alternately.
Information from the right camera 103 is input to terminal a. Each information is L I+ L! as shown in the figure. +L3+”'r
L□1+ R1+Rt+ R3+”'+ R*++
and 601 (z) are output at the vertical synchronization signal period. Since the switch 105 switches between terminals b and c and between terminals a and c at the vertical synchronization signal period of 60Hz, Ll+RZ is output from terminal C.
+L;l+R4+... A stereoscopic video signal is output. In other words, the stereoscopic video signal referred to here is 60H
It becomes a video signal in which one set of left and right information of the z vertical synchronization signal period (l frame unit) constitutes one field. Therefore, when the stereoscopic video signal is input to the stereoscopic television 106 shown in FIG. 11, left and right information is displayed for each frame at a cycle of 1/60. Assume that the display screen is viewed with both eyes through the stereoscopic scope 107. The stereoscopic scope 107 consists of a left shutter 108 and a right shutter 109, which open and close in opposite directions with the same vertical synchronization period as the stereoscopic video signal.For example, the stereoscopic video signal shown in FIG. information) is displayed on the stereoscopic television 106 in FIG. 11, the left shutter 108 of the stereoscopic scope 107 is opened;
The right shutter 109 is closed, and the left iI! From ioo, only information from the left camera 102 is seen through the left shutter 108. Next, when the R2 frame signal (information from the right camera) is displayed, the stereoscope 10
7, the left shutter 108 is closed, the right shutter 109 is opened, and the right eye 101 sees only information from the right camera 103 through the right shutter 109. Each operation above 0 is repeated at a vertical synchronization signal period of 60 Hz. Combined with the afterimage effect of the human eye, this becomes equivalent to viewing the binocular parallax video information shown in FIG. 9(C), and a three-dimensional image can be realized.

つまり第11図に示す立体テレビ106は、現在一般に
使用されている垂直60Hz、水平15KHzのラスク
ースキャンテレビが使用出来ることになる。
In other words, the stereoscopic television 106 shown in FIG. 11 can be a Lascous scan television of 60 Hz vertically and 15 KHz horizontally, which is currently commonly used.

が”しようとする晋 従来の時分割シャッタ一方式による立体テレビジョンシ
ステムは、通常一般の垂直偏向周波数60Hzのデイス
プレィを使用している為、左右映像の繰返し周波数も6
0Hzで行なわれる。そのため映像としてはチカチカし
たフリッカ−が表われ、立体視効果を妨げる。そこで該
フリッカ−の発生を解決する為、繰返し周波数を倍の1
20Hzに変更することが考えられるが、垂直帰線時間
は周波数に対する依存性が少ない為、周波数の変更のみ
では表示画面に歪みが出て正常な映像が得られない。
However, since conventional 3D television systems using one type of time-sharing shutter normally use a display with a general vertical deflection frequency of 60Hz, the repetition frequency of the left and right images is also 60Hz.
This is done at 0Hz. Therefore, flickering appears in the image, which interferes with the stereoscopic effect. Therefore, in order to solve the occurrence of flicker, the repetition frequency was doubled by 1.
It is conceivable to change the frequency to 20 Hz, but since the vertical retrace time has little dependence on frequency, changing the frequency alone will distort the display screen and make it impossible to obtain a normal image.

本発明はこのような点に鑑みなされたものであって、垂
直偏向周波数を変えた場合に画面上に歪が生じないよう
に工夫した新規な垂直偏向回路を提供することを目的と
する。
The present invention has been made in view of these points, and it is an object of the present invention to provide a novel vertical deflection circuit designed to prevent distortion from occurring on the screen when the vertical deflection frequency is changed.

量 を”るための 上記の目的を達成するため本発明では、垂直同期信号の
周波数が異なる映像を表示することのできるテレビジョ
ン受像機用の垂直偏向回路において、垂直同期信号の周
波数に応じて垂直帰線期間の垂直偏向電圧の波高値を切
換える手段を具備した構成としている。
In order to achieve the above-mentioned object of increasing the frequency of the vertical synchronizing signal, the present invention provides a vertical deflection circuit for a television receiver capable of displaying images with different frequencies of the vertical synchronizing signal. The configuration includes means for switching the peak value of the vertical deflection voltage during the vertical retrace period.

また、本発明は、垂直同期信号の周波数が異なる映像を
表示することのできるテレビジョン受像機用の垂直偏向
回路において、垂直同期信号の周波数が変わると垂直帰
線期間中の垂直偏向電圧の波高値を垂直同期に同期して
且つ偏向コイルに大きな逆起電力が発生していないとき
に切換える回路を有するように構成している。
Furthermore, the present invention provides a vertical deflection circuit for a television receiver that can display images with different frequencies of vertical synchronization signals, in which the vertical deflection voltage changes during the vertical retrace period when the frequency of the vertical synchronization signal changes. It is configured to include a circuit that switches the high value in synchronization with vertical synchronization and when no large back electromotive force is generated in the deflection coil.

止−■ このような構成によると、例えば垂直同期信号の周波数
が120Hzの映像信号を再生する場合、垂直帰線期間
の偏向電圧が60Hzの場合に比し高くなるので、垂直
帰線が早(なり、その分、表示期間が長くなって画面上
に歪が生じない。
With this configuration, for example, when reproducing a video signal with a vertical synchronizing signal frequency of 120 Hz, the deflection voltage during the vertical retrace period is higher than when the frequency is 60 Hz, so the vertical retrace occurs quickly ( Therefore, the display period becomes longer and no distortion occurs on the screen.

また、前記偏向電圧の切換えを偏向コイルに高い逆起電
力が生じている期間を避けて行なうようにすると、回路
部品に大きなストレスを与えない。
Moreover, if the switching of the deflection voltage is performed while avoiding a period when a high back electromotive force is generated in the deflection coil, large stress will not be applied to the circuit components.

裏」L± 以下本発明を実施例に基き詳細に説明する。第1図は本
実施例のブロック図である。同図において、lは入力さ
れる垂直同期信号により同期をとり自動発振をする垂直
発振回路、2は垂直発振回路1で発生した鋸歯状波電圧
を最終段の垂直出力回路3で十分に偏向コイル4をドラ
イブ出来る信号レベルに増幅、波形整形する増幅・整形
回路である。垂直出力回路3は偏向コイル4に十分な電
流を流すための電力増幅をする。5はポンプアップ回路
であり、垂直出力回路3へ各電源を切換えて供給してい
る。偏向コイル4は垂直出力回路3から供給される鋸歯
状波電流により電子ビームを上から下へ(垂直に)走査
させるものである。
Back" L± The present invention will be described in detail below based on examples. FIG. 1 is a block diagram of this embodiment. In the figure, l is a vertical oscillation circuit that synchronizes with an input vertical synchronization signal and automatically oscillates, and 2 is a vertical oscillation circuit that generates a sawtooth wave voltage generated in the vertical oscillation circuit 1 and sends it to the final stage vertical output circuit 3. This is an amplification/shaping circuit that amplifies and shapes the waveform to a signal level that can drive 4. The vertical output circuit 3 performs power amplification to allow sufficient current to flow through the deflection coil 4. A pump-up circuit 5 switches and supplies each power source to the vertical output circuit 3. The deflection coil 4 scans the electron beam from top to bottom (vertically) using a sawtooth wave current supplied from the vertical output circuit 3.

第2図は前記垂直出力回路3.ポンプアップ回路5.偏
向コイル4からなる部分の一実施例を示す。ここでは垂
直出力回路3はプッシュプルアンプのようなトランジス
タ電力増幅器であり、偏向コイル4.コンデンサC1抵
抗Rに偏向型a I oを流す、該垂直出力回路3の端
子jにはポンプアップ回路5からの電源電圧Vnがかか
るため、出力端子kにおける出力波形電圧Vou tは
VoutζVnとなる。
FIG. 2 shows the vertical output circuit 3. Pump up circuit 5. An example of a portion consisting of a deflection coil 4 is shown. Here, the vertical output circuit 3 is a transistor power amplifier such as a push-pull amplifier, and the deflection coil 4. Since the power supply voltage Vn from the pump-up circuit 5 is applied to the terminal j of the vertical output circuit 3, which causes the deflection type a I o to flow through the capacitor C1 resistor R, the output waveform voltage Vout at the output terminal k becomes VoutζVn.

ポンプアップ回路5は電源より与えられる電圧v1゜V
t、 Vsを60/120HzスイッチSW、  と、
ポンプアップスイッチ5IIIzの2つのスイッチでそ
れぞれ切換えて垂直出力回路3の電源電圧として供給す
る。ポンプアップスイッチSl’l! は端子d、e、
fからなり、帰線検出回路6からの検出信号SDにより
切換えられる。帰線検出回路6は、垂直出力回路3の出
力電圧波形より帰線期間のみを抽出する回路であり、第
2図に示すように帰線期間のみハイレベルになるパルス
を検出信号SDとして出力する。この検出信号SDのハ
イレベルつまり帰線期間はポンプアップスイッチSW、
の端子d−e間がONになり、端子jには60/120
HzスイッチSW、の端子gからの電圧が加えられる。
The pump-up circuit 5 receives a voltage v1°V from the power supply.
t, Vs as 60/120Hz switch SW, and
The two switches of the pump-up switch 5IIIz switch the voltage and supply it as the power supply voltage to the vertical output circuit 3. Pump up switch Sl'l! are terminals d, e,
f, and is switched by the detection signal SD from the retrace detection circuit 6. The retrace detection circuit 6 is a circuit that extracts only the retrace period from the output voltage waveform of the vertical output circuit 3, and outputs a pulse that is at a high level only during the retrace period as a detection signal SD, as shown in FIG. . During the high level of this detection signal SD, that is, during the retrace period, the pump-up switch SW,
is turned on between terminals d and e, and 60/120 is applied to terminal j.
A voltage from terminal g of the Hz switch SW is applied.

検出信号SDがローレベルつまり帰線期間以外の時間は
ポンプアップスイッチSW2の端子d−f間がONにな
り電圧v1が垂直出力回路3の端子jに加えられる。こ
れは電源電圧を高くすると垂直出力回路3の消費電力が
増加し、発熱などの問題が起こるので高い電源電圧V、
、V、は垂直帰線期間のみ加えることとし、表示期間は
最小限の電源電圧v1に切換えることで総合的な低消費
電力化を図るためである。
When the detection signal SD is at a low level, that is, at times other than the retrace period, the terminals d and f of the pump-up switch SW2 are turned on, and the voltage v1 is applied to the terminal j of the vertical output circuit 3. This is because when the power supply voltage is increased, the power consumption of the vertical output circuit 3 increases and problems such as heat generation occur.
, V are added only during the vertical retrace period, and the display period is switched to the minimum power supply voltage v1 in order to reduce overall power consumption.

因みに電源電圧はV s > V z > V +の関
係にある。
Incidentally, the relationship between the power supply voltages is V s > V z > V +.

60/1208Zスイッチ針、は端子H,h、iからな
り、端子りは電[Vt (120Hz用)へ、端子iは
電源V□(60Hz市)へ接続されている。垂直偏向が
60Hzの時は端子g−4間を、120Hzの時はg−
h間を手動操作でONにする。つまり垂直偏向が60+
lzの時、電源電圧v2が端子i−g−eと導かれ、垂
直帰線期間に垂直出力回路3の電源電圧として加えられ
る。次に、垂直120Hz偏向の場合、電源V、が端子
h−g−eと導かれて、垂直帰線期間にやはり垂直出力
回路3の電源電圧として加えられる。
The 60/1208Z switch needle consists of terminals H, h, and i, the terminal is connected to the power supply Vt (for 120Hz), and the terminal i is connected to the power supply V□ (for 60Hz). When the vertical deflection is 60Hz, connect between terminals g-4, and when the vertical deflection is 120Hz, connect between terminals g-4.
Turn on the h interval manually. So the vertical deflection is 60+
At the time of lz, the power supply voltage v2 is led to the terminals i-ge and is applied as the power supply voltage to the vertical output circuit 3 during the vertical retrace period. Next, in the case of vertical 120 Hz deflection, the power supply V is led to the terminals hge and is also applied as the power supply voltage of the vertical output circuit 3 during the vertical retrace period.

これら偏向波形と各スイッチSW+、 5lll!の状
態を示したものが第3図〜第6図である。
These deflection waveforms and each switch SW+, 5lll! FIGS. 3 to 6 show the state.

尚、第3図が60Hz偏向の場合の偏向波形を示し、第
4図がその場合の各スイッチSW、、 SW2の状態を
示している。一方、第5図が120Hz偏向の場合の偏
向波形を示し、第6図がその場合におけるスイッチSW
、、 SW!の状態を示している。
Incidentally, FIG. 3 shows the deflection waveform in the case of 60 Hz deflection, and FIG. 4 shows the states of each switch SW, SW2 in that case. On the other hand, Fig. 5 shows the deflection waveform in the case of 120Hz deflection, and Fig. 6 shows the switch SW in that case.
,, SW! It shows the status of.

60)1z偏向の時、1. + 1.が表示期間+ t
3が垂直帰線期間であり、該t、u間にかかる電圧はV
l+表示期間1.+1.にががる電圧はV、である。一
方、1201(2偏向の時、垂直帰線期間t、lにかか
る電圧はV1+表示期間t% +t、’ にかかる電圧
はV、になる。ここで、60Hz偏向の時の各波形(a
)の周期に対して120Hz偏向の時の各波形周期は約
半分にならなければならない、これは垂直発振回路1に
入力する垂直同期信号周波数と該垂直発振回路1の周波
数を倍にすることにより達成できるが、垂直帰線は偏向
電流■。の急激な鋸歯状波による変化により偏向コイル
4に逆起電力が発生することにより作られているため、
その帰線期間を短くするためには電源電圧を高(して、
逆起電力エネルギーを放出させなけばならない。そのた
め60)1zの帰線期間t3の時の電圧V!に対して、
120Hzの帰線期間t、l の時はv2より高い電圧
V、を加えるのである。これにより垂直偏向を倍の12
0Hzにしても必要十分な表示期間が確保できる。よっ
て垂直偏向が60Hz、 12082のいずれにおいて
も画面に歪を生じさせない垂直偏向回路が実現できる。
60) At the time of 1z deflection, 1. +1. is the display period + t
3 is the vertical retrace period, and the voltage applied between t and u is V
l+display period 1. +1. The bitter voltage is V. On the other hand, 1201 (at the time of 2 deflections, the voltage applied to the vertical blanking period t, l is V1 + the voltage applied to the display period t% + t,' is V. Here, each waveform (a
) The period of each waveform at the time of 120Hz deflection must be approximately half of the period of 120Hz deflection. Although it can be achieved, the vertical retrace is a deflection current■. It is created by generating a back electromotive force in the deflection coil 4 due to a sudden change in the sawtooth wave.
In order to shorten the retrace period, increase the power supply voltage (
The back electromotive force energy must be released. Therefore, 60) Voltage V during retrace period t3 of 1z! For,
During the retrace period t,l of 120 Hz, a voltage V higher than v2 is applied. This doubles the vertical deflection by 12
Even at 0 Hz, a necessary and sufficient display period can be ensured. Therefore, it is possible to realize a vertical deflection circuit that does not cause distortion on the screen when the vertical deflection is either 60 Hz or 12082 Hz.

ところで、上述のように垂直帰線期間のみ高い電源電圧
を加えて垂直偏向電圧の波高値を高くする場合に偏向コ
イルに高い逆起電力が発生している時に60/120H
zスイッチSW、を操作して電源電圧を切換える可能性
があり、各回路部品に大きな電気的ストレスを与えてし
まう。
By the way, as mentioned above, when applying a high power supply voltage only during the vertical retrace period to increase the peak value of the vertical deflection voltage, when a high back electromotive force is generated in the deflection coil, the 60/120H
There is a possibility that the power supply voltage may be changed by operating the z switch SW, which causes a large electrical stress to be applied to each circuit component.

そこで、第7図に示す実施例は垂直帰線期間中に印加さ
れる電源電圧の切換えを偏向コイルに大きな逆起電力が
発生していないときに行うようになっている。同図にお
いて、ポンプアップ回路5は第2図の実施例の構成に更
にラッチ回路7と60/120Hz指示スイツチ8を有
している。ラッチ回路7のクロック端子CMには帰線検
出回路6の出力が加えられ、データ端子りには60/ 
120Hz指示スイツチ8の出力が与えられる。これら
の入力とQ出力との関係は第8図に示される。この構成
によれば、60/120Hz指示スイツチ8がどのよう
なタイミングで切換られても必ず垂直帰線期間の始め(
従って偏向コイルに高い逆起電力が発生していないとき
)に60/12011zスイッチ籏、が切換えられる。
Therefore, in the embodiment shown in FIG. 7, the power supply voltage applied during the vertical retrace period is switched when no large back electromotive force is generated in the deflection coil. In the same figure, a pump-up circuit 5 has a latch circuit 7 and a 60/120 Hz instruction switch 8 in addition to the structure of the embodiment shown in FIG. The output of the retrace detection circuit 6 is applied to the clock terminal CM of the latch circuit 7, and the output of the retrace detection circuit 6 is applied to the data terminal CM.
The output of the 120Hz indicating switch 8 is provided. The relationship between these inputs and the Q output is shown in FIG. According to this configuration, no matter what timing the 60/120 Hz instruction switch 8 is switched, the start of the vertical retrace period (
Therefore, the 60/12011z switch is switched when no high back electromotive force is generated in the deflection coil.

従って、回路部品に大きな電気的ストレスを与えない。Therefore, no large electrical stress is applied to the circuit components.

光9I裏九果 以上述べたように本発明によれば、極めて簡易な回路構
成で垂直偏向を例えば60Hz、 1201(zの両方
の周波数で適正に行なえ、且つ垂直帰線期間のみ前記周
波数に応じて垂直偏向電圧の波高値を変えるようにして
いるので、低消費電力化を図ると共にフリッカ−及び画
面歪を生じさせない垂直偏向回路を実現できる。
As described above, according to the present invention, vertical deflection can be properly performed at both frequencies, for example, 60 Hz and 1201 (z) with an extremely simple circuit configuration, and only during the vertical retrace period can the beam be deflected according to the frequency. Since the peak value of the vertical deflection voltage is changed by changing the peak value of the vertical deflection voltage, it is possible to realize a vertical deflection circuit that reduces power consumption and does not cause flicker or screen distortion.

また、本発明によれば垂直帰線期間の垂直偏向電圧の波
高値の切換えを偏向コイルに高い逆起電力が発生してい
ないときに行なうので、回路部品に大きな電気的ストレ
スを与えることがない。
Furthermore, according to the present invention, the peak value of the vertical deflection voltage during the vertical retrace period is switched when a high back electromotive force is not generated in the deflection coil, so that no large electrical stress is applied to the circuit components. .

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の垂直偏向回路のブロック図であり、第
2図はその要部について一実施例を示す図、第3図、第
4図、第5図及び第6図はその説明図である。第7図は
第1図における要部の他の実施例を示す図であり、第8
図はその説明図である。第9図2第10図及び第11図
は時分割シャッタ一方式の立体テレビを説明するための
図である。 3・−垂直出力回路、4−・・−偏向コイル。 5−ポンプアップ回路16・−垂直帰線検出回路7−ラ
ッチ回路、8・・・60/120Hz指示スイツチSW
+−−−60/120Hzスイツチ、。 SW、−−ポンプアップスイッチ。 VI+ Vt、 V3’−−一電源電圧。 第7図
FIG. 1 is a block diagram of the vertical deflection circuit of the present invention, FIG. 2 is a diagram showing one embodiment of the main parts thereof, and FIGS. 3, 4, 5, and 6 are explanatory diagrams thereof. It is. FIG. 7 is a diagram showing another embodiment of the main part in FIG.
The figure is an explanatory diagram thereof. FIG. 9, FIG. 10, and FIG. 11 are diagrams for explaining a time-division shutter type three-dimensional television. 3.--vertical output circuit, 4--deflection coil. 5-pump up circuit 16--vertical retrace detection circuit 7-latch circuit, 8...60/120Hz indication switch SW
+---60/120Hz switch. SW, --Pump up switch. VI+ Vt, V3'-- one power supply voltage. Figure 7

Claims (2)

【特許請求の範囲】[Claims] (1)垂直同期信号の周波数が異なる映像を表示するこ
とのできるテレビジョン受像機用の垂直偏向回路におい
て、垂直同期信号の周波数に応じて垂直帰線期間の垂直
偏向電圧の波高値を切換える手段を具備したことを特徴
とする垂直偏向回路。
(1) In a vertical deflection circuit for a television receiver capable of displaying images with different vertical synchronization signal frequencies, means for switching the peak value of the vertical deflection voltage during the vertical blanking period according to the frequency of the vertical synchronization signal. A vertical deflection circuit characterized by comprising:
(2)垂直同期信号の周波数が異なる映像を表示するこ
とのできるテレビジョン受像機用の垂直偏向回路におい
て、垂直同期信号の周波数が変わると垂直帰線期間中の
垂直偏向電圧の波高値を垂直同期に同期して且つ偏向コ
イルに大きな逆起電力が発生していないときに切換える
回路を有することを特徴とする垂直偏向回路。
(2) In a vertical deflection circuit for a television receiver that can display images with different vertical synchronization signal frequencies, when the frequency of the vertical synchronization signal changes, the peak value of the vertical deflection voltage during the vertical retrace period A vertical deflection circuit characterized by having a circuit that switches in synchronization and when a large back electromotive force is not generated in a deflection coil.
JP1050583A 1989-03-02 1989-03-02 Vertical deflection circuit Expired - Fee Related JPH0759043B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1050583A JPH0759043B2 (en) 1989-03-02 1989-03-02 Vertical deflection circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1050583A JPH0759043B2 (en) 1989-03-02 1989-03-02 Vertical deflection circuit

Publications (2)

Publication Number Publication Date
JPH02228897A true JPH02228897A (en) 1990-09-11
JPH0759043B2 JPH0759043B2 (en) 1995-06-21

Family

ID=12863001

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1050583A Expired - Fee Related JPH0759043B2 (en) 1989-03-02 1989-03-02 Vertical deflection circuit

Country Status (1)

Country Link
JP (1) JPH0759043B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04110069U (en) * 1991-03-06 1992-09-24 日本電気ホームエレクトロニクス株式会社 Vertical deflection device for high-definition television receivers
EP0789485A3 (en) * 1996-02-09 1998-12-30 Sanyo Electric Co. Ltd Vertical deflecting circuit

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5536606U (en) * 1978-08-28 1980-03-08
JPS5678278A (en) * 1979-11-30 1981-06-27 Jeol Ltd Deflecting circuit of scanning type electron microscope or the like
JPS5685458U (en) * 1979-12-05 1981-07-09
JPS63157570A (en) * 1986-12-20 1988-06-30 Nec Home Electronics Ltd Vertical deflection circuit

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5536606U (en) * 1978-08-28 1980-03-08
JPS5678278A (en) * 1979-11-30 1981-06-27 Jeol Ltd Deflecting circuit of scanning type electron microscope or the like
JPS5685458U (en) * 1979-12-05 1981-07-09
JPS63157570A (en) * 1986-12-20 1988-06-30 Nec Home Electronics Ltd Vertical deflection circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04110069U (en) * 1991-03-06 1992-09-24 日本電気ホームエレクトロニクス株式会社 Vertical deflection device for high-definition television receivers
EP0789485A3 (en) * 1996-02-09 1998-12-30 Sanyo Electric Co. Ltd Vertical deflecting circuit

Also Published As

Publication number Publication date
JPH0759043B2 (en) 1995-06-21

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