JPH02228020A - Manufacture of integrated circuit - Google Patents

Abstract

PURPOSE:To form a circuit accurately by changing an area to be exposed in an exposing step, and repeating a patterning step. CONSTITUTION:The inside of a silicon wafer 22 is divided into several regions. Some regions 44 among said regions are picked up and selectively exposed. The wafer 22 is etched and machined. At this time, resist which is not exposed remains in the regions 44 which are not selected in the selecting and exposing step. Therefore, a large amount of polymers are formed. Then, for example, when a coarse end dense pattern is present in the selected region, the approximately same amount of polymers from the non-exposed resist are attached to the side wall of a wiring region. Dispersion in wiring widths after machining can be avoided. Thereafter, photoresist is applied in the application step again, and the non-selected regions are newly selected. The dispersion in wiring widths in the selected regions can be avoided by the same way by repeating the patterning step. In this way, the circuit can be formed accurately.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an integrated circuit manufacturing method for forming an integrated circuit through a patterning process using a photoresist.

[Prior Art] Semiconductor integrated circuits, in which 106 or more elements are formed on a microscopic semiconductor chip, are used in computers and various other devices, and as their degree of integration improves, how to accurately mass-produce them becomes a major issue. It has become a challenge.

FIG. 6 shows a flowchart of a conventional integrated circuit manufacturing method. An oxide film is formed on a semiconductor substrate in an oxide film formation process 10, and a polycrystalline silicon film is formed on the oxide film in a polycrystalline silicon deposition process. Thereafter, the circuit is patterned in a patterning process consisting of a coating process 14, an exposure process 16, and a processing process 18, and finally, in a wiring process 20, wiring of each element is performed using aluminum.

Here, of the series of processes described above, the lithography process 14.16 will be explained in more detail with reference to FIG. FIG. 8 shows an IX-IX cross section of the micro region 24 in the silicon wafer 22 shown in FIG. 7, and FIG. is formed, and furthermore, in the coating process 14, a positive resist 3 becomes alkali-soluble by irradiation with ultraviolet rays.
2 is spin coded.

Next, in an exposure process 16, the positive resist film 32 is irradiated with ultraviolet rays for a certain period of time through a photomask, and the exposed portions are dissolved in a basic aqueous solution, as shown in FIG.

Following the above lamination lithography process, processing process 1
At step 8, reactive ion etching (RIE) is performed in a gas containing fluorine or chlorine using the resist remaining on the polycrystalline silicon film 30 in the exposure process 16 as a mask to process the polycrystalline silicon film 30. FIG. 8C shows the state after processing.

As described above, conventionally, the patterning processes of the coating process 14, the exposure process 16, and the processing process 18 are performed all at once not only in the micro region 24 but also in other regions within the silicon wafer 22, thereby patterning a desired circuit. was doing.

[Problem to be solved by the invention] However, in the conventional method, processing process 1
When performing ion etching using a resist as a mask in No. 8, several problems occurred. That is, when reactive ion etching is performed in a gas such as CCl4 using a resist as a mask, a polymer containing C5CJl is generated from the resist and adheres to the side walls of the etching pattern.

This polymer acts as a mask for ion etching, so it can be etched, for example, in the gate region 3 as shown in FIG.
4 and the wiring regions 36 and 38 are parallel to each other, a larger amount of polymer from the resist on the gate region 34 adheres to the sidewalls of the wiring region 36 than to the sidewalls of the wiring region 38, and as a result, as shown in FIG. As shown in FIG.
However, there is a problem that large variations occur in the line width, making it impossible to form accurate circuits.

The present invention has been made in view of the above-mentioned conventional problems, and its purpose is to improve the conventional patterning process, reduce variations in circuit wiring width, and provide an integrated circuit manufacturing method that can form circuits with high precision. Our goal is to provide the following.

[Means for Solving the Problems] In order to achieve the above object, the present invention includes a coating process 14 for coating a photoresist on a polycrystalline silicon film and a silicon wafer in a patterning process, as shown in FIG. a selective exposure process 42 of dividing the polycrystalline silicon film into a plurality of regions using virtual lattice stripes, extracting regions in an alternating relationship among the plurality of regions, and exposing only the photoresist on the extracted regions; a processing process 18 for ion etching the patterning process, and repeating the patterning process by changing the area to be exposed in the exposure process.
It is a feature.

[Operation] That is, the inside of the silicon wafer is not patterned all at once as in the conventional method, but is divided into several areas, and some of them are patterned almost uniformly within the wafer with a certain relationship. When the silicon wafer is processed by reactive ion etching by extracting the area and selectively exposing it to light, unexposed resist remains in the area not selected in the selective exposure process. A larger amount of polymer is generated than in the batch exposure method. Then, even when a dense pattern as shown in FIG. 9 exists in the selected area, approximately the same amount of polymer from the unexposed resist is attached to the side walls of the wiring areas 36 and 38, and the wiring after processing is It is possible to eliminate variations in width.

Thereafter, photoresist is applied again in the coating process 18, an unselected area is newly selected, and the patterning process described above is repeated, thereby making it possible to similarly eliminate variations in wiring width in the selected areas.

It should be noted that when the patterning process is repeated, the area that has already been processed is masked by the reapplied photoresist, so there is no fear that it will be etched again.

By repeating the above patterning process until there are no more areas to select, it is possible to eliminate variations in wiring width over the entire silicon wafer.

Embodiments] Preferred embodiments of the integrated circuit manufacturing method according to the present invention will be described below with reference to the drawings.

FIG. 2 shows that a SiO2 oxide film, a polycrystalline silicon film, and a positive resist film are sequentially formed on a silicon wafer 122 in the same manner as in the conventional method. In this example, the silicon wafer/X22 is It is divided into a large number of minute regions using virtual lattice stripes shown by dashed dotted lines. Then, out of the regions, a group of regions 44 having an alternating relationship indicated by X marks in the figure are extracted, and a cross section of the minus region of the extracted regions is shown in FIG. FIGS. 3a, 3b, and 3c show how desired patterning is formed in the patterning process of this embodiment, and the selective exposure process 42
The positive resist film 32 is irradiated with ultraviolet rays for a certain period of time through a photomask, and the exposed portions are dissolved in a basic aqueous solution (FIG. 3b).

Then, in a processing process 18, reactive ion etching (RIE) is performed in a gas containing fluorine or chlorine using the resist remaining on the polycrystalline silicon film 30 in the exposure process 16 as a mask, to remove the polycrystalline silicon film 30. Process (Figure 3C).

At this time, the resist is not removed from the unextracted area of the silicon wafer 22, that is, the unmarked area in the figure, since it is not exposed to light, and the configuration shown in FIG. 3a is maintained. Therefore, during the processing shown in FIG. 3C, a large amount of polymer is generated from the unexposed resist in the unmarked area, and
Since a large amount of etching adheres to the sidewalls of the etching, even when there is a dense pattern as shown in FIG. 9, the wiring width becomes the same as that of the wiring area 50 and 51 after processing as shown in FIG. 4, making it difficult to eliminate variations. can.

Thereafter, the coating process is started again, this time the unmarked area in FIG. 2 is extracted and selectively exposed, and the same process as in FIG. 3 is performed to form a desired pattern. At this time, the second
As shown in FIG. 5, the etched area of the processing area indicated by the X mark in the figure is protected by a coating resist 32, and a large amount of polymer adheres from this resist to the side wall of the etching pattern in the unmarked area in the figure. Therefore, as described above, it is possible to eliminate variations in wiring width and also to prevent re-etching of the processed area.

In this way, the present invention divides the exposed area of the silicon wafer 1 into several parts and repeats the patterning process until all areas are processed, thereby generating a large amount of polymer from the resist during the processing process. This makes it possible to eliminate the variations in wiring width that conventionally occur and to form circuits with high precision.

Note that in this example, patterning is used.

Although patterning was performed by repeating the steps twice, it is also possible to complete the patterning by repeating the steps two or more times, if necessary.

[Effects of the Invention] As explained above, according to the method for manufacturing an integrated circuit according to the present invention, it is possible to eliminate variations in wiring width and form a circuit with high precision.

[Brief explanation of the drawing]

FIG. 1 is a flowchart of the integrated circuit manufacturing method according to the present invention, FIG. 2 is an explanatory diagram of dividing a silicon wafer, FIG. 3 is a process explanatory diagram of the integrated circuit manufacturing method according to the present invention, and FIGS. 4 and 5 Figure 6 is a flowchart of the conventional integrated circuit manufacturing method, Figure 7 is a silicon wafer configuration diagram, and Figure 8 is the process of the conventional integrated circuit manufacturing method. The explanatory drawings, FIGS. 9 and 10 are explanatory drawings showing processing by a conventional integrated circuit manufacturing method. 10...Oxide film formation process 12...Polycrystalline silicon film deposition process 14.
... Coating process 18 ... Machining process 42 ... Selective exposure process

Claims (1)

[Scope of Claim] An integrated circuit manufacturing method in which an oxide film and a polycrystalline silicon film are sequentially formed on a semiconductor substrate and an integrated circuit is formed on the semiconductor substrate through a patterning process, wherein the patterning process comprises: a coating process of coating a photoresist on a film; dividing the semiconductor substrate into a plurality of regions with virtual checkered stripes;
a selective exposure process of exposing only the resist on alternating regions among the plurality of regions; and a processing process of ion etching the polycrystalline silicon film, the regions to be exposed in the exposure process. A method for manufacturing an integrated circuit, characterized in that a circuit can be formed with high precision by repeating the patterning process while changing the patterning process.