JPH02226458A - Pipe line processing system for parallel processing computer - Google Patents

Abstract

PURPOSE:To attain a high speed processing and to efficiently deal with a frequent interrupting processing from the other processor by alternately receiving plural processes for a pipe line processing. CONSTITUTION:Respective instructions are set in instruction buffers 2-1 and 2-2 from two processes. An instruction switch circuit 3 alternately receives the instructions of two processes. A result decoded in a stage by a decoding circuit 4 is set in a pipe line register 5. At that time, it is indicated by a process flag 5-1 that to which process in two processes the instruction decoded by the stage belongs. Check means 11 and 12 decide to which stage the instruction affected by the occurrence of the situation is positioned when the situation that the flow of the pipe line processing is not in a normal state has occurred. Thus, efficient correspondence to the frequent interrupting processing from the other processor is attained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] This invention relates to an lff single-column processing computer pipeline processing method in which processing inside each processor in a parallel processing computer is executed by pipeline processing.

The purpose is to speed up 'ζ through pipeline processing and to be able to effectively handle frequent interrupt processing from other processors.

An instruction switch circuit is provided on the input side of a pipeline process that is divided into n stages to alternately accept a plurality of different processes, and process flags are provided corresponding to the stages. For example, it has a configuration that reduces the number of stage processing results that are undesirably canceled when executing a branch instruction.

[Industrial application field]

The present invention relates to a parallel processing computer pipeline processing method for executing processing inside each processor in a parallel processing computer by pipeline processing.

Conventionally, parallel processing computers have been realized to speed up relatively monotonous operations such as numerical calculations. However, in recent years, data-dependent processing methods such as those in the field of artificial intelligence have been developed, and the use of the above-mentioned parallel processing computers is being considered. In this case, if you try to introduce pipelining.

Due to asynchronous interrupts from other processors, the flow of the pipeline is disrupted and efficiency cannot be improved.

[Conventional technology]

Pipeline processing has been widely used as a method to speed up processing, but it can be used when two-branch processing is required or when restrictions arise from register usage.
The normal flow of the pipeline is disrupted.

FIG. 5 shows an aspect of branch processing, and FIG. 6 shows an aspect when the assignment order is restricted.

In FIG. 5, the case of pipeline processing consisting of n=4 stages is shown, and it is assumed that the instruction lot shown in the first diagram is a branch instruction and it is found at time T that a branch has occurred. It is shown. In this case, the number shown in the figure is []<, command 102, command 103. Instruction 104 is canceled, and the processing performed before time T0 with respect to each of these instructions is wasted. Note that instruction 105 is a branch destination instruction.

FIG. 6 shows a state in which an interlock occurs, and shows a case where the instruction 107 in the first diagram is forced to wait because it is supposed to use the value calculated in the fourth phase of the instruction 106. ing.

[Problem to be solved by the invention]

As shown in Figure 5, when the pipeline has n stages, generally 2
When a branch occurs, the execution of the (n-1) stage instructions that have already entered the pipeline and started execution is immediately interrupted, jumps to the one branch destination instruction, and execution starts from there. The n-1 stage instructions that are wasted at that time cause a reduction in the efficiency of the pipeline. Further, as shown in FIG. 6, this is an example in which the first phase uses the value calculated in the previous fourth phase, so that the calculation is waited until the end of the calculation. In this case as well, the flow of the pipeline becomes clogged, causing a drop in efficiency.

As described above, pipeline processing is very efficient when the instructions in the pipeline are independent, but the processing efficiency decreases when the flow of the pipeline is disturbed, such as by a one-branch instruction or an interlock.

This is the reason why pipeline processing cannot theoretically increase efficiency for applications such as artificial intelligence that often involve single-condition judgments and branch processing.

On the other hand, when combined with parallel processing technology that has become popular in recent years, it is necessary to frequently execute interrupt processing due to asynchronous interrupts from other processors. This also disturbs the flow of the pipeline, similar to two-branching, and is the reason why efficiency is not improved.

SUMMARY OF THE INVENTION The present invention aims to speed up processing through pipeline processing and to efficiently deal with frequent shaving processing from five other processors.

[Means to solve the problem]

FIG. 1 shows a basic configuration diagram of the present invention. Reference numeral 1 in the figure represents an instruction bus, and 2-1, 2-2 represent instruction buffers in which instructions corresponding to different processes are set. Reference numeral 3 denotes an instruction switch circuit, which is provided on the input side of the pipeline processing 50 and successively receives instructions from different processes. 4 is a decoding circuit, 6 is a memory address circuit, 8 is a cache read circuit 10
5 are execution circuits, each corresponding to a stage process of the pipeline process 50. 5゜7.9 are pipeline registers that partition between stages, 5-1 7-
1.9-1 represents a process flag that is set corresponding to the people stage. Process flag 5-1.7
-1.91 indicates which process the corresponding stage has performed processing for. 11 is a first checking means for checking the identity of processes; 12
represents a second checking means for checking duplicate use of registers.

[Effect]

In the case shown in FIG. 1, instructions from two processes are set in instruction buffers 2-1 and 2-2. The instruction switch circuit 3 alternately accepts instructions of two processes. 1. For example, the result decoded at the stage by the illustrated decoding circuit 4 is set in the pipeline register 5, and at this time, it is determined to which of the two processes the instruction decoded at the stage belongs. This is indicated by the process flag 51.

When a situation occurs in which the flow of pipeline processing is not in a normal state, check means 11 and 12 determine in which stage those affected by the occurrence of the situation are located.

〔Example〕

Before explaining the embodiments, the advantages of the present invention will be explained.

FIG. 7 shows an aspect of branch processing in the case of the present invention,
FIG. 8 shows the case a when the assignment order is restricted in the case of the present invention.

FIG. 7 corresponds to the case shown in FIG. 5, but shows a case where the instruction 101 of the first process Pi branches at time T0. In this case.

The instructions input into the pipeline process consisting of four stages are instruction 101 and instruction 102 belonging to the first process, and instruction 10 belonging to the O-th process PO.
1' and instruction 102'. Therefore, the only instruction that is wasted due to the occurrence of one branch processing is instruction 102, which is more efficient than the conventional case shown in FIG.

Further, FIG. 8 corresponds to the case shown in FIG. 6, but an instruction 106' belonging to the first O-th process exists between the instruction 106 and the instruction 107 belonging to the first process. As a result, the waste caused by the interlock between instructions +06 and +07 is reduced to one, improving efficiency.

FIG. 2 shows the configuration of an embodiment of the present invention, FIG. 3 is a diagram for explaining countermeasures during branch processing, and FIG. 4 shows the configuration of the main part of the embodiment.

Reference numeral 1 shown in FIG. 2, 2.5.5-1.7.7=1.
9. 9-1 correspond to FIG. 1, respectively.

4', 6', 8', and lO' are respectively 4. shown in FIG. 6. 8゜Equivalent to IO, 13 is a pipeline register, 14 is a process flag, 15 is a program counter corresponding to the first process, 16 is a program counter corresponding to the Oth process, and 17 is a part for executing instructions. The figure shows the register converter used in the figure. Note that the instruction switch circuit 3 shown in FIG. 1 is omitted in FIG. 2 to show that the contents of the program counters 15 and 16 are used alternately and incorporated into pipeline processing.

In the case shown in Figure 2, the pipeline processing is +11
Decode and read address register 2)
Memory address calculation and address output (3) Cache tag pull and operation register reading 4) The case of four phases of instruction execution is taken. Additionally, the instruction buffer before decoding is used for instruction fetch cycles (read ahead).

In the case shown in FIG. 2, the instructions belonging to the first process are in instruction execution 10', address calculation and output 6', and the instructions belonging to the 0th process are in cache read and register read 8'. It is located at decode and address register read 4'.

Then, an instruction belonging to the first process is set in the pipeline register 13 in a secondary manner.

Note that when calculating the memory address, the contents of the program counter 1516 corresponding to each process are used.

In the case shown in FIG. 2, as will be described later with reference to FIG. 4(B), registers R3 and R2 are used when the instruction belonging to the first process is executed in instruction execution 10'. R1 and register R11 are used. Also, register R and register R2 are used when the instruction belonging to the 0th process is executed.
I and register R. It is made to use O. In order to do this, when an instruction belonging to the first process is processed in the instruction execution 10', the register converter 1 shown in FIG.
By 7.

Copy R, 1 to R eye occurs for instructions belonging to the second-order 0th process. copyRo+toRot is caused to occur.

Therefore, even if instructions belonging to two processes correspond to the same instruction, different registers will be used, and there will be no undesirable influence on each other.

Further, in the case of the configuration shown in FIG. 2, since instructions of the same process are not located in consecutive stages of pipeline processing, the probability of occurrence of interlock is reduced.

The symbols in FIG. 3 correspond to those in FIG.

In the illustrated case, the instruction executed in instruction execution 10' belongs to the first process and a branch occurs. Corresponding to the fact that the branch has taken place, it is found that an instruction belonging to the first process exists at address calculation and output 6'.

Canceled. Then, one branch destination address is given to the first process side. Therefore, waste in pipeline processing is reduced.

FIG. 4 shows the main part configuration of the embodiment. 41D(A) is the 1st
The illustrated pipeline register 5 and process flag 5-
For example, 1 bit for identifying the process is sent to the process flag 5-1.

FIG. 4(B) shows a portion corresponding to the register conversion section 17 shown in FIG. For example, the register R shown in FIG.
The register number +7-1 indicating 2 and the process flag 17-2 at that time are merged by the register number converter 17-3 to obtain the register number 17-4 that is actually used.

FIG. 4(C) shows a configuration example of a process for canceling an instruction. In the illustrated case, the comparator 24 compares the process flag 21 of the instruction in the 7-instruction execution phase 10' with the process flag 22 of the instruction being executed in each stage.

Then, when a cancel signal 23 is supplied from the first checking means 11 shown in FIG. 1, etc., and the output of the comparator 24 outputs a match, the instruction located at the relevant stage is canceled. In this case, the cancel bit 26 in the pipeline register 25 (corresponding to the pipeline register 7 shown in FIG. 3) is set to logic "1".
” is set to indicate that the processing result should be canceled and should not be executed in the instruction execution phase.

In the case of the configuration of the present invention described above, in the parallel processing computer, it appears that p processors with a speed of months/p are running. If two processes have many common cache blocks in cache memory,
Cache miss hints are reduced and speed is actually increased.
Efficiency is improved compared to the case where nine /p processors are prepared.

Therefore, it brings about a significant improvement in cost performance for applications that assume parallel processing.

Furthermore, the requirements that require the most 11 feet in parallel processing include δ and synchronization. If two processes perform the same process, there are the following advantages.

5 when controlling to prevent conflicts between multiple caches, such as in a parallel cache system.
Since there is a transfer between caches operating in parallel, the cache hint rate decreases. However, in the case of the present invention, since the cache is shared because the execution is performed using the same processor, the cache hint rate does not decrease even if the data communication method on the memory is used.

However, this does not exclude communication within the PL1 sensor using a shared register.

〔Effect of the invention〕

As explained above, 1. According to the present invention, 2. For applications such as artificial intelligence, where there is often a close relationship between processes, by bringing parallelism into the pipeline, the pipework, such as at the time of 9 branches, can be improved. It becomes possible to reduce waste in the line. Also.

It is expected that the hint rate will improve for applications where one communication is a living body due to the sharing of the cache system.

Furthermore, since interlocks are less likely to occur, wiring such as bypass is minimized.

[Brief explanation of the drawing]

Figure 1 is a diagram showing the principle configuration of the present invention, Figure 2 is the configuration of an embodiment of the invention, Figure 3 is a diagram explaining countermeasures during branch processing, Figure 4 is the configuration of the main parts of the embodiment, and Figure 5. Figure 6 shows the conventional case of branch processing in a form, and Fig. 6 shows the conventional case in which assignment order is constrained.
FIG. 7 shows a mode of branch processing in the case of the present invention, and a 'fIB figure shows a mode when the assignment order is restricted in the case of the present invention. In the figure, 2 is an instruction buffer, 3 is an instruction switch circuit, and 50
5-1.7-1, 9-1.27 are process flags, and 11.12 are check means.

Claims (1)

[Claims] A plurality of mutually different processes are stored in a process pool, a plurality of processors receive the processes held in the process pool, and each processor receives the processes through pipeline processing. In the parallel processing computer that executes the above pipeline processing (50), n
The instruction switch circuit (50) is configured to be divided into stages, and is configured to alternately accept a plurality of different processes on the input side of the pipeline processing (50).
3) and process flags (5-1, 7 -1, 9-1), and the process flag (5
-1, 7-1, 9-1)
11 or 12), and a plurality of processes are accepted in turn for the pipeline processing.