JPH0222572A - Wiring inspecting method for integrated circuit - Google Patents

Abstract

PURPOSE:To easily and securely detect a wire breaking point by forming a liquid crystal film on the top surface of an IC chip so that its wiring layer is covered, applying an impulsive voltage to the wiring layer, and observing a repetitive light and dark pattern where the inclination of molecule axes of a liquid crystal material due to electric field effect is reflected. CONSTITUTION:In a 1st step, the liquid crystal film 20 is formed on the top surface of the IC ship 10 while covering the wiring layer 16. In this case, no cover glass is installed and orientation is not performed. Further, a wiring protection film 18 is not removed either. In a 2nd step, the impulsive voltage signal is applied to the wiring layer 16 to form the optically observable repetitive light and dark pattern where the inclination of molecule axes of the liquid crystal material due to the electric field effect is reflected in the liquid crystal film 20 along the wiring layer 16. In a 3rd step, the generation state of the repetitive light and dark pattern is observed optically to detect the wire breaking position of the wiring layer 16.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a wiring inspection method for integrated circuits (hereinafter referred to as IC), and particularly relates to an improvement in a method for detecting disconnections.

[Summary of the Invention] This invention forms a liquid crystal film on the upper surface of an IC chip so as to cover its wiring layer, applies a pulse-like voltage signal to the wiring layer, and tilts the molecular axis of the liquid crystal material by an electric field effect. By observing the shading pattern reflecting the shading with an optical microscope, etc., it is possible to easily and reliably detect the disconnection point.

[Prior Art] Several methods have been proposed to analyze failures in ICs such as LSIs (Large-Scale Integrated Circuits), such as using a strobe scanning electron microscope. Because of its simplicity, a method that uses the birefringence effect of liquid crystal to visualize the wiring potential state (specifically, optically observing parts of the wiring layer that are in a high potential state) is attracting attention.

In this visualization method, a cover glass is provided on the top surface of the IC chip with the liquid crystal interposed therebetween, and the liquid crystal is vertically aligned by alignment treatment. Then, a pulse voltage is applied to the wiring layer to cause birefringence in the liquid crystal due to the electric field effect, but the applied voltage at this time must be higher than the voltage normally used by the IC, or the protective film covering the wiring layer must be made thinner in advance. Unless it is etched as much as possible, the molecular axis of the liquid crystal material cannot be tilted.
I couldn't visualize it. Therefore, as a method that does not require protective film etching and can be visualized at a voltage lower than the normal operating voltage of IC, a
It has been proposed to apply two pulse voltages in a superimposed manner (see, for example, the 15th Japan Society of Science and Technology Reliability and Maintainability Symposium Materials, May 1985, pp. 243-246).

[Problems to be Solved by the Invention] According to the above-mentioned conventional technology, even if voltage reduction is achieved without protective film etching by applying pulsed voltage in a superimposed manner, cover glass installation processing and orientation processing are indispensable. The orientation treatment requires heat treatment for about one hour. For this reason, a considerable amount of time and effort is required to prepare analysis samples, making it difficult to perform failure analysis simply and quickly.

An object of the present invention is to provide a new IC wiring inspection method that can perform failure analysis simply and quickly, and can safely and reliably detect disconnections.

[Means for Solving the Problems] The IC wiring inspection method according to the present invention includes the following first to third steps.

That is, in the first step, a liquid crystal film is formed on the upper surface of the IC chip so as to cover the wiring layer. in this case,
No cover glass is installed, no orientation treatment is performed, and no wiring protection film is removed.

In the second step, by applying a pulsed voltage signal to the wiring layer, an optically observable repeating pattern of light and shade that reflects the inclination of the molecular axis of the liquid crystal material due to the electric field effect is created in the liquid crystal film along the wiring layer. cause to occur.

In the third step, a disconnection point in the wiring layer is detected by optically observing the generated state of the repetitive pattern of shading.

[Function] According to the method of the present invention, the repeating pattern of shading is generated by the electric field effect, so that the repeating pattern of shading does not occur in the portions of the wiring layer where no voltage is applied due to a disconnection. Therefore, by optically observing the generation state of the repeating pattern of shading using an optical microscope or the like, it is possible to reliably detect a break in the repeating pattern of shading, such as in the middle of a wiring layer, as a disconnection point.

In addition, this invention does not optically observe the wiring layer itself under voltage application, but optically observes the repetitive pattern of shading that occurs with voltage application. It may be in any orientation state, and cover glass installation treatment and orientation treatment are not required. Furthermore, the repeating pattern of light and shade occurs even when the wiring protection film is attached and the voltage is lower than the IC's normal usage voltage (for example, 5 [V]), so there is no need for a protection film etching process, and it is difficult to use when high voltages are used. There is no risk of damaging the IC function.

[Embodiment] FIG. 1 shows an embodiment of the IC wiring inspection method of the present invention.

The cases in which IC failure analysis is performed can be broadly classified.

There is a first case in which the process is carried out in a wafer state, for example, before the IC chip is assembled into a package, and a second case in which the process is carried out after the IC chip is assembled in the package.

In the first case, the IC chip is exposed, so there is no need for chip exposure treatment, but in the second case, the package is chemically or mechanically opened and the IC chip is exposed. Expose the chip. At this time, be careful not to damage the bonding wire.

As shown in FIG. 1, the IC chip 10 has a plurality of circuit elements formed on the surface of a semiconductor substrate such as silicon, and
These circuit elements are connected to a wiring layer 1 formed on an insulating film 14.
6 to obtain the desired circuit function.
Usually, the wiring layer 18 is covered with a protective film such as PSG (phosphosilicate glass), and one end and the other end of the wiring layer 16 are covered with connection layers C1 and C2 as bonding pads.
is led out to the upper surface of the protective film 18.

After preparing the IC chip IO to be analyzed, this chip is made electrically operable. Specifically, in the above-mentioned first flat stand, metal probes are set up on the connection layers C1 and C2 so that a voltage signal can be applied from the outside, and in the above-mentioned second case, the external terminals of the package (leads) so that a voltage signal can be applied to them. Terminals TI and T2 in FIG. 1 correspond to probes or leads.

Next, as an example, a nematic liquid crystal MBB is placed on the top surface of the chip.
After coating A, excess liquid crystal is removed to form an extremely thin (approximately 3 mm or less) liquid crystal film 20 on the chip. Then, the IC chip 10 is placed under the optical microscope 30 with the surface on which the liquid crystal film 20 is formed facing upward.

In the optical microscope 30, a half mirror 38 is provided between the objective lens 32 and the eyepiece lens 34 so as to direct the light from the light source 36 toward the object to be observed.

Between the light source 36 and the half mirror 38 and the eyepiece 34
First and second polarizers 40 and 42 are disposed between the half mirror 38 and the half mirror 38 so that their polarization planes are perpendicular to each other.
are placed respectively.

Next, terminal T! And T2 has a peak voltage of +5 as an example.
[V], a square wave pulsed voltage signal Va with a frequency of 5 [Hzl] is applied. Then, in this voltage applied state, the top surface of the IC chip is observed with the naked eye through the optical microscope 30.

Now, assuming that the wiring layer 16 is broken at the point X, in the part (A) to the left of X, the light P from the microscope 30 enters the top surface of the chip with the plane of polarization in the direction of arrow a.
The microscope 30 holds the polarization plane of the reflected light Q in the direction of the arrow.
incident on . At this time, since no voltage is applied to the portion of the wiring layer 16 to the left of X due to the disconnection, no optical change is observed as shown in ^ in FIG.

On the other hand, in the part (B) on the right side of X, the molecular axis of the liquid crystal substance is tilted due to the change in the electric field around the wiring, so the direction of the polarization plane of the reflected light Q changes from b to b'. As shown in FIG. 2KB, a repeated pattern of light and shade can be seen along the wiring layer portion on the right side from X.

Since the presence or absence of the pattern at KB and ^ in FIG. 2 can be clearly observed through the microscope 30, it is easy to detect that the wiring layer 16 is broken at the location X. Note that if the wiring layer 18 is normal with no disconnections, a repeating pattern of light and shade as shown in FIG. 3 will be seen.

In the above embodiment, the observation was made with the naked eye through the microscope 30, but it may also be observed by taking a photograph.The voltage value and frequency of the voltage signal Va should be set within a range in which a repeating pattern of light and shade appears optically observable. It may be set as appropriate and is not limited to the above-mentioned example values.

[Effects of the Invention] As described above, according to the present invention, the repeating pattern of shading that occurs with the application of voltage is optically observed, so that it is possible to perform the wiring protection film etching process, cover glass installation process, and alignment process. It has excellent effects, such as eliminating the need for troublesome preparation processes such as That's what you get.

[Brief explanation of the drawing]

FIG. 1 is a layout diagram for explaining one embodiment of the IC wiring inspection method of the present invention, and FIGS. 2 and 3 show repeated patterns of shading for a wiring layer with a disconnection and a normal wiring layer, respectively. FIG. lO...IC chip, 12...semiconductor substrate, 14.
...Insulating film, IB...Wiring layer, 1B...Protective film, 2
0...Liquid crystal film, 30...Optical microscope.

Claims (1)

[Claims] (a) forming a liquid crystal film on the upper surface of an integrated circuit chip so as to cover the wiring layer; and (b) applying a pulsed voltage signal to the wiring layer to generate a liquid crystal film by applying an electric field effect. (c) producing an optically observable repeating pattern of light and shade in the liquid crystal film along the wiring layer, reflecting the inclination of the molecular axis of the liquid crystal substance; Detecting a disconnection point in the wiring layer by observing the wiring of the integrated circuit.