JPH0581866B2 - - Google Patents
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- Publication number
- JPH0581866B2 JPH0581866B2 JP63172038A JP17203888A JPH0581866B2 JP H0581866 B2 JPH0581866 B2 JP H0581866B2 JP 63172038 A JP63172038 A JP 63172038A JP 17203888 A JP17203888 A JP 17203888A JP H0581866 B2 JPH0581866 B2 JP H0581866B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring layer
- liquid crystal
- voltage
- chip
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004973 liquid crystal related substance Substances 0.000 claims description 19
- 238000000034 method Methods 0.000 claims description 16
- 230000005685 electric field effect Effects 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 4
- 230000003287 optical effect Effects 0.000 description 7
- 230000001681 protective effect Effects 0.000 description 7
- 238000004458 analytical method Methods 0.000 description 6
- 230000003252 repetitive effect Effects 0.000 description 6
- 238000007689 inspection Methods 0.000 description 5
- 239000006059 cover glass Substances 0.000 description 4
- 239000005360 phosphosilicate glass Substances 0.000 description 4
- 230000010287 polarization Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 239000000523 sample Substances 0.000 description 3
- 238000009434 installation Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 239000004988 Nematic liquid crystal Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- FEIWNULTQYHCDN-UHFFFAOYSA-N mbba Chemical compound C1=CC(CCCC)=CC=C1N=CC1=CC=C(OC)C=C1 FEIWNULTQYHCDN-UHFFFAOYSA-N 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000007794 visualization technique Methods 0.000 description 1
Description
【発明の詳細な説明】
［産業上の利用分野］
この発明は、集積回路（以下ICと称する）の
配線検査法に関し、特に断線個所検出法の改良に
関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a wiring inspection method for integrated circuits (hereinafter referred to as IC), and particularly relates to an improvement in a method for detecting a disconnection point.
［発明の概要］
この発明は、ICチツプの上面にその配線層を
おおうように液晶膜を形成すると共に該配線層に
パルス状の電圧信号を印加し、電界効果による液
晶物質の分子軸の傾きを反映した濃淡の繰返しパ
ターンを光学顕微鏡等で観察することにより断線
個所を簡単且つ確実に検出可能としたものであ
る。[Summary of the Invention] This invention forms a liquid crystal film on the upper surface of an IC chip so as to cover the wiring layer, applies a pulsed voltage signal to the wiring layer, and tilts the molecular axis of the liquid crystal material by an electric field effect. By observing the repeating pattern of light and shade reflecting the shading with an optical microscope etc., it is possible to easily and reliably detect the location of the disconnection.
［従来の技術］
従来、LSI（大規模集積回路）等のICの故障を
解析する方法としては、ストロボ走査型電子顕微
鏡を用いるものなどがいくつか提案されている
が、高価な装置を用いないで済む簡便さから液晶
の複屈折効果を利用して配線電位状態を可視化す
る（具体的には配線層のうち高電位状態にある個
所を光学的に観察する）方法が注目されている。[Conventional technology] Several methods have been proposed to analyze failures in ICs such as LSIs (Large-Scale Integrated Circuits), such as using a strobe scanning electron microscope, but this method does not use expensive equipment. A method of visualizing the wiring potential state by utilizing the birefringence effect of liquid crystals (specifically, optically observing parts of the wiring layer that are in a high potential state) is attracting attention because of its simplicity.
この可視化する方法にあつては、ICチツプの
上面に液晶を介してカバーガラスを設け、配向処
理により液晶を垂直配向させる。そして、配線層
にパルス電圧を印加してその電界効果により液晶
に複屈折を起こさせるが、このときの印加電圧を
ICの通常使用電圧より高くするか又は配線層を
おおう保護膜を予め薄くすべくエツチしておかな
ければ液晶物質の分子軸を傾けることができず、
可視化できなかつた。そこで、保護膜エツチング
を要せず、しかもICの通常使用電圧以下の電圧
で可視化する方法として、約10［Hz］と約１［Ｋ
Hz］との２つのパルス電圧を重畳して印加するこ
とが提案されている（例えば第15回日科技連信頼
性・保全性シンポジウム資料、昭和60年５月、第
243〜246頁参照）。 In this visualization method, a cover glass is provided on the top surface of the IC chip with the liquid crystal interposed therebetween, and the liquid crystal is vertically aligned by alignment treatment. Then, a pulse voltage is applied to the wiring layer to cause birefringence in the liquid crystal due to the electric field effect.
The molecular axis of the liquid crystal material cannot be tilted unless the voltage is set higher than the voltage normally used by the IC or the protective film covering the wiring layer is etched to make it thinner.
I couldn't visualize it. Therefore, as a method that does not require protective film etching and can be visualized at a voltage lower than the normal operating voltage of the IC, a
It has been proposed to apply two pulse voltages in a superimposed manner (e.g., 15th Japan Society of Science and Technology Reliability and Maintainability Symposium Materials, May 1985, Vol.
(See pages 243-246).
［発明が解決しようとする課題］
上記した従来技術によると、パルス電圧の重畳
的印加により保護膜エツチングなしで低電圧化を
達成したとしても、カバーガラス設置処理及び配
向処理は不可欠であり、特に配向処理は１時間程
度の加熱処理を要する。このため、解析試料の作
製に相当の時間と労力が必要であつて、簡単且つ
迅速に故障解析を行なうのが困難であつた。[Problems to be Solved by the Invention] According to the above-mentioned conventional technology, even if voltage reduction is achieved without protective film etching by applying pulsed voltage in a superimposed manner, cover glass installation processing and orientation processing are indispensable. The orientation treatment requires heat treatment for about one hour. For this reason, a considerable amount of time and effort is required to prepare analysis samples, making it difficult to perform failure analysis simply and quickly.
この発明の目的は、簡単且つ迅速に故障解析を
行なえると共に安全且つ確実に断線個所を検出す
ることのできる新規なIC配線検査法を提供する
ことにある。 An object of the present invention is to provide a new IC wiring inspection method that can perform failure analysis simply and quickly, and can safely and reliably detect disconnections.
［課題を解決するための手段］
この発明によるIC配線検査法は、次の第１〜
第３のステツプを含むものである。[Means for Solving the Problems] The IC wiring inspection method according to the present invention includes the following first to
This includes a third step.
すなわち、第１のステツプでは、ICチツプの
上面にその配線層をおおうように液晶膜を形成す
る。この場合、カバーガラスは設置せず、配向処
理も行なわない。また、配線保護膜も除去しな
い。 That is, in the first step, a liquid crystal film is formed on the upper surface of the IC chip so as to cover the wiring layer. In this case, no cover glass is installed and no orientation treatment is performed. Further, the wiring protection film is not removed either.
第２のステツプでは、配線層にパルス状の電圧
信号を印加することより電界効果による液晶物質
の分子軸の傾きを反映した光学的に観察可能な濃
淡の繰返しパターンを配線層に沿つて液晶膜に生
じさせる。 In the second step, by applying a pulsed voltage signal to the wiring layer, an optically observable repeating pattern of light and shade reflecting the inclination of the molecular axis of the liquid crystal substance due to the electric field effect is created in the liquid crystal film along the wiring layer. cause to occur.
第３のステツプでは、濃淡の繰返しパターンの
生成状態を光学的に観察することにより配線層の
断線個所を検出する。 In the third step, a disconnection point in the wiring layer is detected by optically observing the formation of a repetitive pattern of shading.
［作用］
この発明の方法によると、濃淡の繰返しパター
ンは、電界効果によつて生ずるものであるから、
配線層のうちでも断線によつて電圧が印加されな
い部分については濃淡と繰返しパターンが生じな
い。従つて、濃淡の繰返しパターンの生成状態を
光学顕微鏡等を用いて光学的に観察することによ
り配線層の途中等において濃淡の繰返しパターン
が途切れているところは断線個所として確実に検
出することができる。[Function] According to the method of the present invention, the repetitive pattern of light and shade is produced by the electric field effect.
Even in the wiring layer, the shading and repetitive patterns do not occur in portions to which no voltage is applied due to disconnection. Therefore, by optically observing the generation state of the repeating pattern of shading using an optical microscope or the like, it is possible to reliably detect a place where the repeating pattern of shading is interrupted in the middle of a wiring layer as a disconnection point. .
また、この発明は、電圧印加状態にある配線層
そのものを光学的に観察するのではなく、電圧印
加に伴つて生ずる濃淡の繰返しパターンを光学的
に観察するようにしたので、液晶膜が初期的にど
のような配向状態にあつてもよく、カバーガラス
設置処理及び配向処理は不要である。その上、濃
淡の繰返しパターンは、配線保護膜を付けたまま
でICの通常使用電圧（例えば５［Ｖ］）以下でも
生ずるので、保護膜エツチング処理が不要であ
り、しかも高電圧を用いた場合のようにIC機能
を損うおそれもない。 In addition, this invention does not optically observe the wiring layer itself under voltage application, but optically observes the repetitive pattern of shading that occurs as voltage is applied, so that the liquid crystal film is It may be in any orientation state, and cover glass installation processing and orientation processing are unnecessary. In addition, the repetitive pattern of shading occurs even when the wiring protection film is attached and the voltage is lower than the IC's normal operating voltage (for example, 5 [V]), so there is no need for a protection film etching process, and moreover, when high voltage is used, As such, there is no risk of damaging IC functionality.
［実施例］
第１図は、この発明のIC配線検査法の一実施
例を示すものである。[Embodiment] FIG. 1 shows an embodiment of the IC wiring inspection method of the present invention.
ICの故障解析を行なう場合を大別すると、IC
チツプをパツケージに組込む前に例えばウエハ状
態で行なう第１の場合と、ICチツプをパツケー
ジに組込んだ後行なう第２の場合とがある。 When performing IC failure analysis, there are two main types of IC failure analysis:
There is a first case where the process is carried out in a wafer state, for example, before the chip is assembled into the package, and a second case where the process is carried out after the IC chip is assembled into the package.
第１の場合にあつては、ICチツプが露出して
いるので、チツプ露出処理は必要ないが、第２の
場合にあつては、パツケージを薬品（化学的）あ
るいは機械的に開封してICチツプを露出させる。
このとき、ボンデイングワイヤにダメージを与え
ない様に注意する。 In the first case, the IC chip is exposed, so there is no need for chip exposure treatment, but in the second case, the package is chemically or mechanically opened and the IC chip is exposed. Expose the tip.
At this time, be careful not to damage the bonding wire.
第１図に示すように、ICチツプ１０は、シリ
コン等の半導体基板の表面に複数の回路素子を形
成すると共に、これらの回路素子を絶縁膜１４上
に形成された配線層１６で接続して所望の回路機
能を得るようになつている。通常、配線層１６
は、PSG（リンケイ酸ガラス）等の保護膜１８で
おおわれており、配線層１６の一端及び他端は、
ボンデイングパツドとしての接続層C1及びC2に
より保護膜１８の上面に導出されている。 As shown in FIG. 1, the IC chip 10 has a plurality of circuit elements formed on the surface of a semiconductor substrate such as silicon, and these circuit elements are connected by a wiring layer 16 formed on an insulating film 14. The desired circuit function is obtained. Usually, wiring layer 16
is covered with a protective film 18 such as PSG (phosphosilicate glass), and one end and the other end of the wiring layer 16 are covered with a protective film 18 such as PSG (phosphosilicate glass).
The connection layers C 1 and C 2 as bonding pads lead out to the upper surface of the protective film 18 .
解析対象となるICチツプ１０を用意した後、
このチツプを電気的に動作可能な状態とする。具
体的には、上記した第１の場合は、接続層C1及
びC2に金属探針（プローブ）を立てて外部から
電圧信号を印加できるようにし、上記した第２の
場合は、パツケージの外部端子（リード）に電圧
信号を印加できるようにする。第１図の端子T1
及びT2は、プローブ又はリードに相当する。 After preparing the IC chip 10 to be analyzed,
This chip is made electrically operable. Specifically, in the first case described above, metal probes are set up on the connection layers C 1 and C 2 so that a voltage signal can be applied from the outside, and in the second case described above, a metal probe is set up on the connection layers C 1 and C 2 so that a voltage signal can be applied from the outside. Allows voltage signals to be applied to external terminals (leads). Terminal T 1 in Figure 1
and T 2 corresponds to a probe or lead.
次に、チツプ上面に一例としてネマテイツク液
晶MBBAを塗布した後余分な液晶を除去してチ
ツプ上に極めて薄い（約３［μｍ］以下）液晶膜
２０を形成する。そして、ICチツプ１０を、液
晶膜２０の形成面が上になるようにして光学顕微
鏡３０の下に置く。 Next, for example, a nematic liquid crystal MBBA is applied to the upper surface of the chip, and then excess liquid crystal is removed to form an extremely thin (approximately 3 μm or less) liquid crystal film 20 on the chip. Then, the IC chip 10 is placed under the optical microscope 30 with the surface on which the liquid crystal film 20 is formed facing upward.
光学顕微鏡３０にあつては、対物レンズ３２と
接眼レンズ３４との間に光源３６からの光を観察
対象に向けるようにハーフミラー３８が設けられ
ると共に、光源３６とハーフミラー３８との間及
び接眼レンズ３４とハーフミラー３８との間には
各々の偏光面が互いに直角をなすようにして第１
及び第２の偏光子４０及び４２がそれぞれ配置さ
れている。 In the optical microscope 30, a half mirror 38 is provided between the objective lens 32 and the eyepiece 34 so as to direct the light from the light source 36 toward the observation target, and a A first mirror is disposed between the lens 34 and the half mirror 38 so that their polarization planes are perpendicular to each other.
and second polarizers 40 and 42, respectively.
次に、端子T1及びT2に一例としてピーク電圧
が＋５［Ｖ］、周波数が５［Hz］の方形波パルス状
電圧信号Vaを印加する。そして、この電圧印加
状態において光学顕微鏡３０を介して肉眼でIC
チツプの上面を観察する。 Next, as an example, a square wave pulse voltage signal Va having a peak voltage of +5 [V] and a frequency of 5 [Hz] is applied to the terminals T 1 and T 2 . Then, in this voltage application state, the IC is inspected with the naked eye through the optical microscope 30.
Observe the top of the chip.
いま、配線層１６がＸの個所で断線しているも
のとすると、Ｘより左側の部分Ａでは、顕微鏡３
０からの光Ｐが矢印ａ方向の偏光面をもつてチツ
プ上面に入射し、その反射光Ｑが矢印ｂ方向の偏
光面をもつて顕微鏡３０に入射する。このとき、
配線層１６のＸより左側の部分には断線により電
圧が印加されていないので、第２図KAに示すよ
うに光学的な何等変化が認められない。 Now, assuming that the wiring layer 16 is broken at a point X, in a portion A to the left of X, the microscope 3
Light P from 0 is incident on the top surface of the chip with a plane of polarization in the direction of arrow a, and its reflected light Q is incident on the microscope 30 with a plane of polarization in the direction of arrow b. At this time,
Since no voltage is applied to the portion of the wiring layer 16 to the left of X due to the disconnection, no optical change is observed as shown in FIG. 2 KA .
一方、Ｘより右側の部分Ｂでは、配線周辺の電
界の変化によつて液晶物質の分子軸が傾けられる
ために反射光Ｑの偏光面の方向がｂからb′のよう
に変化し、この結果として第２図KBに示すよう
にＸから右側の配線層部分に沿つて濃淡の繰返し
パターンが見られる。 On the other hand, in part B on the right side of X, the molecular axis of the liquid crystal substance is tilted due to the change in the electric field around the wiring, so the direction of the polarization plane of the reflected light Q changes from b to b'. As shown in Figure 2 KB , a repeating pattern of light and shade can be seen along the wiring layer portion on the right side from X.
第２図のKB及びKAにおけるパターンの有無は
顕微鏡３０を介して明瞭に観察されるので、配線
層１６がＸの個所で断線していることを容易に検
出できる。なお、配線層１６が断線なしの正常な
ものであれば第３図に示すような濃淡の繰返しパ
ターンが見られる。 Since the presence or absence of patterns at K B and K A in FIG. 2 can be clearly observed through the microscope 30, it is possible to easily detect that the wiring layer 16 is broken at the location X. Note that if the wiring layer 16 is normal with no disconnections, a repetitive pattern of shading as shown in FIG. 3 will be seen.
上記実施例では、顕微鏡３０を介して肉眼で観
察したが、写真にとつて観察してもよい。また、
電圧信号Vaの電圧値及び周波数は、濃淡の繰返
しパターンが光学的に観察可能に現われる範囲で
適宜設定すればよく、上記した例示値に限定され
るものではない。 In the above embodiment, the observation was made with the naked eye through the microscope 30, but the observation may also be made by taking a photograph. Also,
The voltage value and frequency of the voltage signal Va may be appropriately set within a range in which a repeating pattern of light and shade appears optically observable, and are not limited to the above-mentioned exemplary values.
［発明の効果］
以上のように、この発明によれば、電圧印加に
伴つて生ずる濃淡の繰返しパターンを光学的に観
察するようにしたので、配線保護膜エツチング処
理、カバーガラス設置処理、配向処理等の面倒な
準備処理が不要であり、簡単且つ迅速にICの故
障解析を行うことができ、しかもICの通常使用
電圧以下の電圧で安全且つ確実に断線個所を検出
できるなど優れた効果が得られるものである。[Effects of the Invention] As described above, according to the present invention, the repeating pattern of shading that occurs as a result of voltage application is optically observed. This method eliminates the need for troublesome preparation processes, allows for easy and quick IC failure analysis, and has excellent effects such as safely and reliably detecting disconnections at voltages below the IC's normal operating voltage. It is something that can be done.
第１図は、この発明のIC配線検査法の一実施
例を説明するための配置図、第２図及び第３図
は、それぞれ断線ありの配線層及び正常な配線層
について濃淡の繰返しパターンを示す上面図であ
る。
１０……ICチツプ、１２……半導体基板、１
４……絶縁膜、１６……配線層、１８……保護
膜、２０……液晶膜、３０……光学顕微鏡。
FIG. 1 is a layout diagram for explaining one embodiment of the IC wiring inspection method of the present invention, and FIGS. 2 and 3 show repeated patterns of shading for a wiring layer with a disconnection and a normal wiring layer, respectively. FIG. 10...IC chip, 12...semiconductor substrate, 1
4... Insulating film, 16... Wiring layer, 18... Protective film, 20... Liquid crystal film, 30... Optical microscope.
Claims (1)
おうように液晶膜を形成するステツプと、 (b) 前記配線層にパルス状の電圧信号を印加する
ことにより電界効果による液晶物質の分子軸の
傾きを反映した光学的に観察可能な濃淡の繰返
しパターンを前記配線層に沿つて前記液晶膜に
生じさせるステツプと、 (c) 前記濃淡の繰返しパターンの生成状態を光学
的に観察することにより前記配線層の断線個所
を検出するステツプと を含む集積回路の配線検査法。[Claims] 1. (a) forming a liquid crystal film on the top surface of an integrated circuit chip so as to cover the wiring layer; and (b) applying a pulsed voltage signal to the wiring layer to generate an electric field effect. (c) generating an optically observable repeating pattern of light and shade in the liquid crystal film along the wiring layer, reflecting the inclination of the molecular axis of the liquid crystal material; A method for inspecting wiring of an integrated circuit, comprising the step of detecting a disconnection point in the wiring layer by visually observing the wiring layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63172038A JPH0222572A (en) | 1988-07-11 | 1988-07-11 | Wiring inspecting method for integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63172038A JPH0222572A (en) | 1988-07-11 | 1988-07-11 | Wiring inspecting method for integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0222572A JPH0222572A (en) | 1990-01-25 |
| JPH0581866B2 true JPH0581866B2 (en) | 1993-11-16 |
Family
ID=15934376
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63172038A Granted JPH0222572A (en) | 1988-07-11 | 1988-07-11 | Wiring inspecting method for integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0222572A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4001373B2 (en) * | 2003-01-21 | 2007-10-31 | 独立行政法人理化学研究所 | Integrated circuit disconnection inspection method and apparatus |
| DE102004045025B3 (en) * | 2004-09-15 | 2006-02-16 | Phoenix Contact Gmbh & Co. Kg | Electrical connection or connection terminal |
| WO2023272704A1 (en) * | 2021-07-01 | 2023-01-05 | 重庆康佳光电技术研究院有限公司 | Detection membrane and manufacturing method, chip bonding detection method and device, and classification method |
-
1988
- 1988-07-11 JP JP63172038A patent/JPH0222572A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0222572A (en) | 1990-01-25 |
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