JPH02224516A - Adaptive signal processing circuit - Google Patents

Abstract

PURPOSE:To decrease the number of program steps relating to the calculation of power sum by adding 1s with an adder circuit so as to reduce the power sum calculation error and using an integrated adder circuit so as to simplify the control of the power sum calculation. CONSTITUTION:A high order 8-bit of a data of a data latch 1 is inputted to an adder 5 and a multiplexer 6 with a high level of a signal 103. The adder 5 adds 1 to the least significant digit, the multiplier 6 calculates square of data and stores the result in an accumulator 10. When a signal 103 goes to a low level, the high order 8-bit of the data in the latch 2 is inputted to a multiplexer 4, the calculated value squared by the multiplier 6 is latched by a latch 7 with a control signal 106 and a logical inversion data is inputted to the adder 5. Thus, the output of the adder 5 is 2's complement of the output value of the multiplier 6. Thus, the calculation error of the power sum is decreased by the addition of 1s and the number of calculation steps is decreased by 2's complement.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an adaptive signal processing circuit that corrects filter coefficients so as to minimize the square of a prediction error, and in particular, relates to an adaptive signal processing circuit that corrects filter coefficients so as to minimize the square of a prediction error. Therefore, the present invention relates to an adaptive signal processing circuit that repeatedly adds the squares of input signals.

[Prior Art] Conventionally, adaptive signal processing algorithms have been used to modify filter coefficients so as to minimize the square of prediction and measurement errors.
5tochastic approximation algorithm
)It has been known.

This algorithm performs prediction using an input signal sequence and a quantization error signal. For example, each signal is input from a signal source and a noise source, and the noise component of the signal input from the signal source is predicted and removed. By doing so, it was used in noise cancellers, etc. that remove noise.

FIG. 6 is a diagram showing an example of the system configuration of such a noise canceler.

In FIG. 6, s (k) is the signal input from the noise source 162, P (k) is the predicted noise signal, and e 4 (k)
is the system output signal obtained by removing P (k) from the signal s (k) from the signal source 161.

In the stochastic approximation algorithm, the input signal vector 5s (k-1) from the past noise source is 1, SN (k
-1) = [5(k-1), 5(k-2), ---5
(k-N)]"... (1) The filter coefficient vector A (k-1) of the adaptive filter 163 in FIG. 6 is expressed as A(k-1) = [at(k-1) ), az(k-1
).

..., a5(k-1)]1 d...(2) Then, the current predicted noise P due to the past input signal sequence is
(k) can be expressed as shown in equation (3) below.

P(k)=A (k-1)S N (k-1)
...... (3) Also, the filter coefficient correction formula A
(k+1) is obtained as shown in the following equation (4).

A(k+1> = α・A (k) where α is a constant of 0 and α<1, g and Con5t are constants given to the system. Ss” in equation (4)
(k) The term 5N(k) is a term used for normalization and is called a power sum. This power sum value needs to be updated every time a signal is input from the noise source.

In adaptive signal processing such as noise cassette, - generally (4
), that is, the number of taps of the adaptive filter 163, is very large, for example, about N=103. For this reason,
Conventional adaptive signal processing methods have a problem in that they require a huge amount of calculation to modify filter coefficients. (
For example, 1. D.

Gibson et at, “5equentia
lly Adaptive Prediction an
d Coding of 5peech Signal
sIEEE Trans, on Communica
tions VOL, C0M-22°No, 11
Nov. 1974, etc.).

Therefore, as a means to reduce such a huge amount of calculations, methods of deleting the number of bits for power sum calculations and methods of reducing the amount of calculations using memory are being considered.

Among these, in the latter method, the power sum P, (k)=
S w”(k) Regarding S 5(k), the following (5)
Using the recurrence formula of Eq.

P, (k)=P, (k-1)+82(k)-3
2(k-N)...(5) That is, the past power sum value P, (k-1) is stored, and the sample value s(i) input from the noise source is stored in memory for N samples. The square of the value s2(k) newly input from the noise source is added to P,(k-1), and from the addition result, the square of the oldest data in the memory is calculated.
By subtracting 2(k-N), P in equation (5), (k
). Thereafter, s (k) is stored in memory instead of data s (k-N) in memory.

Conventionally, in the method using this recurrence formula, processing procedures such as two multiplications, one addition, and one subtraction are determined by a program, and the number of program steps for calculating the power sum is large enough to not be ignored. It was.

In addition, if the number of bits for calculating the power sum is set to, for example, 0 digits after the decimal point, that is, if n+1 digits or less are truncated, data 5 (i) before truncation and data S after truncation.
o(i) has the following relationship.

s o (i) Ss (i) < s o (i) + 2-
The maximum value of the error due to truncation regarding '-(6)s''(i) is expressed by the following equation (7).

(s o(i)+2-”) ”-s, 2(i)=
2-”ls o(i)+2-”-(7)
For the power sum P,(k), this error is added by the number of taps.

[Problems to be Solved by the Invention] As explained above, in conventional applied signal processing circuits, when the number of power sum calculation bits is reduced in order to reduce the amount of calculation and further reduce the amount of hardware, the error The disadvantage was that it became large.

In addition, even when calculating the power sum using the recurrence formula mentioned above, the number of program steps is still large because the calculation processes of two multiplications, one addition, and one subtraction are executed by a program, etc. was there. Generally, in an adaptive signal processing circuit such as a noise canceller, the number of taps of an adaptive filter is limited by the number of program steps that can be executed within a certain period of time. If the number of program steps for calculating the power sum overwhelms the number of steps of other programs, there is a problem that the number of taps that can be processed becomes smaller.

The present invention has been made in view of such problems, and includes:
It is an object of the present invention to provide an adaptive signal processing circuit that has a small number of calculation steps and has fewer errors due to a reduction in the number of calculation bits.

[Means for Solving the Problems] An adaptive signal processing circuit according to the present invention includes a first data latch that latches current sampling data, and a first data latch that latches sampling data N (N is a positive integer) sampling periods before. 2 data latches, a first multiplexer that inputs the outputs of the first and second data latches and selects and outputs one of them, and the output of the first multiplexer that inputs the output of the first multiplexer to one input terminal. a second multiplexer that selects and outputs one of the data input to the output and the other input terminal; an adder that adds 1 to the output of the second multiplexer; a third data latch that latches the output of this multiplier and outputs its inverted data to the other input terminal of the second multiplexer; and an output of the multiplier. and the output of the adder, a third multiplexer that selects and outputs one of them; an accumulative adder that cumulatively adds the outputs of the third multiplexer; A third multiplexer selects the outputs of the first data latch, the first multiplexer, and the multiplier, respectively, and causes the cumulative adder to perform addition, and in a second period, the first to third multiplexers select the outputs of the first data latch, the first multiplexer, and the multiplier, respectively. selecting the outputs of the second data latch, the first multiplexer and the multiplier, and causing the second and third multiplexers to select the outputs of the third data latch and the adder, respectively, in a third period; The present invention is characterized by comprising a control means for supplying a control signal for causing the adder to perform addition to the first to third multiplexers and the cumulative adder.

[Operation] According to the present invention, in the first period, the square of the current sampling data stored in the first data latch is calculated, and in the second period, the square of the current sampling data stored in the second data latch is calculated. The square of the sampled data before the sampling period is calculated.

In these calculations, since 1 is added to one of the multiplicands by the adder, correction for the reduction in the number of bits for power sum calculation is performed, and errors due to reduction in the number of bits for calculation can be reduced.

Further, according to the present invention, two's complement representation is obtained by selecting the first to third multiplexers, and addition, that is, two additions including subtraction, is the same as two multiplications by the two's complement representation. Since the calculation is performed at the same timing, the number of calculation steps can also be reduced.

[Example] Next, the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a diagram showing the configuration of an adaptive signal processing circuit according to a first embodiment of the present invention.

In FIG. 1, data latch 1 and data latch 2 are 8-bit data latches that transfer the upper 8 bits of 20-bit audio data on data bus 114 to buses 115 and 11.
6 respectively. Data latch 1 is currently (
Time 1=1. ), and data latch 2 latches the upper 8 bits of the audio data 1024 sampling cycles ago. In this embodiment, the sampling period is 20.8 μs, so the data latched in data latch 2 is stored at time 1=1.
゜-21.3ms (1024X 20.8μs = 2
1.3m5) are the upper 8 bits of the audio data. Furthermore, the upper 8 bits include a sign bit.

The outputs of these data latches 1 and 2 are connected to the 8-bit bus 1.
01 and 102, respectively, to two input terminals of the multiplexer 3. The multiplexer 3 is a multiplexer that selectively outputs one of the bus 101 from the data latch 1 and the bus 102 from the data latch 2. When the control signal 103 is at a high level, the multiplexer 3 selects the bus 101,
If the level is low, bus 102 is selected.

The output of multiplexer 3 is supplied via an 8-bit bus 104 to one input end of multiplexer 4.

Multiplexer 4 selects either bus 104 or bus 110 for 15-bit output data from data latch 7, which will be described later, and outputs it to 15-bit data bus 107.

If bus 104 is selected, the contents of bus 104 are output to the lower eight bits of bus 107. This multiplexer 4 controls the bus 1 when the control signal 106 is at high level.
04 is selected and the control signal 106 is low level,
Select bus 110. The output of multiplexer 4 is supplied to adder 5 and multiplier 6 via bus 107.

The adder 5 is a circuit that adds 1 to the contents of the bus 107 and outputs it to the bus 108. For example, if the contents of the bus 107 are '003F,'', add 1 to it and output it to the bus 108.
The output of the adder 5 is given to the multiplier 6 via a 15-bit bus 108.

Multiplier 6 combines the contents of the lower 8 bits of bus 107 with bus 10.
Perform signed multiplication with the contents of the lower 8 bits of 8,
The result is output to data latch 7 and multiplexer 8 via 15-bit bus 109.

The data latch 7 is a circuit that latches the contents of the bus 109 at the falling edge of the control signal 106, inverts the logic of the latched value, and outputs its output to the multiplexer 4 via the 15-bit bus 11°.

The multiplexer 8 also selects one of the 15-bit data bus 109 and 108, and selects one of the 15-bit data buses 109 and 108.
A multiplexer that outputs an output to bus 11 selects bus 109 when control signal 106 is at high level, and selects bus 108 when it is at low level. This selection output is given as one input of adder 9.

Adder 9 is output from multiplexer 8 via bus 111 . This is a 25-bit adder/adder that adds the content and the content output from the accumulator 10 via the bus 113, which will be described later, and outputs the result to the accumulator 10 via the 25 bit bus 112. This adder 9 starts the addition operation at the falling edge of the control signal 114, sign-extends the most significant bit (sign bit) of the 15 bit bus 113 by 10 bits to obtain 25 bit data, and then adds this data. 25 and the contents of the bus 113 are added.

Accumulator 10 latches the contents provided from adder 9 via bus 112 at the falling edge of control signal 114 and outputs it to 25-bit bus 113. This accumulator 1o and adder 9 constitute a cumulative adder.

Further, the delay circuit 11 transmits the control signal 103 to 100n.
Output with a delay of s. OR gate 12 is control progress 10
This circuit outputs the logical sum 6 of 3 and the output signal 105 of the delay circuit 11 as a control signal 106.

FIG. 2(a) shows the structure of data on bus 114 in FIG. 1, and FIG. 2(b) shows the structure of data on bus 107 and bus 108 when control signal 106 is at high level. , FIG. 2(c) shows the structure of data on the bus 107 and the bus 108 when the control signal 106 is at a low level. The structure of data on bus 109 and bus 110 is always the structure shown in FIG. 2(C). Adder 5 performs a process of adding 1 to the least significant bit of data on bus 107, regardless of the value of control signal 106.

Next, the operation of the circuit of this embodiment configured as described above will be explained.

FIG. 3 shows a time chart of the operation of this embodiment.
In the figure, Ml, M2. Al, X and AD are the first
Signal 103, signal 106, bus 108, bus 109 in the figure
and the contents of the signal 114.

When the signal 103 becomes high level at time A (A>to) in FIG.
The upper 8 bits of audio data at =10 are bus 101
, 104 and 107, the adder 5 and the multiplier 6
is input. Adder 5 unconditionally adds 1 to the least significant digit of bus 107 and outputs it to bus 108. This addition is for correcting the truncation of the lower 12 bits when the audio data on the bus 114 is taken into data latch 1 and data latch 2.

That is, the audio data on the bus 114 is 5(i), and the data taken into data latch 1 and data latch 2 is s0.
(i), output data of adder 5 as s, (i)+2″′
+1, the following relationship holds true regardless of the sign of 5(i).

s, (i)≦s(i)<s0(i)+2”
” ...(8) Here, if the possible values of s (i) are uniformly distributed, the average value of s (i) is s,
, (i) can be expressed as follows.

= s, (i) + 2-”-1= (9) Therefore, the average, value s, and the square of (i) are as follows.

,',sm(i)2=s0(i)2+2-'5o(i)
+2-”-2”=80(1)”+2-”s o(
t) = s, (i) (s, (i)+2-”)...
...(10) The multiplier 6 calculates s, (i) (s, (i)+2-"l) shown in the above equation (10). Calculation result of the multiplier 6 are input to the adder 9 via buses 109 and 111, respectively.At time B, the adder 9 performs an addition operation, and at time C, the addition result is stored in the accumulator 10.

On the other hand, when the signal 103 becomes low level at the time, the time j ” 'f latched in the data latch 2
-o The upper 8 bits of the audio data at 21.3 ms are input to the multiplexer 4 via buses 102 and 104, respectively. At this time, the control signal 106 is at a high level, and this 8-bit audio data is output to the bus 107. Thereafter, the multiplication result by multiplier 6 is output to bus 109 in the same manner as in the above-described operation.

At time E, when 100 ns have elapsed from the clock, when the control signal 106 transitions from high level to low level, the multiplication result output to the bus 109 is latched to the data latch 7, and the data obtained by logically inverting the multiplication result is transferred to the bus 110. , 117 to the adder 5. Therefore, the output of the adder 5 is the two's complement of the output value of the multiplier 6 immediately before time E. This two's complement number is input to an adder 9 via a multiplexer 8.

Adder 9 and accumulator 10 at times F and G below
The operation is similar to that at times B and C, but since the data to be added is a two's complement representation of the multiplication result of the multiplier 6, at time F, subtraction processing is performed.

The processing explained above is based on the sampling period of audio data (2
It can be executed every 0.8 μs). Therefore, according to this embodiment, power sum calculation of 1024 taps can be easily executed.

Note that the bus width, data latch,
The number of bits of multiplexers and accumulators, the bit configuration of multipliers and adders, the delay time of delay circuits, etc. are not limited to the above-mentioned bus width, bit configuration, delay time, etc., and may be other suitable values. Needless to say, this can also be achieved through configuration.

FIG. 4 is a diagram showing the configuration of an adaptive signal processing circuit according to a second embodiment of the present invention. In FIG. 4, blocks and signals labeled with the same numbers as in FIG. 1 are the same as those in the previous embodiment.

In this embodiment, an additional value generation circuit 60 is newly provided. The added value generation circuit 60 is a circuit that outputs an added value signal 150 based on the contents of the data bus 107 and the control signal 106. This addition value generation circuit 60 is configured as shown in FIG. 5, for example. In Figure 5, D1
4. D13. ....

Do is the data of each bit of the bus 107 in FIG.
14 is the MSB (most significant bit) and DO is the LSB (least significant bit).
When the content of 7 is the maximum positive value, gate circuits 51 to 57
This circuit detects this and sets the addition input value ADDI (signal 150) to the adder 5 to "0'". That is, the control signal 106 is at a high level, and the contents of the bus 107 are 007FH.
or the control signal 106 is low level, the bus 107
When the content of is 3 F F F II, the signal 150 becomes low level.

Note that in this second embodiment, the adder 5 receives the signal 15
Add the contents of 0 to the least significant digit of bus 107.

Therefore, when the signal 150 is at a low level, no addition processing is performed.

According to this embodiment, overflow due to addition by the adder 5 can be prevented.

Further, since the operations other than those described above are the same as the circuit operations of the first embodiment described above, a description thereof will be omitted here.

[Effects of the Invention] As explained above, the present invention is capable of reducing power sum calculation errors by using an addition circuit that adds 1, and also simplifies control for power sum calculation using this addition circuit. The number of program steps involved in power sum calculation can be reduced.

In general, in adaptive signal processing circuits such as noise 2 cancellers, the number of taps of the adaptive filter is limited by the number of program steps that can be executed within a certain period of time, so reducing the number of program steps involved in power sum calculation is extremely effective. big.

Further, according to the present invention, since it is possible to improve the power sum calculation accuracy, it is possible to reduce the number of data bits in the power sum calculation section, and it is possible to reduce the amount of hardware. Therefore, the effect is very large.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an adaptive signal processing circuit according to the first embodiment of the present invention, FIG. 2 is a diagram showing the data structure on the bus of the circuit shown in FIG. 1, and FIG. 4 is a circuit diagram of the adaptive signal processing circuit according to the second embodiment of the present invention, FIG. 5 is a detailed circuit diagram of the addition value generation circuit shown in FIG. 4, and FIG. 6 is a timing diagram of the circuit shown in FIG. FIG. 2 is a system configuration diagram of a noise canceller. 1.2.7; Data latch, 3, 4. s; multiplexer, 5.9; adder, 6; multiplier, 10; accumulator, 60; addition value generation circuit, 161; signal source, 162;
Noise source, 163; Adaptive filter Fig. 1 (b) ↑ l・Number sense↑ 4. Cheers・ (C) Fig. Fig. Fig. Fig.

Claims (1)

[Claims] (1) A first data latch that latches current sampling data, and a second data latch that latches sampling data N (N is a positive integer) sampling period before;
a first multiplexer that inputs the outputs of the first and second data latches and selects and outputs one of them;
a second multiplexer that inputs the output of the first multiplexer to one input terminal and selects and outputs one of the above output and the data input to the other input terminal;
an adder that adds 1 to the output of the multiplexer; a multiplier that multiplies the output of this adder by the output of the second multiplexer; and a multiplier that latches the output of this multiplier and applies the inverted data to the second multiplexer. a third data latch that outputs to the other input end of the multiplexer; a third multiplexer that receives the output of the multiplier and the output of the adder and selects and outputs one of them; an accumulative adder that cumulatively adds outputs of the multiplexers; and an accumulative adder that causes the first to third multiplexers to select the outputs of the first data latch, the first multiplexer, and the multiplier, respectively, in a first period; The outputs of the second data latch, the first multiplexer, and the multiplier are selected by the first to third multiplexers, respectively, in a second period, and the outputs of the second and third multiplexers are selected in a third period. control means for supplying a control signal to the first to third multiplexers and the cumulative adder to cause the third multiplexer to select the output of the third data latch and the adder, respectively, and to cause the cumulative adder to perform addition; An adaptive signal processing circuit characterized by comprising: