JPH02224267A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce parasitic impedance between a bonding pad and an internal reference voltage generator circuit by disposing said internal reference voltage generator circuit in the vicinity of the ground input bonding pad. CONSTITUTION:A voltage limiter circuit is divided into an internal reference voltage generator circuit 6 and a drive circuit 7, and the internal reference voltage generator circuit 6 is disposed in the vicinity of a ground input bonding pad 4. Hereby, parasitic impedance of a ground wiring 9 can be reduced and highly accurate internal reference voltage stable against ground noise can be yielded. Further, an internal reference voltage wiring 10 can reduce any noise from the adjacent wiring layer using a shielding line, and is made stable against power supply noise because of parasitic capacity possessed by the shielding line.

Description

[Detailed description of the invention]

[Industrial Application Field] The present invention relates to a semiconductor integrated circuit, and particularly to a semiconductor integrated circuit that uses an internal power supply voltage different from an external power supply voltage inside the integrated circuit.

[Prior Art] As elements in highly integrated circuits become smaller, element breakdown voltage tends to decrease. Therefore, it is necessary to lower the voltage applied to these elements, and as a method for this purpose, it has been proposed to provide a voltage step-down circuit on the semiconductor device. This step-down circuit (
For example, regarding the voltage limiter circuit (hereinafter referred to as voltage limiter circuit),
I.E.E. Journal of Solid State Circuits Volume Nisshii 22.
Number 3, pages 437 to 441, June 1987 (IEEE, Journal ○f S. 1id-9tate C1rcuts, Vol. 5C-22, No, 3.PP, 437-441゜Jun
e 1987). FIG. 2 shows the circuit configuration of the voltage limiter circuit described in this document. In the same figure, 6 is the internal power supply voltage VL
An internal reference voltage generation circuit generates constant voltages V and R that serve as the reference for the circuit, and 7 is a drive circuit that supplies an internal power supply voltage to the load circuit based on the internal reference voltage. In the internal reference voltage generation circuit 6, transistors Q1 to Q4 constitute a constant current source, and Q5 generates an internal reference voltage based on the ground voltage. The drive circuit 7 is a feedback circuit composed of a differential amplifier composed of transistors Q6 to Qll and a PMOS transistor Q i 2. The internal reference voltage and internal power supply voltage are input to the differential amplifier, and the voltage difference is amplified and output. Transistor Q7 is a current source for the differential amplifier and is always on. Transistor Q6 is turned on and off by drive circuit activation signal φ, and controls the current consumption of the differential amplifier. Transistor Q12 is a drive transistor that receives the output of the differential amplifier and generates an internal power supply voltage from external power supply voltage vCC. As described above, the voltage limiter circuit includes an internal reference voltage generation circuit 6 that generates an internal reference voltage based on the ground voltage,
It is composed of a drive circuit 7 that generates an internal power supply voltage from an external power supply voltage based on the internal reference voltage. Further, the load circuit operates with the internal power supply voltage lowered by the voltage limiter circuit to cope with the reduction in the element breakdown voltage. [Problems to be Solved by the Invention] The above-mentioned conventional technology takes into consideration the arrangement of each circuit constituting the voltage limiter circuit, the arrangement of the load circuit, and the method for connecting the layerer 1, such as external and internal power supply voltage wiring, and ground voltage wiring. Instead, the voltage limiter circuit was simply placed near the body butt for inputting the external power supply voltage9.For this reason, when mounted in a package with pin placement restrictions, the following problems occurred. Figure 3 shows a typical MOS/dynamic RAM package and a dynamic RAM equipped with a voltage limiter circuit.
The circuit layout inside the chip is shown. 41 is the entire package and 1 is a chip. 42, 43, and 44 are input/output pins, of which 42 is an input pin for external power supply voltage, and 43 is an input pin for ground voltage. Both pins are arranged symmetrically about the center of the package. 5 is a bonding pad for inputting an external power supply voltage, and 4 is a bonding pad for inputting a ground voltage. Further, 8 is an external power supply voltage wiring, and 9 is a ground voltage wiring. 6 is an internal reference voltage generation circuit, and 7 is a drive circuit. These two circuits constitute a voltage limiter circuit. L is a load circuit that receives the internal power supply voltage output from the voltage limiter circuit. 10 is an internal reference voltage wiring, and 11 is an internal power supply voltage wiring. In the conventional technology, the parasitic impedance of the wiring between the bonding pad 5 and the drive circuit 7 was reduced by simply arranging the voltage limiter circuit near the bonding pad 5 for inputting the external power supply voltage. In this case, the wiring between the ground voltage input bonding pad 4 and the internal reference voltage generation circuit 6 becomes long, and the parasitic impedance becomes large. Therefore, large ground noise is generated by the current flowing when the load circuit operates, and the ground noise is superimposed on the internal reference voltage, which should originally be a constant voltage, and noise is also generated in the internal power supply voltage. As a result, there is a problem in that the deterioration of elements with low breakdown voltages that are supplied with the internal power supply voltage is promoted, and the reliability of the elements cannot be ensured. Further, by arranging the drive circuit 7 near the bonding pad 5 for external power input, the internal power supply voltage wiring becomes long and the parasitic resistance on the wiring becomes large. As a result, there is a problem in that the voltage drop during operation of the load circuit due to the parasitic resistance becomes large, and the internal power supply voltage applied to the load circuit becomes low. The present invention solves the above problems and provides a stable and highly accurate internal reference voltage generation circuit and a drive circuit that reduces fluctuations in internal power supply voltage due to the operation of a load circuit, without increasing the chip area. The purpose is to achieve the above effects. (Means for Solving the Problems) In order to achieve the above object, the present invention separates the internal reference voltage generation circuit and the drive circuit, places the internal reference voltage generation circuit near the ground input bonding pad, and places the drive circuit in the vicinity of the ground input bonding pad. Place each near the load circuit.Also, apply electrostatic shielding to the wiring between the internal reference voltage generation circuit and the drive circuit, and add capacitance to the wiring between the drive circuit and the load circuit.Furthermore, provide a capacitor for the external power supply voltage input. The wiring between the bonding pad and the drive circuit is thick and laid out at the shortest distance, and a decoupling capacitance is formed under the wiring as necessary.

[Effect] By dividing the voltage limiter circuit into a reference voltage generation circuit and a drive circuit, and placing the internal reference voltage generation circuit near the ground input bonding pad, the parasitic impedance of the ground wiring can be reduced, resulting in stable and high resistance to ground noise. Accurate internal reference voltage can be obtained. In addition, the internal reference voltage wiring can reduce noise from adjacent wiring by using a shielded wire, and also becomes stable against power supply noise due to the parasitic capacitance of the shielded wire. As for the drive circuit, by arranging the drive circuit near the load circuit, it is possible to reduce the parasitic resistance of the internal type IS voltage wiring, thereby reducing the voltage drop that occurs there. Furthermore, by adding capacitance to the internal power supply voltage wiring, the parasitic impedance of the wiring can also be reduced. Furthermore, the parasitic impedance of the external power supply voltage wiring can be reduced by thickening the wiring between the external power supply input bonding pad and the drive circuit and adding decoupling capacitance. Note that by forming the above capacitor under the external power supply wiring, the above effect can be achieved without increasing the area. 【Example】

An embodiment in which the present invention is applied to a semiconductor memory will be shown below, but the present invention can also be applied to other semiconductor integrated circuits. A first embodiment is shown in FIG. In the figure, 1 indicates the entire chip, 2 is a memory array composed of microscopic elements, and 3 is a peripheral circuit that controls the memory array. Further, 4 is a ground voltage, 5 is a bonding pad for external power supply voltage input, 6 is an internal reference voltage generation circuit, and 7 is a drive circuit, and 6 and 7 constitute a voltage limiter circuit. CDI is a decoupling capacitor for internal power supply voltage. In this embodiment, one peripheral circuit 3 is operated with an external power supply voltage,
The memory array 2 is operated with an internal power supply voltage stepped down by a voltage limiter circuit constituted by an internal reference voltage generation circuit 6 and a drive circuit 7. That is, the memory array 2 serves as a load circuit for the voltage limiter circuit. The feature of this embodiment is that the internal reference voltage generation circuit 6 and the drive circuit 7 are separated, the internal reference voltage generation circuit 6 is placed near the ground voltage input pad 4, and the drive circuit 7 is placed in the load circuit, that is, the memory array. The internal reference voltage generation circuit 6 and the drive circuit 7
This is because the wiring 10 between the two is provided with an electrostatic shield. In addition, a decoupling capacitor CD is connected to the internal power supply voltage wiring 11.
By adding I, the parasitic impedance of the wiring 11 is reduced. As a result, the parasitic impedance of the ground voltage wiring 9 between the internal reference voltage generation circuit 6 and the ground input bonding pad 4 is reduced, and ground noise is reduced. Further, the internal reference voltage wiring 10 is electrostatically shielded to eliminate coupling noise from other signal lines and the board, and is wired to the drive circuit 7 located at the bottom of the chip. This results in
Power supply noise is reduced by the parasitic capacitance of the shielded wire. Here, the drive circuit 7 is arranged so as to be close to both the bonding pad 5 for inputting the external power supply voltage and the memory array 2 which is the load, so that the external power supply voltage arrangement 38 and the internal power supply voltage wiring 11 are free from parasitics. Reduces resistance. As described above, according to this embodiment, it is possible to reduce noise in the internal reference voltage and prevent a voltage drop in the internal power supply voltage, so that the memory array 2, which is a load, can be driven stably and at high speed. A second embodiment is shown in FIG. In this embodiment, peripheral circuits are arranged on the top, middle, and bottom sides of the chip, and these peripheral circuits are also supplied with an internal power supply voltage that has been stepped down by a voltage limiter circuit. The features of this embodiment are the same as those described above, and in addition, a decoupling capacitor CD2 is added to the external power supply voltage wiring 8. In the peripheral circuit arrangement as shown in this figure, the power supply wiring (8 or 11) extends in the long side direction of the chip. For this reason, the resistance component of the wiring increases, so by placing the drive circuit 7 near the peripheral circuit 3, which is the load, and reducing the parasitic resistance of the internal power supply voltage wiring 11,
The voltage drop occurring on the wiring 11 is reduced. In this embodiment, the external power supply voltage wiring 8 is longer and its resistance is also increased, but this is corrected by the drive circuit 7. The internal power supply voltage does not change, and the external power supply voltage wiring 8
By adding the decoupling capacitance CDI to , the parasitic impedance of the external power supply voltage wiring 8 is reduced, so that the drive circuit 7 can operate at high speed. Further, by forming the decoupling capacitors CD1 and CD2 under the external power supply voltage wiring, the above effect can be obtained without increasing the chip area. In this embodiment, the reference voltage generation circuit 6, the memory array drive circuit 7, the internal power supply voltage distribution! The arrangement relationship of 10 is the same as the embodiment shown in FIG. 1, such as 0 or more.
In this example, since the parasitic resistance of the internal power supply voltage wiring is small, the voltage drop of the internal power supply voltage is small, and the voltage drop on the external power supply voltage wiring is absorbed by the voltage limiter circuit, so that the internal power supply is stable when the load circuit is operating. Power supply voltage can be obtained. Further, these allow high-speed operation of the load circuit.A third embodiment is shown in FIG. 5. The feature of this embodiment is that the peripheral circuit 3 is arranged only in the center of the chip, and the drive circuit 7 is arranged near it. The advantage of this arrangement is that since the wiring within the peripheral circuit 3 is shorter, the processing speed can be increased compared to the above embodiment. If the speed is increased, the interval between signals generated in the peripheral circuit 3 will become shorter, and the external power supply voltage wiring and internal reference voltage wiring #! In the conventional system, the voltage drop increases because the peak current flowing through the circuit 8 increases, but according to this embodiment, the amount of voltage drop decreases as in the previous embodiment. Furthermore, they prevent timing racing, etc., and enable more stable operation. A fourth embodiment is shown in FIG. The feature of this embodiment is that the peripheral circuit 3 is placed in the center of the chip, and the external power supply and ground voltage input pads 5 and 4 are also placed in the center of the chip. In this embodiment, as in the previous embodiment, the internal reference voltage generation circuit 6 is located near the ground voltage input bonding pad 4, and the drive circuit 7 is located near the external power supply voltage input bonding pad 5 and the load circuit (
It is placed in the middle of memory array 2). The advantage of arranging the drive circuit 7 near the load circuit is as described above.
An advantage of arranging the circuit near the load circuit 2 is that the amount of variation in the internal power supply voltage is smaller than in the above embodiments when the load current increases or the external power supply voltage decreases. That is, in the above embodiment, the voltage drop due to the resistance between the external power supply voltage input bonding pad 5 and the drive circuit 7 is caused by the source of the drive transistor Q12 (FIG. 2),
This could be corrected by reducing the voltage between the drains. However, because the resistance is large, if a voltage drop occurs due to a drop in external power supply voltage or an increase in load current beyond a certain amount,
The sum of the voltage drops of the external power supply wiring and the drive transistor was greater than the difference between the external power supply voltage and the internal power supply voltage, and the correction could not be completed, causing the internal power supply voltage to drop below the internal reference voltage. In contrast, in this embodiment, the resistance of the external power supply wiring can be made almost zero, so that a correspondingly large current can be obtained. It also becomes resistant to drops in external power supply voltage. As described above, according to this embodiment, a larger current can be obtained than the above-mentioned one, so that higher speeds can be achieved. It also becomes more stable against fluctuations in external power supply voltage.

【Effect of the invention】

As described above, in the present invention, by arranging the internal reference voltage generation circuit near the ground input bonding pad, the parasitic impedance between the bonding pad and the internal reference voltage generation circuit can be reduced, and as a result, the internal reference voltage The generation circuit output can be stabilized and highly accurate. Further, by wiring the internal reference voltage wiring with a shielded wire, noise from adjacent wiring can be reduced, and furthermore, the parasitic capacitance of the shielded wire makes it stable against power supply noise. By arranging the drive circuit near the load, the resistance of the internal power supply voltage wiring can be reduced, so that the voltage drop occurring on the wiring can be reduced. Furthermore, by adding capacitance to the internal power supply voltage wiring, parasitic impedance of the wiring can be reduced. Furthermore, by thickening the wiring between the external power supply voltage input bonding pad and the drive circuit, parasitic impedance of the wiring can be reduced. Furthermore, by adding a decoupling capacitance to the wiring, the parasitic impedance of the wiring can be further reduced. By forming the above capacitor under the external power supply voltage wiring, the above effect can be obtained without increasing the chip area.

[Brief explanation of the drawing]

1.4 and 5.6 are plan views showing the configuration of a semiconductor memory according to an embodiment of the present invention, FIG. 2 is a circuit diagram of a voltage limiter circuit, and FIG. 3 is a plan view of a conventional general semiconductor memory. It is. Explanation of symbols 1...Semiconductor chip, 2...Memory array, 3...
・Peripheral circuit, 4... Bonding pad for ground input, 5... Bonding pad for external power supply voltage input 6.
...Internal reference voltage generation circuit, 7...Drive circuit, 8
...External power supply voltage wiring, 9...Ground wiring, 10
...Internal reference voltage wiring, 11...Internal power supply voltage wiring, VCC...External power supply voltage, VR...Internal reference voltage, VL...Internal power supply voltage, φ...Drive circuit activation signal , L...Load circuit, 41 package, 42...
・External power supply voltage input pin, 43...Ground input pin, 44...Signal input/output pin, CDI internal power supply voltage decoupling capacitance, CD2...External power supply voltage decoupling diagram.

Claims (1)

[Scope of Claims] 1. An internal voltage generation circuit that steps down the voltage of an off-chip power supply within a semiconductor integrated circuit, the internal voltage generation circuit consisting of an internal reference voltage generation circuit and a drive circuit that drives a load; A semiconductor integrated circuit characterized in that a generating circuit is placed near a ground voltage input terminal of the semiconductor integrated circuit. 2. The semiconductor integrated circuit according to claim 1, wherein the drive circuit is arranged near the load. 3. The semiconductor integrated circuit according to claim 1, wherein an electrostatic shield is applied to the wiring between the output of the internal reference voltage generation circuit and the input of the drive circuit. . 4. A semiconductor integrated circuit according to claim 2, characterized in that a capacitor is added to the output of the drive circuit. 5. The semiconductor integrated circuit according to claim 2, wherein a capacitor is added to the wiring between the external power input terminal and the drive circuit.