JPH02224016A - Data speed converting circuit - Google Patents

Abstract

PURPOSE:To simplify the circuit constitution by delaying a write reset signal by a specific time and selecting this specific time so that the reset state of a read set signal is indicated when a read clock falls. CONSTITUTION:This circuit is equipped with a frequency dividing circuit 2 which generates the write reset signal by dividing the frequency of a write clock to an elastic store 1, a delay circuit 3 which generates a read reset signal for preventing access to the same address of the elastic store 1 with the write reset signal by delaying the write reset signal by the specific period, and a PLL circuit 4 which generates the read clock of the elastic store 1 phase- synchronized with the read reset signal. This specific time is so selected that the reset state of the read reset signal is indicated when the read clock falls. Therefore, only one elastic store 1 is required and no special signal generating circuit is used. Consequently, the circuit scale can be reduced.

Description

[Detailed Description of the Invention] [Summary] Regarding a circuit that converts the speed of data by changing the speed at which data is written to and read from an elastic store, a data speed conversion circuit having a simpler configuration is provided. In order to achieve this, a delay circuit is provided to generate a read reset signal that delays the write reset signal by a predetermined time and does not access the same address as the write reset signal, and the read clock is set to P.
Depending on whether the LL circuit generates the write reset signal from the write reset signal or its delay circuit output, the read reset signal is generated by the pulse width adjustment circuit as necessary so that the read reset signal indicates the reset state at the falling edge of the read clock. 9 [Industrial Application Field] The present invention relates to a data rate conversion circuit, and in particular, the present invention relates to a data rate conversion circuit, and in particular, the present invention relates to a data rate conversion circuit that increases the data rate by changing the speed at which data is written to an elastic store and the speed at which it is read. This relates to a circuit that converts .

Data sent from a subscriber line termination device used in a digital communication network to a terminal at a speed of, for example, 1.5 Mb/s is transmitted to the terminal at a rate of, for example, 3'84 kb/s or 1.
It is necessary to process the data by converting it to data at a speed of 92 kb/s.

[Conventional technology]

FIG. 5 shows a conventional data rate conversion circuit, in which 10 and 20 are elastic stores composed of FIFO memories, etc., 11 is an elastic store 10.
20 is a signal generation circuit that generates a write reset signal WR and a write inhibit signal WI from a write clock WCLK for 20; 12 is an elastic store 10.20;
a signal generating circuit that generates a read reset signal RR and a read inhibit signal RI from a read clock WCLK, X3 and 14 are inverters for inverting the logic of signals, and 15 is a PLI that generates a read clock RCLK synchronized with the write clock WCLK. It is a circuit.

In this conventional example, in order to write the input data DI to the elastic store 10, the signal generation circuit 11 generates write reset No. 53 WR based on the write clock WCLK extracted from the input data DI and turns off the write inhibit signal W+. Elastic Store 10
At the same time, the write inhibit signal Wl is turned on by the inverter 13 to the elastic store 20 so that the input data DI cannot be written.

On the other hand, the read clock RCLK is the write clock W
The read clock RCLK is supplied from the PLL circuit 15 to the elastic store 10.20 with a phase difference of M (the frequency is different to match the receiving side), and the signal generation circuit 12 receives the read clock RCLK from the elastic store 10.20. When the elastic store 10 is writing data based on the write inhibit signal WI, the read reset signal RR is generated based on the write inhibit signal WI, and the read inhibit signal RI is turned on. R1 is inverted and turned off by the inverter 14, and control is performed to read output data DO from address 0.

These relationships are such that when a write to Elastic Store 10.20 is reversed, a signal is generated so that the subsequent write is also reversed, and write/read access to the same address in the same Elastic Store is avoided. There is.

[Problem to be Solved by the Invention] However, in such a conventional data rate conversion circuit, it is necessary to use two memories in order to prevent accesses between write and read operations of the same elastic store from colliding. In addition, there is a problem in that a circuit is required to generate the write/read resen F signal and the write/read inhibit signal.

Therefore, it is an object of the present invention to realize a data rate conversion circuit having a simpler configuration.

[Means to solve the problem] Above! 1! In order to solve this problem, in the data rate conversion circuit according to the first aspect of the present invention, as shown in principle in FIG. and a delay circuit 3 that delays the write reset signal for a predetermined period to generate a read reset signal that does not access the same address of the elastic store 1 as the write reset signal;
and a PLL circuit 4 that generates a read clock for the elastic store 1 that is phase-synchronized with the read reset signal, so that the predetermined time indicates the reset state of the read reset signal at the falling edge of the read clock. has been selected.

Further, in the data rate conversion circuit according to the second invention, the second
As shown in principle in the figure, the write reset signal is delayed by a predetermined time in the adjustment circuit 3 and then applied to the PLL circuit 4 to generate a read clock, and the output signal from the delay circuit 3 is sent to the pulse width adjustment circuit 5. It is also possible to widen the pulse width and use it as a read reset signal.

[For production]

The operation of the first invention shown in FIG. 1 will be explained with reference to the time chart shown in FIG.

First, on the write side of the elastic store 1, the frequency divider circuit 2 converts the write clock WCLK into a write reset signal W.
When R is generated and applied to the elastic store 1, the elastic store 1 captures and stores the input data DI after the write reset signal WR becomes "H" level at the falling edge of the write clock WCLK.

The write reset signal WR is directly sent to the PLL circuit 4, and the PLL circuit 4 generates a phase-synchronized read clock RCLK (different in frequency) and supplies it to the elastic store 1.

Further, the write reset signal WR is delayed by a predetermined time T in the delay circuit 3 and is then provided to the elastic store 1 as a read reset signal RR.

Therefore, the write reset signal WR and read reset signal RR are generated out of sync to prevent access collision.

Note that the delay time T is selected such that the read reset signal RR is in the reset state ("H" level) at the fall of the read clock RCLK, so that a normal read operation can be performed.

FIG. 4 is a time chart showing the operation of the second invention shown in FIG.
The L circuit 4 generates a phase-synchronized read clock RCLK, and the pulse width adjustment circuit 5 generates a read reset signal RR with an expanded pulse width.

Therefore, write access and read access are performed at different times, and the pulse width of the read reset signal RR is widened, so that the read clock RCL
At the time when K falls, the read reset signal RR is always in the reset state ("H'" level), and a normal read operation is guaranteed.

In this way, data rates can be converted with one elastic store without the use of signal generation circuitry including write/read inhibit signals.

〔Example〕

As a first embodiment of the data rate conversion circuit according to the present invention, the frequency dividing circuit 2 uses a counter that inputs the write clock WCLK as a clock and outputs the lip recall RC signal as the write reset signal WR of the elastic store 1. Further, as the delay circuit 3, an n-stage shift register can be used.

As a second embodiment of the data rate conversion circuit according to the present invention, the pulse width adjustment circuit 5 can increase the pulse width, that is, the duty ratio, by using a monostable multipipe rake.

〔Effect of the invention〕

As described above, according to the data speed conversion circuit of the present invention, a delay circuit is provided that generates a read reset signal that delays the write reset signal by a predetermined time and does not access the same address as the write reset signal, and the read clock is controlled by the PLL circuit. Depending on whether the read reset signal is generated from the write reset signal or its delay circuit output, the pulse width adjustment circuit adjusts the pulse of the read reset signal as necessary so that the read reset signal indicates the reset state at the falling edge of the read clock. Since it was configured to widen the width,
Only one elastic store is required, and there is no need to use a special signal generation circuit, so the circuit scale can be reduced.

In Figure 1, 1...Elastic store, 2... Frequency dividing circuit, 3...Delay circuit, 4...P L 1. ,circuit.

In the figures, the same reference numerals indicate the same or corresponding parts.

Claims (2)

[Claims] (1) Frequency divider circuit (
2), a delay circuit (3) that delays the write reset signal for a predetermined time and generates a read reset signal that does not access the same address of the elastic store (1) as the write reset signal; A PLL circuit (PLL circuit) that generates a phase-synchronized read clock for the elastic store (1)
4), wherein the predetermined time is selected to indicate the reset state of the read reset signal at the falling edge of the read clock. (2) Frequency divider circuit (
2), a delay circuit (3) that delays the write reset signal for a predetermined period and generates a signal that does not access the same address of the elastic store (1) as the write reset signal; A pulse width adjustment circuit (5) that generates a read reset signal with a widened pulse width of the output signal, and a PLL that generates a read clock for the elastic store (1) that is phase synchronized with the output signal of the delay circuit (3).
A data rate conversion circuit comprising: a circuit (4);