JPH02223923A - Display panel - Google Patents

Display panel

Info

Publication number
JPH02223923A
JPH02223923A JP1043003A JP4300389A JPH02223923A JP H02223923 A JPH02223923 A JP H02223923A JP 1043003 A JP1043003 A JP 1043003A JP 4300389 A JP4300389 A JP 4300389A JP H02223923 A JPH02223923 A JP H02223923A
Authority
JP
Japan
Prior art keywords
wiring
pattern
constitution
substrate
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1043003A
Other languages
Japanese (ja)
Inventor
Junichi Owada
淳一 大和田
Keiji Nagae
慶治 長江
Eiji Kaneko
英二 金子
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP1043003A priority Critical patent/JPH02223923A/en
Publication of JPH02223923A publication Critical patent/JPH02223923A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To obtain the constitution of a picture element adapted to a large area display by using a consecutive pattern such as a line or a curve. CONSTITUTION:A thin film semiconductor layer 2 which is the active layer of a TFT element combined with a part of a wiring 5 on a signal side is formed on a glass substrate and it is formed in an island shape by performing etching after applying resist. Then, a gate insulating film is formed all over the surface of a substrate. Furthermore, after forming a thin film for wiring on a scanning side, etching work is performed in line shape and doping is performed by ion implantation, etc., so as to form a source, gate and drain electrode and make the resistance of the wiring 1 on the scanning side lower. Furthermore, the insulating film is formed for passivation if necessary and a contact part 4 in a line shape is formed by etching, etc., and the wiring 5 on the signal side and a display electrode 3 are formed by using a transparent electrode. The consecutive pattern in the line shape is used much in order to easily form the resist when the pattern is formed in a printing method and the constitution of the picture element appropriate for the printing method is obtained.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、液晶等を用いた平面型ディスプレイの構造に
係り、特に薄膜l−ランジスタ等のスイッチ素子を用い
たアクティブマトリクス型液晶ディスプレイの大面積化
あるいは高精細化に好適な構造に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the structure of a flat display using liquid crystal, etc., and particularly to the structure of a large active matrix type liquid crystal display using switching elements such as thin film L-transistors. The present invention relates to a structure suitable for increasing the area or increasing the definition.

〔従来の技術〕[Conventional technology]

ガラス等の透明基板上にスイッチ素子たとえば薄膜トラ
ンジスタやダイオード素子を形成し、液晶等の電気光学
特性を有する物質と積層した。いわゆるアクティブマト
リクスディスプレイは、高精細化や大面積化に適した方
式としてアイ・イー・イー・イー、フロシーディング5
9 (1971年)第1566頁(Proeeedin
gs of IEIEE、 59 。
Switch elements such as thin film transistors and diode elements are formed on a transparent substrate such as glass and laminated with a substance having electro-optic properties such as liquid crystal. The so-called active matrix display is a method suitable for high definition and large area, such as IEE and Floseeding 5.
9 (1971) p. 1566 (Proeeedin
gs of IEEE, 59.

p1566(197]、))に提案されて以来、近年特
に非晶質シリコンを用いた薄膜トランジスタ(a −S
 i T F T ; amorphous 5ili
con Th1n Fi]mTransistor)や
多結晶シリコンを用いたa瞑トランジスタ(p −S 
i T F T ; 2o1yerystalline
Si  TFT)3用いて活発に研究・開発がなされて
いる。この方式は対角寸法が1インチ程度から10〜1
4インチ程度まで小型から大型まで各種のサイズが開発
されているが、さらに大型の仕様のディスプレイが開発
されようとしている。しかしこの製造工程をホトエツチ
ングを含む工程であり、精度良く微細なパターンを製造
することが最大の課題となっている。
In recent years, thin film transistors using amorphous silicon (a-S
i T F T ; amorphous 5ili
con Th1n Fi]mTransistor) and a transistor using polycrystalline silicon (p-S
i T F T ; 2o1yerystalline
Active research and development is being conducted using Si TFTs. This method has diagonal dimensions ranging from about 1 inch to 10 to 1 inch.
Various sizes have been developed, from small to large, up to about 4 inches, and displays with even larger specifications are about to be developed. However, this manufacturing process involves photo-etching, and the biggest challenge is manufacturing fine patterns with high precision.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

このような従来のホトエツチング工程では、ホトマスク
の精度やマスクアライナ−の精度あるいは光の干渉や回
折によるパターンの精度、あるいは基板の伸縮を考慮し
て、最小加工線幅を決定し、それに従ってパターンを作
成する工程を用いている。しかし、基板寸法が大きくな
るに従って、これらの精度の要求仕様が厳しくなるため
、パターンに余裕をもって設計する必要がでてくる。し
かし、従来のホトエツチング工程では、生産性や価格に
限界があり、新たに印刷法によるレジストパターン形成
法が試られている。
In such a conventional photoetching process, the minimum processing line width is determined by taking into account the accuracy of the photomask, the accuracy of the mask aligner, the accuracy of the pattern due to light interference or diffraction, or the expansion and contraction of the substrate, and the pattern is formed accordingly. It uses the process of creating. However, as the substrate size increases, the required specifications for these precisions become stricter, and it becomes necessary to design the pattern with a margin. However, the conventional photoetching process has limitations in productivity and cost, and new methods of forming resist patterns using printing methods are being tried.

印刷法によるパターン形成法は小さな面積ではホトエツ
チング法に比べて精度が劣るが、大面積になるほどスル
ープットが大きいという利点があり、大面積で比較的加
工精度の必要としない場合には有効な方法である。しか
しながら、ディスプレイの表示特性に大きな影響を及ぼ
す画素部の開口率(有効表示電極が画素の面積に占める
割合)を大きくするためには最小加工線幅を小さくする
方が望ましい、また、印刷法の加工の方向性を考えた場
合には、従来のホトエツチング法での設計法の概念を大
きく変える必要がある。
The pattern forming method using the printing method is less accurate than the photoetching method for small areas, but it has the advantage of higher throughput as the area becomes larger, and is an effective method when relatively high processing precision is not required for large areas. be. However, in order to increase the aperture ratio of the pixel portion (the ratio of the effective display electrode to the area of the pixel), which has a large effect on the display characteristics of the display, it is desirable to reduce the minimum processed line width. When considering the direction of processing, it is necessary to significantly change the concept of the design method using the conventional photoetching method.

本発明の目的は印刷法に適した画素の構造を提供するこ
とにある。
An object of the present invention is to provide a pixel structure suitable for printing methods.

〔課題を解決するための手段〕[Means to solve the problem]

上記目的は、印刷法において、原版の構造と原版から加
工基板上にレジストを転写する工程において、加工精度
を大幅に緩める構造を用いることにより達成される。
The above object is achieved by using a structure in the printing method that greatly reduces processing precision in the structure of the original and in the step of transferring resist from the original onto the processed substrate.

〔作用〕[Effect]

印刷法においては、ドツト状のパターン、あるいは微小
な島状のパターンは形成することが困難で、直線や曲線
のような連続パターンの方が加工が容易である。この連
続パターンを用いることにより、大面積化に対し適応し
た画素構成が得られる。
In printing methods, it is difficult to form dot-like patterns or minute island-like patterns, and continuous patterns such as straight lines and curves are easier to process. By using this continuous pattern, a pixel configuration suitable for increasing the area can be obtained.

〔実施例〕〔Example〕

以下、本発明の一実施例を第1図により説明する。第1
図は一画素の構成を示したものであり。
An embodiment of the present invention will be described below with reference to FIG. 1st
The figure shows the configuration of one pixel.

信号側配線(ドレインパスライン)5と走査側配線(ゲ
ートパスライン)1の交点にTFT素子と。
A TFT element is placed at the intersection of the signal side wiring (drain pass line) 5 and the scanning side wiring (gate pass line) 1.

TFT素子のソース電極に接続された透明電極材料で形
成された画素電極3からなる。この形成法としては、ま
ずガラス基板上にTFT素子の活性層と信号側配線の一
部を兼用した薄膜半導体層2を形成し、レジスト塗布後
エツチングすることにより、島状に形成する。次に、ゲ
ート絶縁膜を基板上全面に形成する。さらに走査側配線
用薄膜を形成後、第1図のように直線状にエツチング加
工し、イオン打込み等によりドーピングしてソース。
It consists of a pixel electrode 3 made of a transparent electrode material connected to the source electrode of the TFT element. As for this formation method, first, a thin film semiconductor layer 2 serving as the active layer of the TFT element and part of the signal side wiring is formed on a glass substrate, and a resist is applied and then etched to form an island shape. Next, a gate insulating film is formed over the entire surface of the substrate. Furthermore, after forming a thin film for scanning side wiring, it is etched into a linear shape as shown in Figure 1, and doped by ion implantation etc. to form a source.

ゲート、ドレイン電極を形成すると同時に走査側配線の
低抵抗化を行う。さらに、必要に応じて絶縁膜をパッシ
ベーション用に形成し、直線状のコンタクト部4をエツ
チング等により形成し、信号側配線59表示電極3を透
明電極を用いて形成する。
At the same time as forming the gate and drain electrodes, the resistance of the scanning side wiring is reduced. Further, if necessary, an insulating film is formed for passivation, linear contact portions 4 are formed by etching, etc., and signal side wiring 59 and display electrode 3 are formed using transparent electrodes.

このとき、信号側配線5と表示電極3は別な材料を用い
て、別々に形成しても良い。
At this time, the signal side wiring 5 and the display electrode 3 may be formed separately using different materials.

上記の構成は、印刷法でパターンを形成するときに、レ
ジストの形成が容易なように直線状の連続パターンを多
用しているのが特徴である。
The above configuration is characterized in that when forming a pattern by a printing method, linear continuous patterns are frequently used so that resist formation is easy.

第2図(a)〜(d)に印刷法に適したパターンを示す
、第2図(a)は印刷方向に直線状に形成したパターン
であり、特に印刷方向のずれに対して許容差が大きくで
きる。第2図(b)〜(d)は印刷方向に対して、印刷
方向と垂直方向においてどの位置でも必ずパターンが基
板上に存在するようにしたものである。このようにする
ことにより、原版上にパターンが存在することによる凹
凸で、パターン印刷時に原版と基板との間隔が一定に保
たれ、精度良いパターン形成が可能となる。
Figures 2(a) to 2(d) show patterns suitable for the printing method. Figure 2(a) is a pattern formed linearly in the printing direction, and has a particular tolerance for misalignment in the printing direction. You can make it bigger. In FIGS. 2(b) to 2(d), the pattern is always present on the substrate at any position in the direction perpendicular to the printing direction. By doing so, the spacing between the original plate and the substrate is kept constant during pattern printing due to the unevenness caused by the presence of the pattern on the original plate, making it possible to form a pattern with high precision.

第3図に本発明の実施例を用いた印刷法の概念を示す、
ガラス基板6の上に、ロール状の原版7にレジスト8を
形成し1回転しながらパターンを形成する方法である。
FIG. 3 shows the concept of a printing method using an embodiment of the present invention.
In this method, a resist 8 is formed on a roll-shaped original 7 on a glass substrate 6, and a pattern is formed while making one rotation.

第1図で示したパターンをこの方法で形成するためには
基板の挿入方向をパターンの方向に合わせて90°回転
すれば良い。
In order to form the pattern shown in FIG. 1 using this method, it is sufficient to rotate the insertion direction of the substrate by 90 degrees to match the direction of the pattern.

第3図では、原版をローラ状のものとしたが、平面状の
原版であっても、基板上に原版を置く場合に精度が良い
方向を考慮し、印刷方向を決めることにより1本発明の
実施例を適用することができることはいうまでもない。
In Fig. 3, the original is in the form of a roller, but even if the original is flat, the present invention can be achieved by determining the printing direction by considering the direction with good accuracy when placing the original on the substrate. It goes without saying that the embodiments can be applied.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、印刷法によりレジストパターンを形成
するときに精度良く形成できるため、大面積の基板を用
いたディスプレイ等の加工が容易に行えるという効果が
ある。
According to the present invention, since a resist pattern can be formed with high precision by a printing method, it is possible to easily process a display or the like using a large-area substrate.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例の画素部の平面端造図、第2
図は本発明に適したレジス1−のパターン図、第3図は
、印刷法の概念図である。 1・・・走査側配線、3・・・表示電極、5・・・信号
側配線。 S−−一信号1則叡涛策
FIG. 1 is a plan view of a pixel portion according to an embodiment of the present invention, and FIG.
The figure is a pattern diagram of a resistor 1 suitable for the present invention, and FIG. 3 is a conceptual diagram of a printing method. 1...Scanning side wiring, 3...Display electrode, 5...Signal side wiring. S--One signal, one rule, countermeasure

Claims (1)

【特許請求の範囲】[Claims] 1、ガラス基板上にTFTと液晶とを積層してなるアク
ティブマトリクス液晶ディスプレイにおいて、配線、コ
ンタクトホール、電極を少なくとも2つ以上の複数画素
以上にわたる連続パターンとして形成したことを特徴と
する表示パネル。
1. A display panel in which wiring, contact holes, and electrodes are formed as a continuous pattern spanning at least two or more pixels in an active matrix liquid crystal display formed by laminating TFTs and liquid crystals on a glass substrate.
JP1043003A 1989-02-27 1989-02-27 Display panel Pending JPH02223923A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1043003A JPH02223923A (en) 1989-02-27 1989-02-27 Display panel

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1043003A JPH02223923A (en) 1989-02-27 1989-02-27 Display panel

Publications (1)

Publication Number Publication Date
JPH02223923A true JPH02223923A (en) 1990-09-06

Family

ID=12651822

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1043003A Pending JPH02223923A (en) 1989-02-27 1989-02-27 Display panel

Country Status (1)

Country Link
JP (1) JPH02223923A (en)

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