JPH02223165A - Integrated circuit package and connector - Google Patents

Abstract

PURPOSE:To decrease electric contacts of the whole connector, improve reliability, reduce the number of components, and improve the efficiency of the assembling work by providing a press terminal and contacts on a lead frame itself. CONSTITUTION:A press terminal 81 to be pressure-welded with electric wires 61-66 and many contacts 82 are provided on a lead frame itself of an integrated circuit package 80. The electric wires 61-66 constituting a bus line 2 are pressure-welded to the pressure terminal 81, many contacts 82 are directly used as contacts of a connector 3, thereby electric contacts between pins of the IC package 80 and the terminal of the connector 3 storing IC are eliminated. The reliability of the connector 3 incorporating the IC package 80 is improved. The lead frame itself has the pressure terminal 81 and the contacts 82, thus the number of components is reduced, the efficiency of the assembling work is improved, and the cost of the whole connector 3 can be lowered.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention relates to an integrated circuit package equipped with an integrated circuit chip configured with a serial-parallel signal conversion circuit that performs signal conversion between a serial signal and a parallel signal. , and a connector including the integrated circuit package.

(Prior Art) As a means for electrically connecting electronic circuits, connectors are used for convenience of connection and disconnection. In recent years, microcomputers and the like have come to control an extremely large number of devices, and the number of wires has accordingly increased. As the number of wires increases, it causes incorrect wiring and increases in cost, so efforts have been made to reduce the number of wires. As one way to reduce the number of wires, an integrated circuit (hereinafter referred to as an IC) having the above-mentioned serial-parallel signal conversion circuit is built into the connector, and a time-series control signal output from a controller such as a microcomputer, etc. The above I built into the connector
C converts it into a parallel signal and supplies the control signal corresponding to each controlled device to the six controlled devices, and the signal detected by each sensor is converted into a time series signal by the IC and transmits it to the controller. It has been considered (Japanese Patent Publication No. 82-19020, Japanese Patent Application No. 83-284102, etc.).

By incorporating the above-mentioned IC in the connector and performing serial-parallel conversion of the signals, it is sufficient to transmit time-series signals from the controller, so the number of wires can be reduced.

FIG. 6 is a diagram showing a control system configured as described above.

A cable (pass line) 2 for inputting and outputting time-series signals is wired from the controller 1, and a number of connectors 3 containing the above-mentioned ICs are disposed in the middle of the pass line 2. The pass line 2 itself also branches at position rXL8. Each connector 3 connects a motor 4, which is each controlled device. A signal is sent to the switch 5, the lamp 6, etc., and the detection signal obtained by the sensor 7 is sent to the corresponding connector 3. It is transmitted to the controller 1 via the pass line 2.

In addition, in FIG. 6, each connector 3 is connected to a controlled device 4.
. You can. Furthermore, the path line 2 is for transmitting control signals, and power for the high power consuming terminal devices such as the motor 4 and the lamp 6 is separately supplied from a power supply source not shown in FIG. do.

By using a connector incorporating the above-mentioned IC in this way, the path line 2 that is wired across a large number of terminal devices only needs to transmit and receive time-series signals, so the overall number of wires can be reduced and errors can be avoided. Wiring can be reduced and costs can be reduced.

(Problem 8 to be Solved by the Invention) Since the connector incorporates the IC, for example, between the pass line 2 and the pass line terminal of the connector, Connected to a pass line pin of an IC package built into the connector, between a terminal device pin of the IC package and a terminal device terminal of the connector, and between a terminal device terminal of the connector and the connector. Since the connector has a large number of electrical contacts, such as with terminals of other connectors, there is a high possibility that poor contact will occur, and therefore there is a problem in that the reliability of the connector decreases. Furthermore, in order to avoid this problem, it may be possible to solder the pins of the IC package to the corresponding terminals of the connector, but soldering increases the number of steps and increases costs. Furthermore, soldering may cause defects, and is not sufficient from the viewpoint of improving reliability.

In view of the above circumstances, the present invention makes it possible to reduce the number of electrical contacts in the entire connector, thereby improving reliability, and further reducing the number of parts and improving the efficiency of assembly work, making it suitable for assembling a low-cost connector. Its purpose is to provide IC (integrated circuit) packages.

In addition, connectors with waterproof structures have been used in places where there is a possibility of coming into contact with water droplets, etc., but if an IC is built into the connector, the IC is vulnerable to humidity. , its waterproofing is a particular problem.

Therefore, the present invention improves reliability, reduces the number of parts, and improves the efficiency of assembly work by incorporating the above-mentioned IC package of the present invention, and at the same time, the built-in IC package can be easily and completely removed from water with a few manufacturing steps. One of the objectives is to provide a connector with a waterproof structure that protects it from damage.

(Means for Solving the Problems) An integrated circuit package of the present invention includes an integrated circuit chip that performs serial-to-parallel conversion of signals, and is equipped with a time-series signal pad and a large number of parallel signal pads, and an electric wire is pressure-welded. The lead frame includes a pressure contact terminal connected to the time-series signal pad, and a large number of contacts each connected to the plurality of parallel signal pads, and the pressure contact terminal and the contact are exposed. The integrated circuit chip is encapsulated in resin.

Furthermore, the connector of the present invention is a connector including the integrated circuit package, the contact having a hole into which the contact is inserted, and which is coupled to another connector by being inserted into the hole. a housing provided with the integrated circuit package and having a section formed therein; an electric wire press-connected to the pressure contact terminal; and a lid that is placed over the housing so as to cover the pressure contact terminal and the integrated circuit chip; An internal space surrounding the press-contact terminal and the integrated circuit chip, which is formed by the press-contact terminal and the housing, is filled with resin.

(Function) In the integrated circuit package (IC package) of the present invention, the lead frame itself is equipped with a pressure contact terminal to which an electric wire is pressure-connected and a large number of contacts. By pressure-welding the IC and using the above-mentioned large number of contacts directly as contacts of the connector, there is no electrical contact between the pins of the IC package and the terminals of the connector containing the IC.
The reliability of the connector incorporating the package is improved.

Furthermore, since the lead frame itself has the pressure contact terminals and contacts as described above, the number of parts can be reduced, the assembly work can be made more efficient, and the cost of the connector as a whole can be lowered.

Further, the integrated circuit package of the present invention can already serve as a connector by itself without being built into a connector housing, and can also be used for 1yia pressure contact or connection with other connectors. In this case, of course, the number of contacts is smaller than the conventional 10-incorporated connector.

Further, the connector of the present invention uses the contacts of the above-mentioned integrated circuit package directly as contacts of the connector,
Further, since the internal space surrounding the parts other than the contacts of the integrated circuit package formed by the lid and the housing is filled with resin, the IC can be completely protected from water droplets. Moreover, this waterproofing can be easily performed. Therefore, an IC built-in connector is constructed that is low in cost and has a waterproof structure.

(Example) Examples of the present invention will be described in detail below with reference to the drawings.

FIG. 7 is a circuit block diagram showing an example of the structure of an internal circuit of an integrated circuit chip constituting the integrated circuit package of the present invention.

This circuit 10 is provided with a power supply connection pad 11, a grounding pad 12, and the following pads 13 to 30 for connection with external circuits.

The two clock input pads 13 and 14 are connected to a control microcomputer (not shown), and receive two clocks CLK+ and CLK- output from the computer and having phases different by 1800 degrees from each other.

The time-series signal input/output pad 15 is connected to the microcomputer, and is connected to the two
A time series signal synchronized with the two clocks CLK+ and CLK- is output and input to this circuit 10 from the pad 15, and a time series signal output from this circuit 10 is transmitted via the pad 15 to the microcomputer. transmitted to. The pad 15 is connected to Vee via a resistor R1.

Moreover, this circuit IO has six address input pads 16 to 16.
21, and therefore it is possible to identify 26 (64) circuits that are the same as this circuit IO.

Each of the address input pads 16 to 21 is either grounded (L level) or left unconnected (open state). Each address input pad 16 to 21 is a circuit l.
Since the pad is connected to the power supply ■ee through the resistor R2 inside the pad O, the pad in the oven state is held at the H level. Additionally, the address of the circuit 10 is set by the combination of H's.

An oscillation signal of 5 K11z is output from the oscillation signal output pad 22, and is supplied to a charge pump circuit (not shown) that generates a voltage higher than the power supply voltage Vcc.

The parallel signal input/output pads 23 to 30 are connected to each terminal device (for example, the lamp described above using FIG. 6).

motors, various sensors, etc.), and sends signals to each terminal device or receives signals from each terminal device. Each pad 23-30 is the pad 23-30.
It is connected to Vcc via each resistor R3 provided correspondingly. Note that, as will be described later, this circuit IO is bidirectional so that it can output signals as well as input signals via each of the parallel signal input/output pads 23 to 30. It is configured. However, each of the parallel signal input/output pads 23 to 30 is normally semi-fixed while being incorporated into a connector to be described later and used, for example, pads 23 to 2B are for parallel signal output,
Pads 29 to 30 are used as either output or input, such as for inputting parallel signals.

Two clocks CLK+ and CLK-, which are sent out from the control microcomputer and inputted from the two clock input pads 13 and 14, are 180° different in phase from each other.
is input to the line receiver 31.

The line receiver 31 acts as a comparator, and from the line receiver 31 there is a signal that is the same as CLK+ (i.e. CLK+).
A clock CLK (which has a phase difference of 180@ from LK-) is output. In this way, two clocks CLK+, CLK
The clock CLK sent out from the control computer by inputting - and passing it through the line receiver 31.
Even if noise is mixed into CLK+ and CLK- and input to this circuit, the clock CLK output from the line receiver 13
impact on the environment is largely prevented.

The clock CLK output from the line receiver 31 is
It is input to a 6-bit address counter 32, a 4-bit window counter 33, a clock sense circuit 34, and a gate circuit 35.

The clock sense circuit 34 provides a clock CL to the circuit 34.
While K is being input, a continuous H level signal is output from the output terminal O8C, and when the clock CLK is stopped, an L level signal is output. The oscillator 3B has its output connected to the oscillation signal output pad 22, and oscillates at 5 KHz while the clock sense circuit 34 outputs an H level signal to output the oscillation signal to the pad 22. . Further, when an L level signal is transmitted from the clock sense circuit 34, the oscillator 3B stops its oscillation.

Further, the output terminal RES of the clock sense circuit 34 is connected to the CLR terminals of the two counters 32 and 33.
While the clock CLK is input to the clock sense circuit 34, the two counters 32 and 33
When the clock CLK is counted and the input of the clock CLK to the clock sense circuit 34 is stopped, the two counters 3
The two counters 32 are cleared so that the counters 2 and 33 are cleared.
．． 33 is controlled by a clock sense circuit 34.

The two counters 32.83 together constitute an IO bit synchronous binary counter, with the 4-bit window counter 33 receiving the lower 4 bits and the 6-bit address counter 32 receiving the upper 6 bits. 32,
33, the symbol A shown in the figure is the least significant bit, B
, C, . . . represent the parallel output terminals of the upper bits in this order.

Parallel output terminals A-F of the address counter 32 are connected to an address comparison circuit 37. The address counter 32 is also connected to the address input pads 16 to 21, and a unique address set externally to this circuit IO is input. The address comparison circuit 37 compares the externally set address and the count value obtained by counting the clock CLK, and when the comparison results match, sends an H level signal to the two 3-bit to 8-bit decoders 38 and 39. Output to C81 terminal. Further, the C82 terminal of the 3-bit to 8-bit decoder 38 is connected to the most significant bit output terminal of the 4-bit ranid counter 33 via the inverter 40, and the C82 terminal of the 3-bit to 8-bit decoder 38 is
The C82 terminal is directly connected to the output terminal. Therefore, after an H level signal is output from the address comparison circuit 37 to the C81 terminal, an H level signal is output to the C82 terminal of the decoder 38 and an L level signal is output to the C82 terminal of the decoder 39 while the 8-bit clock CLK is being input.
A level signal is output, which causes the decoder 38 to operate and decoder 39 to be inhibited from operating. During the subsequent 8 bits, an L level signal is output to the CS terminal of the decoder 38 and the C8 terminal of the decoder 39
An H level signal is output to the second terminal, which activates the decoder 39 and prohibits the operation of the decoder 38. In addition, three input terminals A of each decoder 38 and 39,
B and C are the lower 3 of the window counter 33, respectively.
It is connected to the parallel output terminals A, B, and C of the bit.

Decoder 38 has two terminals cs1. An H level signal is input to cs2, and three terminals A and B.

When a parallel clock signal is input to C, H level signals are sequentially output to eight output lines connected to the gate circuit 35. This H level signal is input to an 8-bit command latch circuit 41 via a gate circuit 35. The command latch circuit 41 is basically composed of eight D-type flip-flop circuits, and includes a gate circuit 35.
The eight output lines are connected to the clock input terminals of each flip-flop circuit. From the control computer (not shown), time series signal input/output pad 1
The time series signal (command signal) inputted via the inverter buffer circuit 42 is inputted to the D input terminal of the command latch circuit 41 (the D input terminal of each flip-flop circuit). This command signal is a signal synchronized with the clock CLK, and each command signal is stored (latched) in the corresponding flip-flop circuit at the timing when the H level signal is sent from the gate circuit 35.

Bidirectional buffer circuit 43 of the command latch circuit 41
The eight output lines connected to the command latch circuit 4
The latched command signal is connected to the Q terminal of each flip-flop circuit 1, and the latched command signal is connected to the corresponding parallel signal input/output pad 23 via the output oven collector buffer circuit 43a of the bidirectional buffer circuit 43. ~30 is output. Also, the clear terminal CLR of the command latch circuit 41 (clear terminal of each flip-flop circuit)
is connected to the power supply Vec via a resistor R4 and grounded via a capacitor C. This resistance R
4 and capacitor C clear the command latch circuit 41 (each type flip-flop circuit) when the power is turned on.

After the command signal is latched and output as described above, an L level signal is input to the terminal C82 of the decoder 38, and an H level signal is input to the terminal C82 of the decoder 39, so that the decoder 39 is activated. do. Three terminals A, B of the decoder 39.

When parallel clocks are input to C, H level signals are sequentially output to eight output lines connected to eight input terminals of the gate circuit 44. In addition, gate circuit 44 (; indicates that input signals from parallel input/output signal pads 23 to 30 are inputted via input buffer circuit 43b of bidirectional buffer circuit 43. From decoder 39 to gate circuit 44 in sequence. Each parallel signal input/output pad 23 to 30 and the bidirectional buffer circuit 43 are connected at the timing when an H level signal is input.
The signals inputted to the gate circuit 44 via the gate circuit 44 are sequentially outputted from the gate circuit 44, and are sent to the OR circuit 45. It is transmitted as a response signal to the control microcomputer connected to the pad 15 via the oven collector buffer circuit 4B and further via the time-series signal input/output pad 15.

FIG. 8 is a timing chart showing the operation of the circuit IO shown in FIG. Here, it is assumed that all six address setting pads IB-21 are grounded (the address of the circuit IO is ooooooo). Also here,
Parallel signal input/output pads 23 to 30 (
R/Co-R/Cr), R/C0~R/
C, is used for parallel signal output (for command),
R/C, ~R/C, is for parallel signal input (for response)
It is assumed that it is used as

When two clocks CLK+ and CLK- are input via two clock input pads ta and t4, the clock sense circuit 34 releases the clearing of the two counters 32 and 33, and the two counters 32 and 33 Counting of the clock CLK is started.

In addition, here, since the address of the circuit IO is set to ooooooo, two 3
An H level signal is immediately sent to the PITTO 8-bit decoders 38 and 39. The command enable signal represents the signal at terminal C82 of decoder 38, and the response enable signal represents the signal at terminal C82 of decoder 39.

The command clock signal is a signal generated by inverting the clock CLK within the gate circuit 35, and the command signal is latched at the rise of each pulse of the command clock signal.

R/Co ” R/Ct represents parallel signals output via parallel signal input/output pads 23 to 27. R/C, to R/C7 represent parallel signal input/output pads 2
These are parallel signals input via signals 8 to 30, which are ON (H level) and 0FF (L level), respectively.

This is an ON (H level) signal. The DATA signal represents a time-series signal that is input and output via the time-series signal input/output pad 15, and the command R/Co"R/Ca is a valid signal, and is outputted at each timing shown in the figure.
Latched N or OFF, parallel signal input/output pad 2
Output from 3 to 27.

Off states R/C5 to R/C7 are not used as commands and DATA is held at H level. Monitor R/
Co” R/Ca is command R/Co-R/C4
is repeated, and the command signal output from the control computer is in turn a response signal (a time-series signal sent from this circuit IO to the above computer).
This allows the computer to monitor whether the command signal was correctly sent to the circuit IO. Responses R/C, to R/C, represent signals input from parallel signal input/output pads 28 to 30. R/C5”-ON, R/C, m0FF
.

R/Cy-ON+ corresponds to L level, H level, and L level signals, respectively. As described above, when 16 pulses of the clock CLK are input, the parallel outputs A-F of the address counter 32 become inconsistent with the externally set address (000000), and the state of the latch of this circuit 10 is maintained. The next circuit (address ooo
The same operation as above is performed for the circuit (root circuit).

In this way, when the above circuit IO is used, any pad of the parallel signal input/output pads 23 to 30 is used for parallel signal output, and the other pads are used for parallel signal input, and input/output is performed from the time series signal input/output pad 15. It is possible to exchange signals with the time series signals that are displayed.

In addition, since the command signal inputted from the time-series signal input/output pad 15 is output from the pad 15 as a response signal in return, the command signal is input to the circuit 10.
It is possible to monitor whether or not the information has been received accurately.

In addition, this circuit IO has eight parallel signal input/output pads 2.
Any one of 3 to 30 can be selected manually or as an output, so if, for example, 5 outputs and 2 inputs are required, for example, 4 out of 8 bads are for output and 4 bads are for output. When using an integrated circuit chip equipped with a fixed circuit for input, two such integrated circuit chips are required, but if an integrated circuit chip equipped with the circuit shown in FIG. 7 is used, only one is required. become.

FIG. 9 is a circuit block diagram showing another example of the internal circuit configuration of the integrated circuit chip constituting the integrated circuit package of the present invention. Elements that are the same as those in the circuit block diagram shown in FIG. 7 are given the same numbers, and explanations thereof will be omitted.

The terminal C82 of the decoder 38 of this circuit 10' was connected to the output terminal of the window counter 33 via the inverter circuit 40 in the circuit 10 of FIG. It is directly connected to the output terminal of the window counter 33. In addition, the input terminal A of the decoder 38 was directly connected to the output terminal A of the ranid counter 33 in the circuit shown in FIG.
O' is connected via an inverter circuit 40'. As a result, the order of signals input and output via the time-series signal input/output pad 5 is different from the circuit shown in FIG.

FIG. 1O is a timing chart showing the time series signal DATA input/output via the time series signal input/output pad 15 of the circuit shown in FIG.

The DATA timing chart shown in Figure 8 is
The order of the cloak signal and response signal is different, command signal R/Co, response signal R/Con...
. . . , the corresponding command signals and response signals are adjacent to each other.

By the way, among the command signals, the invalid signal (off state)
(see FIG. 8) is fixed at H level on DATA. Therefore, in each corresponding command signal/response signal pair in FIG. 10, there cannot be a combination in which the command signal is at L level and the response signal is at H level.

Therefore, by monitoring the combination of L level and H level, errors in signal exchange between the control computer and the circuit 10' can be easily and quickly discovered. On the other hand, in the case of the circuit 10 shown in FIG. 7, it is necessary to store the command signal and calculate whether the two match when receiving or receiving the response signal.

Although the above two examples are shown here as the internal circuit configuration of the integrated circuit chip, these are only examples, and the internal circuit of the integrated circuit chip constituting the integrated circuit package of the present invention may be other than the above two examples. It can also be configured in various ways.

FIG. 11 is a diagram showing a connection system with the outside of the integrated circuit chip 50 having the circuit configuration shown in FIG. 7 or FIG. 9. This integrated circuit 50 is built into the connector 100, as will be described later.

6 extending from a control microcomputer (not shown)
A cable 60 (details will be described later) consisting of electric wires 61 to 6B is connected to a large number of integrated circuit chips 50. The electric wire 61 is a shielding ground wire that is in contact with a shield wire that surrounds the six electric wires 61 to 66. The electric wire 62 is a data line for transmitting and receiving time-series signals between the control computer and each integrated circuit chip 50, and is connected to the DATA terminal (time-series signal input/output pad 15) of the integrated circuit chip 50. . Wires 63 and 84 are two clocks CLK- output from the control computer,
CLK+ clock line for transmission, integrated circuit chip 5
0 to two clock input terminals CLK- and CLK+ (clock input pads 14 and 13).

The electric wire 65 connects the power terminal Vcc of the multiple integrated circuit chips 50.
(power supply pad 11).

The power supply terminal vCC of the integrated circuit chip 50 is connected to the terminal Vcc.
In the vicinity of capacitor C! is grounded through. The electric wire 66 is a ground line that is electrically separate from the shielding ground line and connects the mutual GND terminals (grounding pads 12) of the multiple integrated circuit chips 50 and the ground lines of other attached circuits. . Address input terminal Ao
-A5 (address input pads 16 to 21) are grounded, but are disconnected from the ground as necessary when setting an address.

The 5KHz output terminal (pad 22 for oscillation signal output) and the eight terminals of R/Co" R/CT (pads 23 to 30 for parallel signal input/output) are connected to the ground line 66, power line B5, and shield ground. It is connected to the contact portion 103 of the connector 100 together with the wire 61, and is coupled to an external circuit via another connector (not shown) coupled to the connector 100. 50 is a diagram showing an example of a lead frame to which the lead frame 50 is die-bonded and further wire-bonded. The lead frame 70 is formed by punching out a metal plate and having the shape shown with diagonal lines in the figure. The lead frame 70 further extends upward, downward, and to the right in the figure, and is bent as described below.

Regarding the correspondence with each terminal of the integrated circuit chip 50, each terminal of the lead frame 70 is given the same symbol as each terminal in FIG. 11, and a description thereof will be omitted.

An integrated circuit chip 50 is mounted on a die at a central location 71 as shown in the figure.
It is bonded and wire-bonded to each terminal of the lead frame 70. A terminal 72 of the lead frame 70 that is not wire-bonded is a shield ground terminal connected to the shield ground line 61 shown in FIG. Also, the R/Go terminal is connected to the vcc terminal, which will be connected to the address input terminals A0 to A0 in a later process.
When setting an address by cutting the connection between A5 and the GND terminal as necessary, the connection is cut at position 73. After the integrated circuit chip 50 is wire-bonded, the inside of the region 74 surrounded by the broken line is sealed with resin, leaving an open lower portion 5.78. The open lower part 5 is an opening for setting an address, and the open lower part B is an opening for attaching the capacitor C1 shown in FIG. 11.

After the integrated circuit chip 50 is encapsulated with resin in this manner, the lead frame is cut along the many broken lines 77 shown in the figure to separate the terminals from each other, and each terminal of the lead frame is bent. , the integrated circuit package is completed.

FIG. 13 is a perspective view of the external appearance of one embodiment of the integrated circuit package of the present invention.

After the integrated circuit chip is encapsulated in resin as described above,
Each terminal of the lead frame is bent as shown in FIG. Note that this bending process may be performed before the integrated circuit chip 50 is encapsulated in resin.

Six terminals (shield ground, DATA, CLK-, CLK+, Vcc) extend to the right in FIG.

GND) is a terminal connected to each of the electric wires 61 to 66 of the cable 60 as shown in FIG. 11, and is processed into the shape of the pressure contact terminal 81 shown in FIG. 13. Opening 8 of this pressure contact terminal 81
By press-fitting an electric wire into 1a from above in the figure, the insulating inner sheath of the electric wire is cut, the core wire is electrically connected to the pressure contact terminal 81, and the wire is held by the pressure contact terminal 81.

As shown in FIG. 13, the 12 terminals extending vertically in FIG. 12 can be used directly as contacts of the connector when this integrated circuit package 80 is built into the connector as described later. Then, it is processed into the shape of the contact 82.

As described above, the open lower 5 is an address setting opening, and by cutting the pins exposed from the lower 5 as necessary, the address of this integrated circuit package is set. At this time, the R/Co terminal and Vc shown in FIG.
The connection with the c terminal is also disconnected.

During this time, the lower portion 5 is filled with resin when the integrated circuit package 80 is assembled into the connector, as will be described later.

As described above, the opening arrow is an opening for attaching a capacitor, and the chip capacitor 83 is disposed therein.

As shown in the embodiment of FIG. 13, the integrated circuit separate cage of the present invention has a lead frame itself equipped with a pressure contact terminal to which an electric wire is pressure-connected and a large number of contacts, so that it is already connected to a connector. It can also play the role of When this integrated circuit package is further built into a housing and assembled as a connector, the terminals on the lead frame of this integrated circuit package can be used as pressure contact terminals and contacts, so there is no need to increase the number of contacts. A connector can be realized.

In the embodiment of the integrated circuit package shown in FIGS. 12 and 13, the address setting terminals Ao-A are connected to the GND terminal through the lead frame, and the connection is disconnected as necessary. However, it is also possible to increase the number of contacts formed by bending the lead frame and set them arbitrarily using an external circuit. In this case, although the number of contacts increases, the integrated circuit package itself does not have a unique address, which has the effect that the integrated circuit package can be shared.

Next, the structure of the cable 60 shown in FIG. 11 and press-connected to the pressure contact terminal 81 of FIG. 13 will be described.

FIG. 14 is a sectional view showing a cable including an electric wire that is press-contacted to the press-contact terminal of the integrated circuit package shown in FIG. 13.

In the cable 60, six core wires 61 to 66 are arranged parallel to each other and at equal intervals in a plane. These core wires 61-6
Other core wires 62 to 6B excluding core wire 61 at one end of B
is covered with an insulating inner jacket 67. The inner sheath 67 also extends between each core wire so that the core wires are maintained at equal intervals from each other. Further, this inner sheath 67 extends to the position of the core wires 61, and the core wires 01 are also arranged at equal intervals. These core wires 81 to 66 and inner sheath 67 are covered with a shielding aluminum coating film 68. The core wire 61 is in contact with the film 08 along its extending direction, and the core wire 61 is also maintained at the same potential as the film 68.

The periphery of the film 68 is covered with an insulating jacket 69.

FIGS. 15A and 15B are a side sectional view and a perspective view showing the inside of another embodiment of the cable, respectively.

This cable 90 has a core wire 91, an insulating inner sheath 92, and two
93.94 pieces of aluminum coating film,
It is composed of an outer cover 95. In addition, perforations 93a and 94a are provided in the two films 93 and 94 at predetermined intervals in the length direction of the cable 90, and the perforations in the two films 93 and 94 are arranged so that they do not overlap each other. It's a little off.

When shielding is performed using a single film 68 as shown in FIG. 14, if perforations are provided in this film 68, noise will easily enter through the perforations in a high-noise environment. By stacking two films and shifting the perforation positions from each other, noise can be reliably prevented from entering the film. By peeling off the film 93, 94 at that portion, the electric wire (core wire and inner sheath) of any part of this cable 90 can be exposed.

FIG. 1A is a side sectional view of one embodiment of the connector of the present invention, and FIG. 1B is a front sectional view taken along line xx' in FIG. 1A.

The housing lot of this connector 100 is provided with a hole 102 into which the contact 82 of the integrated circuit package 80 shown in FIG. 13 is inserted. The contacts 82 of the integrated circuit package 80 are inserted into the holes 102 to form contact portions 103 that are coupled to other connectors. A cable 60 shown in FIG. 14 is press-fitted into a press-contact terminal 81 of an integrated circuit package 80 after its jacket 69 and film 68 have been peeled off. Also, this connector 10
0 includes an integrated circuit package 80 within housing 101.
1E104 is provided, which is covered with a crown. Further, in this embodiment, a stuffer 10B for press-fitting the shield plate 105 and the cable 60 into the pressure contact terminal 81 is provided inside the lid 104. By capping M2O3, the stuffer 108 causes the cable 60 to
is more reliably press-fitted into the pressure contact terminal 81. Adhesion 104
A portion thereof is configured to fit into the hook 101a of the housing 101 so that it does not come off.

As shown in FIG. 1B, this shield plate 105 is partially bent and extends to the insulation displacement terminal 81 into which the electric wire 61 (see FIG. 14) that is not covered by the inner sheath 67 of the cable 60 is press-fitted. A piece 105a is formed, and this wire contact piece 105a connects the wire 61 and the shield plate 10.
5 are electrically connected. Further, as described above, the electric wire 61 is in electrical contact with the shielding film 68 of the cable 60, so that the shield of the cable 60 and the shield of the connector 100 are maintained at the same potential.

Further, a portion of the shield plate 105 is bent to form a contact piece 105b that contacts the inner wall of another connector 200 that is coupled to this connector 100. The raised portion of the inner wall of the ground connector in FIG. 1B is metal plated.

Therefore, the shield plate 10
5 and the inner wall of the ground connector 200 are electrically connected, and by coupling both connectors 100, 200, the interior surrounded by these connectors 100, 200 can be more completely shielded.

M2O3 of the connector 100 and the shield plate 105 inside thereof have openings 104c and 10 for injecting resin.
5C is provided, and the housing 1 is
After the contacts 82 of the integrated circuit package 80 are inserted into the holes 102 of 01, the wires of the cable 60 are pressure-connected to the pressure contact terminals 81, and the lid 104 is covered, the integrated circuit package 80 formed by the housing 101 and the lid 104 is removed. An internal space 106 surrounding the is filled with resin. By filling the internal space 10B with resin in this way, the integrated circuit package 80 can be made easily and completely waterproof.

Since the contact part 103 is connected to another connector 200 as shown in FIG. 1B, it is difficult for water droplets to enter from this part, but in order to make this part more completely waterproof,
A ring-shaped waterproof seal ring 1 is attached to the contact portion 103.
07 is fitted, a seal ring presser 10g is fitted from below, and the hook 10 of the nose ring 101 is inserted.
1b and is prevented from coming off.

FIG. 2 is a schematic perspective view schematically showing the structure of the contact portion 103 shown in FIGS. 1A and 1B.

A hook 101b is provided inside the opening 101c forming the contact portion 103 of the housing 101.

The waterproof seal ring 107 is inserted into the opening 101C, and then the seal ring presser 108 is inserted. A groove 108a is provided in the seal ring presser 10g, and the groove 108a engages with the hook 1otb to prevent the seal ring presser 108 and the seal ring 107 from falling off.

This contact portion 103 is provided with two openings 101c (the negative one is not shown). of housing lO1,
A connecting portion 101d for connecting these two openings 101c is provided in a portion forming these two openings 101c. This connection part 1
By changing the position of 01d, incorrect fitting due to a mismatch between this connector and another connector to be coupled to this connector can be prevented.

FIG. 3 is a perspective view of another seal ring holder that can be used in place of the seal ring holder 108 of FIG. 2.

This seal ring presser 108' has a groove 10 that fits with the hook 101b of the seal ring presser 108 shown in FIG.
In addition to the groove 108a' corresponding to the connector 8a, a groove iogb' for preventing incorrect fitting with other connectors is provided. This groove 1
By changing the position of 08b', mismatching of this connector with another connector to be coupled to this connector can be prevented. This groove 108b' can be used in place of or in conjunction with the connecting portion 101d shown in FIG.

Figures 4A to 4C are a perspective view of the main parts before assembly, an external perspective view after assembly, and a sectional view taken along Y-Y' in Figure 4B, respectively, showing an embodiment of the cable branching connector. It is. This connector is used, for example, at the branch point 8 of the path line (cable) 2 in FIG. 6.

Of the signal transmission system connected to the control microcomputer (not shown), the connectors connecting the pass line (cable) and each terminal device are one embodiment of the connector of the present invention, as shown in FIGS. 1A and 1B. As for the connector which is realized by the connector shown in the figure and branches the cable itself, the connector 100' shown here and FIG. 5A described below.

This is realized by a connector 100' shown in FIG. 5B.

As shown in FIG. 4C, after the outer sheath 69 and the shielding film 68 (see FIG. 14) are peeled off from the tip of the cable 60, the cable 60 is provided with a pressure contact terminal having a shape similar to that of the pressure contact terminal 81 shown in FIG. It is press-fitted into the terminal 81'. This press fit is
This is done by a stuffer 106' provided on a lid 104' that is placed on the housing lot'. The pressure contact terminal 81' is combined with a contact 82' having a shape similar to the contact 82 shown in FIG.

A waterproof seal ring 1 is provided inside the contact portion 103'.
07' is provided. A shield plate 105' is provided inside the lid 104'! t104',
An opening 104c' provided in the shield plate 105',
Except that the integrated circuit package 80 shown in FIG. 13 is not incorporated in this connector, and the cable extends only in one direction, such as resin being injected from 105c' and filling the internal space. , which is an embodiment of the connector of the present invention, is constructed almost in the same way as the connector shown in FIGS. 1A and 1B. Furthermore, this connector 1
The outer wall 101a' of the housing 1 (if ') of 00' is metal plated in contact with the shield plate 105',
Enhances shielding effect. Furthermore, if an insulating material is further placed over the metal plating, when this connector 100' is used for wiring an automobile circuit, for example, electrical contact with an external conductive part (automobile chassis, etc.) can be prevented. be able to.

FIGS. 5A and 5B are external perspective views showing a connector to be combined with the cable branching connector shown in FIGS. 4A to 4C, and z-z' shown in FIG. 5A, respectively.
FIG.

This connector has the following features, except that the cable 80 extends in two directions, left and right, and that the housing 101' and contacts 82'' have a shape that allows them to be combined with the connector 101' shown in FIGS. 4A to 4C. Figures 4A to 4C
It has almost the same configuration as the connector 100' shown in the figure. Portions corresponding to the connector 100' shown in FIGS. 4A to 4C are shown with two dashes added to the number corresponding to the connector 100', and detailed description thereof will be omitted.

The cable 60 of this connector 100' extends in two directions, left and right, so by combining this connector 100' with the above connector 100', the cable 60
is branched.

(Effects of the Invention) As explained in detail above, in the integrated circuit package of the present invention, since the lead frame itself is equipped with pressure contact terminals and contacts, the number of electrical contacts in the connector as a whole can be reduced and reliability is improved. do. Furthermore, the number of parts can be reduced, and assembly work can be made more efficient, resulting in lower costs.

Furthermore, since the connector of the present invention incorporates the integrated circuit package of the present invention described above, it is possible to improve reliability, reduce the number of parts, and improve the efficiency of assembly work. Also,
In the connector of the present invention, the internal space surrounding the portions other than the contacts of the integrated circuit package formed by the lid and the housing is filled with resin, so that the pressure contact portion between the integrated circuit and the electric wire is prevented. It can be completely protected from water droplets. Further, this waterproofing can be easily achieved because it only requires filling with resin. Therefore, a connector with a built-in integrated circuit that is low in cost, highly reliable, and has a waterproof structure is constructed.

[Brief explanation of the drawing]

Fig. 1A is a side sectional view of one embodiment of the connector of the present invention, Fig. 1B is a front sectional view taken along the line xx' in Fig. 1A, and Fig. 2 is a cross-sectional view of the contact portion in Figs. A schematic perspective view schematically showing the structure. Figure 3 is a perspective view of another seal ring holder that can be used in place of the seal ring holder shown in Figure 2. Figures 4A to 4C are cable branch connectors. An example of
A perspective view of the main parts before assembly, a perspective view of the exterior after assembly, and a sectional view taken along Y-Y' in Figure 4B. Figures 5A and 5B show the cables shown in Figures 4A to 4C. FIG. 6 is a diagram showing the control system; FIG. 7 is a diagram showing the control system of the present invention; FIG. A circuit block diagram showing an example of the configuration of an internal circuit of an integrated circuit chip constituting an integrated circuit package, FIG. 8 is a timing chart showing the operation of the circuit shown in FIG. 7, and FIG. 9 is an integrated circuit of the present invention. A circuit block diagram showing another example of the configuration of the internal circuit of the integrated circuit chip constituting the package, FIG. 10 shows the time series signal DATA in the circuit of FIG.
FIG. 11 is a diagram showing the external connection system of an integrated circuit chip having the circuit configuration shown in FIG. 7 or FIG. 9. FIG. FIG. 13 is a perspective view of an external appearance of an embodiment of the integrated circuit package of the present invention, and FIG. 14 is a diagram showing an example of a lead frame to which wire bonding is applied. FIG. 15A and 15B are a side sectional view and a perspective view showing the inside of another embodiment of the cable, respectively. 1... Controller 2... Pass line (cable) 3... Connector 4... Motor 5... Switch 6... Lamp 7... Sensor
8... Branch point 10, 10'... Internal circuit
11-30...Pad 31...Line receiver
32.33-... Counter 34... Clock sense circuit 3B... Oscillator 88.39... 3-bit-8-bit decoder 41... Command latch circuit 43... Bidirectional buffer circuit 60.90. ...Cable 61-68.91...Electric wire (core wire) 87.92...Inner cover 88.93.94...Aluminum coating film for shielding 69.95...Outer cover 70...Lead frame 80・
... Integrated circuit package 81 ... Pressure contact terminal 82 ... Contact 8
3... Capacitor 93a, 94a... Perforation 100... Connector 100', 100'... Cable branch connector 1
01... Connection part 101d... Connection part 10
2...hole 103...contact part 104...M
2O3...Shield plate 105a...Wire contact piece
LO5b...Contact piece 108...Inner space 107...Waterproof seal ring 108.108'...Seal ring presser r~ Figure Figure Figure 5A Figure 4A Figure 48 Figure 4C Figure Figure 15A\95

Claims (2)

[Claims] (1) An integrated circuit chip that performs serial-to-parallel conversion of signals, comprising a pad for time-series signals and a large number of pads for parallel signals;
and a lead frame having a pressure contact terminal connected to the time-series signal pad, to which an electric wire is pressure-welded, and a large number of contacts respectively connected to the plurality of parallel signal pads, the pressure contact terminal and the An integrated circuit package characterized in that the integrated circuit chip is encapsulated in a resin so that the contacts are exposed. (2) A connector comprising the integrated circuit package according to claim 1, wherein the contact portion has a hole into which the contact is inserted, and is coupled to another connector by inserting the contact into the hole. a housing including the integrated circuit package, an electric wire press-welded to the press-contact terminal, and a lid mounted on the housing so as to cover the press-contact terminal and the integrated circuit chip, the lid and A connector characterized in that an internal space formed by the housing and surrounding the pressure contact terminal and the integrated circuit chip is filled with resin.