JPH0221783A - Drive method for solid-state image pickup element - Google Patents

Drive method for solid-state image pickup element

Info

Publication number
JPH0221783A
JPH0221783A JP63173205A JP17320588A JPH0221783A JP H0221783 A JPH0221783 A JP H0221783A JP 63173205 A JP63173205 A JP 63173205A JP 17320588 A JP17320588 A JP 17320588A JP H0221783 A JPH0221783 A JP H0221783A
Authority
JP
Japan
Prior art keywords
potential
register
photodiode
electrode
vertical transfer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63173205A
Other languages
Japanese (ja)
Inventor
Yukio Yaji
谷治 行夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP63173205A priority Critical patent/JPH0221783A/en
Publication of JPH0221783A publication Critical patent/JPH0221783A/en
Pending legal-status Critical Current

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  • Solid State Image Pick-Up Elements (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)

Abstract

PURPOSE:To reduce a highlight after-image and to expand the dynamic range by setting a potential under a transfer electrode of a vertical transfer register not in common use with a readout gate electrode higher than the potential set to a photodetector. CONSTITUTION:A charge stored in a photodiode 5 at storage is read to a CCD register 6 under the 2nd layer transfer electrode while a readout gate region 4 is set at readout. In this case, the setting potential of the photodiode 5 is set lower than the potential of a CCD register 7 under the 1st layer transfer electrode, then the charge of the photodiode 5 is all able to be moved to the CCD register 6. Thus, a clear video image without highlight after-image is obtained.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はインターライン型COD固体撮像素子に関し、
特にその特性を改善する方法に関する。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an interline type COD solid-state image sensor,
In particular, it relates to methods of improving its properties.

〔従来の技術〕[Conventional technology]

2次元CODイメージセンサー(固体撮像素子)は複数
の受光素子と、受光素子により光電変換蓄積された電荷
を転送する垂直・水平転送レジスタと、受光素子から電
荷を転送レジスタへ読み出す読み出しゲートを1つの基
板上に備えており、近年、技術の進歩により高密度化と
共に小形化が推し進められている。しかしながら光学フ
ォーマットの制限や解像度の点から限度があり、現状で
はLSIの中でもチップ面積の大きい部類に属している
。一方ブルーミングやスミャといった固体撮像素子特有
の欠点の改善と高密度化を容易にすることを目指した技
術として縮型オーバーフロードレインがあるが、これは
基板のうえに大面積のウェルを形成しその中に素子を作
るためチッブ面積が大きく、また駆動電圧の高いCCD
では駆動パルスによるウェルの揺れが無視できない。
A two-dimensional COD image sensor (solid-state image sensor) consists of multiple light-receiving elements, vertical and horizontal transfer registers that transfer the charges photoelectrically converted and accumulated by the light-receiving elements, and a readout gate that reads the charges from the light-receiving elements to the transfer registers. It is provided on a substrate, and in recent years, advances in technology have led to higher density and smaller size. However, there are limits due to optical format limitations and resolution, and currently it belongs to the category of large chip area among LSIs. On the other hand, there is a reduced-type overflow drain technology that aims to improve the shortcomings peculiar to solid-state imaging devices such as blooming and smearing, and to facilitate higher density. CCDs have large chip areas and high driving voltages to make elements.
In this case, the shaking of the well due to the driving pulse cannot be ignored.

このため受光素子であるフォトダイオードのセット電圧
が2次元状に異なるために飽和出力のシェーディングが
発生し、出力のダイナミックレンジを制限していた。
For this reason, the set voltage of the photodiode, which is a light-receiving element, differs in two dimensions, resulting in shading of the saturated output, which limits the dynamic range of the output.

このような欠点を緩和するために従来ウェルの揺れを少
なくするような方法がとられてきた。例えば、1つのフ
ォトダイオードに対して複数の垂直転送レジスタの電極
を設け、このうちの1つで読み出しゲートを形成し、ウ
ェルへの結合容量を減少させる方法や、同様の目的でよ
り上層の転送電極で読み出しゲートを形成するといった
ことが行われている。第3図(a)に示したものは1つ
のフォトダイオード5に対して2つの垂直転送レジスタ
電極2.3を設け、さらに2層目の電極(第2層転送電
極3の一部(読み出しゲート領域上)が読み出しゲート
電極を兼ねている。)3で読み出すものである。また、
この例では第1層転送電極2の面積を広くして第2層転
送電極3を狭くすることにより更に結合容量を減らして
いる。
In order to alleviate such drawbacks, conventional methods have been used to reduce the shaking of the well. For example, there are methods in which multiple vertical transfer register electrodes are provided for one photodiode and one of these electrodes forms a readout gate to reduce the coupling capacitance to the well, or for the same purpose, upper layer transfer Forming a readout gate with an electrode is being practiced. In the case shown in FIG. 3(a), two vertical transfer register electrodes 2.3 are provided for one photodiode 5, and a second layer electrode (part of the second layer transfer electrode 3 (readout gate) is provided. (on the region) also serves as a readout gate electrode.)3 is used for reading. Also,
In this example, the coupling capacitance is further reduced by increasing the area of the first layer transfer electrode 2 and narrowing the second layer transfer electrode 3.

第3図(b)は第3図(a)のA−A’の7オトダイオ
一ド電荷蓄積時と電荷読み出し時の各部の電位と電荷の
移動の様子を示したものである。蓄積時フォトダイオー
ドらに蓄積されていた電荷は読み出し時読み出しゲート
領域4がONL第2第2送転送電極下CODレジスタ6
荷が読み出される。読み出し時のフォトダイオードの電
位は第1層転送電極下CCDレジスタ7の電位より高い
のでフォトダイオード5に蓄積されている電荷量Qpo
が少なければ電荷は第2層転送電極下CODレジスタ6
に完全に移動するがフォトダイオードに蓄積される電荷
量Qpoが大きくなると第2層転送電極下CODレジス
タ6の面積が小さいために第3図(b)の様にフォトダ
イオードに電荷が残ってしまう。
FIG. 3(b) shows the state of potential and charge movement at various parts during charge accumulation and charge readout in the seven diodes along line AA' in FIG. 3(a). The charge accumulated in the photodiodes during storage is transferred to the COD register 6 under the second transmission and transfer electrode when the readout gate region 4 is ONL during readout.
load is read out. Since the potential of the photodiode during readout is higher than the potential of the CCD register 7 under the first layer transfer electrode, the amount of charge Qpo accumulated in the photodiode 5
If there is less charge, the charge will be transferred to the COD register 6 under the second layer transfer electrode.
However, when the amount of charge Qpo accumulated in the photodiode increases, the area of the COD register 6 under the second layer transfer electrode is small, so that charge remains in the photodiode as shown in FIG. 3(b). .

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述のように強い光がフォトダイオードに入射した場合
、読み残し電荷がフォトダイオード自身に残るためハイ
ライト残像として観測される問題点がある。
When strong light is incident on a photodiode as described above, there is a problem in that unread charges remain on the photodiode itself and are observed as a highlight afterimage.

本発明は上述のハイライト残像を低減しダイナミックレ
ンジを拡大することを目的としている。
The present invention aims to reduce the above-mentioned highlight afterimage and expand the dynamic range.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の駆動方法は同一半導体基板上に受光素子と前記
受光素子により光電変換蓄積された電荷を転送する垂直
転送レジスタ、及び水平転送レジスタと前記受光素子か
ら電荷を垂直転送レジスタへ読み出す読み出しゲートを
からなり、前記受光素子の1素子に対し前記垂直転送レ
ジスタの複数個の転送電極のうち一部より形成されてい
る固体撮像素子において、前記受光素子から電荷を前記
垂直転送レジスタへ読み出す際に前記受光素子に設定さ
れる電位よりも前記読み出しゲート電極をかねない前記
垂直転送レジスタの転送電極下の電位を高く設定する構
成となっている。
The driving method of the present invention includes, on the same semiconductor substrate, a photodetector, a vertical transfer register that transfers the charges photoelectrically converted and accumulated by the photodetector, and a horizontal transfer register and a readout gate that reads the charges from the photodetector to the vertical transfer register. In a solid-state imaging device in which one element of the light receiving element is formed from a part of the plurality of transfer electrodes of the vertical transfer register, when reading charges from the light receiving element to the vertical transfer register, the The configuration is such that the potential under the transfer electrode of the vertical transfer register, which also serves as the readout gate electrode, is set higher than the potential set to the light receiving element.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。第1図
は本発明の実施例を示すものである。
Next, the present invention will be explained with reference to the drawings. FIG. 1 shows an embodiment of the invention.

第1図(a)は第3図(a)とまったく同じものである
。ところが本発明は第1図(b)に示すようにフォトダ
イオード5の設定電位を第1層転送電極下CODレジス
タ7の電位より低くすることにより読み出し時にフォト
ダイオード5の電荷を全てCCDレジスタに移動させる
ことを可能にしている。このような条件を満足させる方
法としては駆動パルス、もしくはプロセスに条件を与え
ることが考えられ固体撮像素子としての特性のバランス
を考慮してこれら条件が決定される。この様子を第2図
を用いて説明する。第2図(a)はゲート電圧に対する
ポテンシャル電位のグラフを読み出しゲート領域4とし
てCCDレジスタについて示したものでb点はCCDレ
ジスタのゲート電圧が0■の時の電位を示し、a点は読
み出しゲート領域4の電位がb点と同じ電位のときのゲ
ート電圧を示したものである。グラフの下の波形は実際
にゲートにかかる電圧を示したものでフォトダイオード
が蓄積時、すなわちCCDレジスタが転送状態ではVM
とVrの間で電圧がかけられ、読み出しゲート領域がO
FFした状態を維持するのに対し、読み出し時には、V
Hの電圧がかかりフォトダイオードは第2図(a)の場
合a点すなわちb点の電位にセットされることになる。
FIG. 1(a) is exactly the same as FIG. 3(a). However, in the present invention, as shown in FIG. 1(b), by setting the set potential of the photodiode 5 lower than the potential of the COD register 7 under the first layer transfer electrode, all the charges in the photodiode 5 are transferred to the CCD register during readout. It is possible to do so. A possible method for satisfying such conditions is to provide driving pulses or conditions to the process, and these conditions are determined in consideration of the balance of characteristics of the solid-state imaging device. This situation will be explained using FIG. 2. Figure 2 (a) shows a graph of potential potential versus gate voltage for a CCD register with readout gate area 4. Point b shows the potential when the gate voltage of the CCD register is 0, and point a shows the potential at the readout gate. It shows the gate voltage when the potential of region 4 is the same potential as point b. The waveform at the bottom of the graph shows the voltage actually applied to the gate, and when the photodiode is storing data, that is, when the CCD register is in the transfer state, it is VM.
A voltage is applied between Vr and Vr, and the read gate region is
While the FF state is maintained, when reading, V
A voltage of H is applied, and the photodiode is set to the potential at point a, that is, point b, in the case of FIG. 2(a).

これから第1図(b)に示すような条件を実現するため
にはVHを第2図のa点より低い電位とすればよいこと
がわかる。しかしながらフォトダイオードに蓄積される
最大電荷量をQpoとすると、これはQpo÷CpoX
 (b / a ) V Hとなり(CPDは7オトダ
イオードの容量)、VHをa点より、極めて小さくする
ことはフォトダイオードに蓄積される最大電荷量の減少
につながるためハイライト残像の発生しないダイナミッ
クレンジとの兼ね合いで設定する必要がある。すなわち
、第1層転送電極下のCCDレジスタの容量をC1,第
2層転送電極下のCCDレジスタの容量をC2とすると
第2図(b)のようにVHをa点からe点まで下げた場
合のCCDレジスタの受けとりうる最大の電荷量(第1
図(b)の読み出し時の斜線部の電荷の最大値)Qcc
oはQcco=CtX(b  d)+C2(e−d)と
して与えられるところからハイライト残像の発生しない
条件は、Qcco≧QpDを満たすように(b−d)の
電位差を確保すればよいことがわかる。また、縦型オー
バーフロードレインの動作によりQpoはある光量以上
ではVGによらず一定となる。この点をQOFとすると
Qopに相当するゲート電圧、すなわち(Q op/ 
Cpo )(a/b)が0点より低い場合にはオーバー
フロードレイン動作によりこのハイライト残像は発生し
ない、従って(Cop/Cpo)  (a/b ) >
cの場合のみ前記の方法に従ってVHを調整する必要が
ある。よってオーバーフロートレインの制御特性によっ
ても条件設定の変更が必要となる。
From this, it can be seen that in order to realize the conditions shown in FIG. 1(b), it is sufficient to set VH to a potential lower than point a in FIG. 2. However, if the maximum amount of charge accumulated in the photodiode is Qpo, then this is Qpo÷CpoX
(b/a) VH (CPD has a capacitance of 7 photodiodes), and making VH extremely smaller than point a will lead to a decrease in the maximum amount of charge accumulated in the photodiode, resulting in a dynamic image that does not cause highlight afterimages. It is necessary to set it in consideration of the range. In other words, if the capacitance of the CCD register under the first layer transfer electrode is C1, and the capacitance of the CCD register under the second layer transfer electrode is C2, VH was lowered from point a to point e as shown in Figure 2(b). The maximum amount of charge that can be received by the CCD register (first
Maximum value of charge in the shaded area during readout in figure (b)) Qcc
Since o is given as Qcco = Ct Recognize. Furthermore, due to the operation of the vertical overflow drain, Qpo remains constant regardless of VG above a certain amount of light. If this point is QOF, then the gate voltage corresponding to Qop, that is, (Q op/
When Cpo ) (a/b) is lower than 0 point, this highlight afterimage does not occur due to the overflow drain operation, so (Cop/Cpo) (a/b ) >
Only in case c, it is necessary to adjust VH according to the method described above. Therefore, it is necessary to change the condition settings depending on the control characteristics of the overflow train.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、ウェルの揺れを少なくすために受
光素子、−素子に対し垂直転送レジスタの複数個の転送
電極を対応させ、読み出しゲート電極をこの一部から形
成するような固体撮像素子についても、受光素子の設定
電位を読み出しゲート電極を兼ねない転送電極の電位よ
り低くすることによりハイライト残像のないクリアーな
映像で得ることができる。
As explained above, in order to reduce well fluctuation, a plurality of transfer electrodes of a vertical transfer register are made to correspond to a light receiving element, and a readout gate electrode is formed from a part of this solid-state image sensor. Also, by setting the potential of the light receiving element lower than the potential of the transfer electrode which also serves as the readout gate electrode, a clear image without highlight afterimages can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)、(b)は本発明の概要図、第2図(a)
、(b)は第1図の動作を説明するためのポテンシャル
電位グラフ、第3図(a)(b)は従来例の概要図であ
る。 2・・・第1層転送電極、3・・・第2層転送電極、4
・・・読み出しゲート領域、5・・・フォトダイオード
、6・・・第2層転送電極下CODレジスタ、7・・・
第1層転送電極下CODレジスタ。
Figures 1(a) and (b) are schematic diagrams of the present invention, Figure 2(a)
, (b) are potential potential graphs for explaining the operation of FIG. 1, and FIGS. 3(a) and 3(b) are schematic diagrams of the conventional example. 2... First layer transfer electrode, 3... Second layer transfer electrode, 4
... Readout gate region, 5... Photodiode, 6... COD register under second layer transfer electrode, 7...
COD register under the first layer transfer electrode.

Claims (1)

【特許請求の範囲】[Claims] 同一半導体基板上に受光素子と前記受光素子により光電
変換蓄積された電荷を転送する垂直転送レジスタ、及び
水平転送レジスタと前記受光素子から電荷を垂直転送レ
ジスタへ読み出す読み出しゲートを備え、前記受光素子
の1素子に対し前記垂直転送レジスタの複数個の転送電
極が対応し、かつ前記読み出しゲート電極が前記垂直転
送レジスタの複数個の転送電極のうちの一部より形成さ
れている固体撮像素子の前記受光素子から電荷を前記垂
直転送レジスタへ読み出す際に、前記受光素子に設定さ
れる電位よりも前記読み出しゲート電極をかねない前記
垂直転送レジスタの転送電極下の電位を高く設定するこ
とを特徴とする固体撮像素子の駆動方法。
A light receiving element, a vertical transfer register for transferring charges photoelectrically converted and accumulated by the light receiving element, and a horizontal transfer register and a readout gate for reading charges from the light receiving element to the vertical transfer register are provided on the same semiconductor substrate, and the light receiving element A plurality of transfer electrodes of the vertical transfer register correspond to one element, and the readout gate electrode is formed from a part of the plurality of transfer electrodes of the vertical transfer register. A solid state characterized in that, when reading charges from an element to the vertical transfer register, a potential under a transfer electrode of the vertical transfer register that serves as the readout gate electrode is set higher than a potential set to the light receiving element. How to drive the image sensor.
JP63173205A 1988-07-11 1988-07-11 Drive method for solid-state image pickup element Pending JPH0221783A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63173205A JPH0221783A (en) 1988-07-11 1988-07-11 Drive method for solid-state image pickup element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63173205A JPH0221783A (en) 1988-07-11 1988-07-11 Drive method for solid-state image pickup element

Publications (1)

Publication Number Publication Date
JPH0221783A true JPH0221783A (en) 1990-01-24

Family

ID=15956062

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63173205A Pending JPH0221783A (en) 1988-07-11 1988-07-11 Drive method for solid-state image pickup element

Country Status (1)

Country Link
JP (1) JPH0221783A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7927640B2 (en) 2004-02-02 2011-04-19 Delavau Llc Calcium fortification of bread dough

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7927640B2 (en) 2004-02-02 2011-04-19 Delavau Llc Calcium fortification of bread dough
US8221808B2 (en) 2004-02-02 2012-07-17 Delavau L.L.C. Calcium fortification of bread dough
US9386776B2 (en) 2004-02-02 2016-07-12 Delavau L.L.C. Calcium fortification of bread dough

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