JPH022176A - Semiconductor device - Google Patents

Abstract

PURPOSE:To realize a rapid operation with stable current-voltage characteristics which are not affected by a substrate potential at all having little stray capacitance by burying a part of a source region of an SOI element into an insulation film and by extending it to an area immediately below a channel region between a drain region and the source region. CONSTITUTION:For example, a silicon oxide film 220 is deposited on a silicon substrate 210 through a CVD method. An opening section 290 is formed in a tapered shape and an N-type polycrystalline silicon film 230 is prepared. Etching is made to an area deeper than a first silicon layer 230 to form an opening section 292. After a mask is removed, a silicon oxide film 293, etc., is buried into the opening section 292 and then the surface is flattened. A surface of a second silicon layer 240 is heat-oxidized and agate insulation film 250 is formed. For example, arsenic ion is ion-implanted all over to form N-type region 270 and 280.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor device formed on an insulating substrate or an insulating film.

(Prior art) Recently, SOI (5
ilicon on in5ulator) technology is being actively developed. Then, an insulated gate single field effect transistor (STOS) is applied to the semiconductor layer obtained using this technology.
A three-dimensional IC formed by forming FgT is currently under development. A conventional MOSFE formed on such an insulating film
A cross section obtained by cutting along one channel length of T is shown in FIG. Usually, elements are formed on the silicon substrate 31, and the insulation layer 32 has a thickness of about 1 μm.
m is formed. Here, in order to make one drawing into one subtitle, a diagram of the formation of elements on the silicon substrate 31 is omitted. On the M edge film 32 formed above, by the SOI technology mentioned in @,
Single crystal silicon 1534 is formed. This layer has a thickness of approximately 0.1 μm and a degree of impurity N = IX1014Cm''
``It's 1.Next.

After forming approximately 10 OA of ub gate insulation @35, polycrystalline silicon @36 is subsequently deposited. Then, the polycrystalline silicon layer 36 and the gate isolation film 35 are patterned using a commonly used phosphorography technique. A drain region 37 and a source region 38 are formed by introducing an impurity, for example, arsenic, into the exposed silicon base plate of this bag 1. In this way, the MOSFET on the insulating film 32 is opened.

In this MOSFET, as mentioned above, the substrate impurity concentration is extremely low at I x 10"cm-".

Moreover, since the semiconductor layer 34 is very thin at about 1.0 μm,
When the gate t4 pressure is applied, the entire substrate is depleted,
The mode of current flowing between the source and drain is not the usual surface type flowing through the inversion 1, but the bulk type flowing through the entire layer plate. Therefore, the mobility of carriers is greater than that of the Momomen type, and there is an advantage that high-speed previous devices can be realized.

However, as mentioned above, since the entire semiconductor layer 34 is depleted, the four lines of force coming out from the gate 1.

It passes through the semiconductor l'1I34 and terminates at the substrate 31.

Therefore, variations in substrate potential directly affect the current-voltage characteristics of the MO8FET. In other words, the gate voltage (
For example, when the substrate potential v3ub changes from □V to -5V, the threshold direct voltage changes by about O, tV, and the 1-current level changes by about 100 times, as shown in the characteristic diagram of the drain current (more) versus V). do. This change has been a major hindrance in the design of integrated circuits.

In addition, as shown in FIG. 3, there is a structure in which a shield 139 is provided in one part of the insulating film 32 in order to four-dimensionally shield the electric lines of force penetrating the semiconductor layer 34.
In this case, between the source 38 and the shield 39, between the drain 37 and the seal 11, and between the silicon IJ connector i[31
The capacitors between the shield 1 and the shield 1 are extremely large, and the high speed of the device is in contrast to the previous work. On the other hand, if the thickness of the insulating films 32, 32a is increased in order to reduce the capacitance, the precision of microfabrication deteriorates, so there is a restriction that the insulating films 32, 32a cannot be made so thick.

(Problems to be Solved by the Invention) The present invention has been made in view of the drawbacks of the above-mentioned conventional methods.
The purpose of this is to provide an SOI device with stable characteristics in which the current flow of the device is not affected by the substrate potential. One object of the present invention is to provide a semiconductor device having an SOI element structure that has little stray capacitance and operates at high speed.

[Structure of the invention]

(Means for determining Section 1:4) The gist of the present invention is that a part of the source region of the SUI element is buried in an insulating layer and extends directly below the channel region between the drain region and the source region. There are many places where this is done. As a result, it has stable current-voltage characteristics that are completely unaffected by substrate potential.

In addition, a semiconductor device having an SOI element structure is provided which can operate at high speed with less floating order.

(Function) The present invention (engineering) embeds the source region of the SOI quadruplets in an insulating layer and extends it directly below the channel region between the drain and the source, so that the gate of the SOI quadrature is The line is terminated to the buried and extended source region.This is where the so-called shielding effect is utilized. It has a structure that can effectively prevent damage and provide effective shielding.

(Embodiment) The details of one embodiment of the present invention will be described below with reference to the drawings.

FIG. 1a) is a top view showing an embodiment of an SOI device according to the invention. In addition, if Fig. 1 1bl, Fig. 1 (a
)) Here, the SOI cut along the dashed line of A-A'
FIG. 3 is a cross-sectional view of the element. Furthermore, in Fig. 1 1cl, the SO
FIG. 3 is a cross-sectional view of an I element. Identical parts in FIG. 11 is, for example, a semiconductor silicon substrate. 12 is an insulating film formed on the semiconductor silicon substrate, for example a silicon oxide film, and 19 is a buried field insulating film. and,
Reference numeral 14 denotes a silicon semiconductor layer of, for example, P-type (100) orientation, and reference numerals 17 and 18 denote drain and source regions having a high impurity concentration, for example, arsenic impurity, and having opposite conductivity to the silicon semiconductor layer. Further, 13 is a buried half wire 1 having a source region connected to the previous source region and a conductivity type. 15 is a gate insulating film. And 16 is a gate electrode made of polycrystalline silicon.

Figure 2 (ml-fit is a sectional view showing the manufacturing process of the SOI device according to the present invention shown in Figures 1-fcl).

First, as shown in FIG. 2, for example, silicon oxide 11i 22 is deposited on a silicon substrate 210 by the CVD method.
Deposit about 0.5 μm of 0. This silicon oxide film 220
A mask pattern based on Raffi technology is used.

The opening 2909 is formed by etching into a tapered shape. Next, as shown in Figure 2 (tb) 1, the entire surface is coated with a thickness of about 0.2 mm.
A μm N-type polycrystalline silicon layer 230 is formed.

Next, as shown in FIG. 21, the polycrystalline silicon FIX 230 is patterned using normal gluing lithography, and a silicon oxide film 2 of about 0.5 μm thick is formed on the entire surface.
20m (Figure 2(d)). For example, acceleration voltage 15KV, beam current 2mA, beam swing I
Annealing is performed using a pseudo-shaped electron beam of f55 mm to deeply crystallize the polycrystalline silicon 5230 and form the first silicon 1230. Thereafter, the silicon oxide film 220a is formed into the opening 29 using a normal phosphorography technique.
1 into a tapered shape (FIG. 2 1e)). Next time,
After forming an amorphous silicon layer 240 with a thickness of about 0.1 μm,
Solid phase growth technology (e.g. 650°C.

20 minutes) to cause heavy viscosity crystallization and form a second silicon layer 240 (see Figure 2). Then, the portion that will become the element region is covered with a mask, and the pond portion is etched, for example, by reactive ion etching, to a depth deeper than the first silicon layer 230 to form an opening 292 (second JI).
gl), after removing the mask, the opening 2922;
For example, a silicon oxide film 293 is buried and the surface 1 is made flat (FIG. 2). In this manner, after the element isolation process is completed, the surface of the second silicon layer 240 is thermally oxidized to form a gate insulating film 250 with a thickness of about 10 OA, for example.

After that, perform boron ion implantation on the entire surface (this), and rub the P-type silicon ylil. Next, for example, polycrystalline silicon
The polycrystalline silicon@260 is patterned using a phosphorography technique with a thickness of approximately 0.4 μm. For example, arsenic ions are implanted into the entire surface, and N
Form regions 270 and 280 (Fig. 2 (1)).

Like this, gate'JL pole 260, drain around t42
70. Then, the process for forming the source region 280 is carried out in accordance with a conventional process.

An SOI device according to Example F of the present invention is completed.

FIG. 5 shows an example of the results of determining the electrical characteristics of the slightly completed 801 tag. A portion of the source region of the SOI device extends to the tip of the drain region. Even if the substrate No. 1 Vsub is changed from Ov to -5V, the 4th class-4th king characteristic is completely f: an SOI element that can shoulder the difference in characteristics.

In addition, the threshold direct voltage fluctuation (V 5ub = OV and -
5VB: ji; Figure 6 shows the relationship between △vT (difference between Lt and 1 voltage VT evaluated at Ip = 1 μA) and partial extension distance of the source region @X with the center of the channel as the origin f. (This relationship shows that the depth of
Even if it is changed within the insulating film 220 having a thickness of m@, there is almost no difference.

On the other hand, as the depth of the buried grindstone in the source region approaches the drain f, the capacitance between the source and drain increases. That is, as the extension 230 goes beneath the drain region, the capacitance increases approximately in direct proportion to the extension V4 +. Therefore, it is optimal to set the position of the extended end at the tip of the drain slope, that is, at the channel end, from the 174th point of the channel length in the direction of the fin 1f region, with the channel center position as the origin. It is.

In the above embodiments, an N-channel SOI device has been described as an example, but a P-channel SOI device may also be used.

In addition, the impurity concentration distribution of the source and drain is 1 normal high a
In addition to this, it is also possible to use a low-density Kamokai with a so-called LDD structure.

〔Effect of the invention〕

According to the present invention, part of the source region of the SOI element is
By embedding it in the insulating film of I and extending it directly below the channel region between its drain and source, stable current-voltage characteristics that are completely unaffected by changes in substrate potential can be obtained. , and the source-drain cavatance is small, making it an extremely immersed high-speed SOI.
An element is obtained.

4, 1! ! : Brief explanation of the J plane. Figure 1 (al is 1 is a top view showing an embodiment of the SOI device according to the present invention, l! 1 Figure 1b) is A- of Figure 1 1a).
A cross-sectional view of the SOI device cut at A', FIG. 1 (cl is
1154 FIG. 2 is a cross-sectional view of the SOI device taken along line BB' in (a), showing an embodiment of the SOI device according to the present invention. Cross-sectional view showing the 11-jit process, FIG. 3(a),
(bl is a sectional view of a conventional SOI device, FIG. 4 is a characteristic diagram of the conventional SOI device, FIG. 5 is a diagram showing the electrical characteristics of the SOI device of the present invention, and FIG. 6 is a diagram of the SOI device of the present invention. FIG. 3 is a diagram showing the relationship between threshold direct voltage fluctuation and source extension distance of an element.

11.210.31...Silicon plate, 12,220
゜220a, 32, 32a...Insulating film, 13,230
... Buried extension of source area, 14,240.34.
...Semiconductor layer, 15.250.35...Gate insulating film, 16,260.36...Polycrystalline silicon@, 17,
270.37...Drain region, 18,280.38
... Source region, 19.293 ... Buried field insulating film, 290, 291.292 ... Opening, 1
8.240a...Remaining part of silicon crystallized,
39...Shield 1゜Representative Patent Attorney Nori W! i Same as right
Mitsuru Matsuyama @ l Prisoner Figure 1 Figure 1 Cause Figure Figure Figure 1/, O -〇, 5 0, s 7.0 Channel 1 Channel center n. figure

Claims (2)

[Claims] (1) A source having a plurality of semiconductor layers containing a first impurity formed in an island shape on an insulating substrate or an insulating film, and a second impurity introduced into the semiconductor layer. and a drain region formed therein, and a semiconductor device having a gate region on the semiconductor layer for controlling the potential of a channel region between the source and the drain, wherein a part of the source region is connected to the insulating substrate below the channel region. ,or,
A semiconductor device characterized by being embedded in an insulating film and extending in the direction of a drain region. (2) The semiconductor device according to claim 1, wherein the region extending in the direction of the drain region of the source region is set from a position of 3/4 of the channel length to a channel end position on the drain side.