JPH02217022A - Galois field computing element - Google Patents

Abstract

PURPOSE:To execute various general purpose operation by providing the title computing element with 1st and 2nd selection means, 1st and 2nd conversion means and a computing means. CONSTITUTION:The computing element is provided with the 1st conversion means for the 1st input in the Galois field GF2<m> (m is a position integer) of a Galois field GF2, the 1st selection means for finding out the 1st operand A from a 1st input and the output of the 1st conversion means, the 2nd conversion means for a 2nd input, the 2nd selection means for finding out a 2nd operand B from the 2nd input and the output of the 2nd conversion means, and the computing means for setting up a 3rd operands C, S respectively to (1, 1) and (B, O) and the time of adding and multiplying based upon the 3rd control signal to find out (A+1).C+B+S. Consequently, the Galois field computing element capable of attaining various operation from inputs P, Q and constituted of a small circuit substrate can be constituted.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a Galois extension field arithmetic unit that performs various general-purpose operations on the Galois extension field required when error correction codes are used.

2. Description of the Related Art Regarding this type of arithmetic unit, in the conventional technology, for example, addition is performed using exclusive OR of vector representations of elements, or (1+
αj−i) is obtained from ROM etc. and α1 αJ=α・(1
+α”-”), and multiplication is a direct operation of the vector representation of the element, or Mod (2”-1) of the exponential representation.
This is done individually by adding .

Problems to be Solved by the Invention However, the above configuration has the problem that it is difficult to configure when various calculations are required, and even if it is configured, the circuit scale is large.

In view of the above, an object of the present invention is to provide a Galois extension field arithmetic unit capable of performing general-purpose operations.

Means for Solving the Problems The present invention provides a first conversion means for a first input, and a first arithmetic operation A is calculated from the output of the first input and the first conversion means on CF (2'''). a first selection means, a second conversion means for a second input, a second selection means for determining a second operation number B from the second input and an output of the second conversion means, and a second selection means based on a third control signal. During addition and multiplication, the third operation number (C, S
) are respectively (1, 1) (B, O) and (A
+1)・C+B+S is a Galois expansion field arithmetic unit equipped with an arithmetic means for calculating C+B+S.

Effect The present invention calculates the first operation number A from the first input P and its several converted values, and the second operation number B from the second input Q and its several conversion values, and then adds them. Sometimes (C,S) = (1
, 1), and when multiplying (C, S') = (B, O), (
By finding A+1) and C+B+S, respectively (
A+ 1 )・1+B+1 =A+B, (A+ 1
)・B+B+0=A-B, input P,
A Galois extension field arithmetic unit with a small circuit scale that enables a variety of operations is constructed from Q.

Example Embodiments of the present invention will be described below with reference to the drawings.

The figure shows the configuration of a Calois extension field arithmetic unit on F (2') in an embodiment of the present invention. 1 is a square converter, 2 is a source converter, 3 is a first selector, 4 is a second selector, 5 is an arithmetic unit, 6 is a buffer, and 7 is a multiplier/adder.

The operation of this Galois extension field arithmetic unit will be explained below. First, the first selector 3 uses the first input P when the first control signal X is 0, and the output P2 of the square converter l when the first control signal X is 1. Output. The second selector 4 selects the second input Q when the second control signal y is O, and selects the output 1/Q of the source converter 2 when the second control signal y is 1.
Output as arithmetic number B. In the arithmetic unit 5, the buffer 6 first pulls up only the least significant bit of its output, pulls down the remaining m-1 bits from the higher order, and uses the third control signal 2 as an output enable (active low). Then, when 2=0, the second arithmetic number B is obtained, and when z=1, (0, 0, . . . , 0.1) is obtained as the third arithmetic number C. Then, in the multiplier/adder 7, the third arithmetic number S is applied to the third control signal 2 (LO+"・+O+2)
Then, (A+1)-C+B+S is determined and output. The actual values of the output are shown in the following table.

In this embodiment, a square converter and a backlight converter are used, but any conversion is possible, and control signals may be assigned arbitrarily. Here, the first input P is a single input, but multiple inputs are subjected to various transformations (the same transformation is not required for each input, and there are cases where no transformation is performed). It is also possible to input the first selector. The same applies to the second input.

Furthermore, the present invention is applicable to any Galois extension field.

As described in detail, according to the present invention, a wide variety of general-purpose operations can be performed with a simple circuit configuration.

[Brief explanation of the drawing]

The figure is a block diagram of a Calois extension field arithmetic unit in one embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Square converter, 2... Source converter, 3... First selector, 4... Second selector, 5... Arithmetic unit, 6...
... Buffer, 7... Multiply adder.

Claims (1)

[Claims] On the extension field GF(2^m) (m is a positive integer) of the Galois field GF(2), one or more first transformation means for the first input P, and the first input P and a first selection means that uses the output of the first conversion means as input and calculates a first operation number A from one or more inputs based on a first control signal;
one or more second conversion means for a second input Q; and a second conversion means for converting one or more inputs based on a second control signal using the second input Q and the output of the second conversion means as inputs. a second selection means for obtaining the two-operational number B;
), at the time of multiplication, the third operation number (S, C) is (0, B), and from the first operation number A and the second operation number B, (A+1)
- A Galois extension field arithmetic unit characterized by having an arithmetic means for calculating C+B+S.