JPH02216860A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH02216860A JPH02216860A JP3883289A JP3883289A JPH02216860A JP H02216860 A JPH02216860 A JP H02216860A JP 3883289 A JP3883289 A JP 3883289A JP 3883289 A JP3883289 A JP 3883289A JP H02216860 A JPH02216860 A JP H02216860A
- Authority
- JP
- Japan
- Prior art keywords
- silicon substrate
- depth
- resist
- resistance
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 11
- 239000012535 impurity Substances 0.000 claims abstract description 14
- 238000005452 bending Methods 0.000 claims abstract description 4
- 238000009792 diffusion process Methods 0.000 claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 10
- 229910052710 silicon Inorganic materials 0.000 abstract description 10
- 239000010703 silicon Substances 0.000 abstract description 10
- 239000000758 substrate Substances 0.000 abstract description 10
- 238000000034 method Methods 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 4
- 239000013256 coordination polymer Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分身〕 この発明は半導体装置に関するものである。[Detailed description of the invention] [Industrial use alter ego] The present invention relates to a semiconductor device.
第8図は従来の半導体抵抗の表面図、第9図は′fg8
図の■(線における断面側面図である。Figure 8 is a surface diagram of a conventional semiconductor resistor, Figure 9 is 'fg8
This is a cross-sectional side view taken along the line (■) in the figure.
図において、(11はシリコン基板CP型) 、(xi
はN型不純物拡散領域、(41は電極^、(51は電極
Bである。In the figure, (11 is a silicon substrate CP type), (xi
is an N-type impurity diffusion region, (41 is an electrode ^, (51 is an electrode B).
また、第10図は従来の半導体装置の説明図で、図にお
いて、(8)は電極AB間の距離LABである。Further, FIG. 10 is an explanatory diagram of a conventional semiconductor device, and in the figure, (8) is the distance LAB between the electrodes AB.
次に動作について説明する。Next, the operation will be explained.
第10図において、不純物拡散領域12)の全領域にお
いて不純物密度が一定であり、不純物拡散領域(2)の
巾が一定である場合、電極AB間の抵抗[をROとする
と、
RO−kLAB (kは正の定数) ・Il
l従って、抵抗匝の大きさは表面電極間距離LABに比
例する。In FIG. 10, if the impurity density is constant in the entire region of the impurity diffusion region 12) and the width of the impurity diffusion region (2) is constant, then if the resistance [between the electrodes AB] is RO, then RO-kLAB ( k is a positive constant) ・Il
Therefore, the size of the resistance box is proportional to the distance LAB between the surface electrodes.
従って抵抗[を大きくするためには、定’l1zkを大
きくするか、距@ LABを長くするかである。Therefore, in order to increase the resistance [, the constant 'l1zk must be increased or the distance @LAB must be increased.
kを大きくするためには、抵抗素子の巾を狭くするか、
不純物密度を下げるかであるが、不純物書r!t″Ir
一定領域だけ変えるのはプロセスフローが増える丈め困
難であり、一般的に抵抗値の調!Iは巾を狭めたり、L
ABを長くしたりしている。巾を狭める方法は写真製版
における限界があり、大体LABを長くして所望の抵抗
素子を形成しているのであるが、抵抗匝の大きなものは
、第8図のように形成せねばならないため、大きな表面
面積を占有することになる。In order to increase k, either narrow the width of the resistance element or
As for lowering the impurity density, impurity book r! t″Ir
Changing only a certain area increases the process flow, making it difficult to adjust the resistance value. I narrows the width, L
AB is also made longer. The method of narrowing the width has limitations in photolithography, and the desired resistance element is generally formed by lengthening the LAB, but a large resistance element must be formed as shown in Figure 8. It will occupy a large surface area.
従来の半導体抵抗は以上のように構成されてい九ので、
高抵抗を形成する場合大きな表面面積を必要とし、近年
、半導体集積回路の集積度が向上して傘ており、集積回
路のトランジスタ、容量。Conventional semiconductor resistors are constructed as shown above, so
Forming high resistance requires a large surface area, and in recent years, the degree of integration of semiconductor integrated circuits has improved, and the transistors and capacitance of integrated circuits have increased.
抵抗などの各素子の表面占有面積を小さくする必要があ
るが、一方、回路の電気特性向上のため一定表面面積内
で所望の抵抗愼を得る必要が生じるという問題点があっ
た。Although it is necessary to reduce the surface area occupied by each element such as a resistor, there is a problem in that it is necessary to obtain a desired resistance within a certain surface area in order to improve the electrical characteristics of the circuit.
この発明は上記のような問題点を解消するためになされ
たもので、深#I(トレンチ)形成により抵抗素子を深
さ方向に折り曲げて、同一占有面積で、所望の抵抗1直
を持った半導体装置を得ることを目的とする。This invention was made to solve the above-mentioned problems, and by forming a deep #I (trench) and bending the resistance element in the depth direction, it is possible to have a desired resistance of one straight line in the same occupied area. The purpose is to obtain a semiconductor device.
〔11題を解決するための手段〕
この発明に係る半導体装置は深#l(トレンチ)形成に
より、深さ方向に折り曲げることにより、小さな表面占
有面積にて、所望の抵抗11i t−持った抵抗素子を
得るようにしたものである。[Means for Solving Problem 11] The semiconductor device according to the present invention forms a deep #l (trench) and bends it in the depth direction, thereby forming a resistance having a desired resistance 11it- with a small surface area. It is designed to obtain an element.
この発明における抵抗素子は深溝(トレンチ)形成によ
って深さ方向に折曲げることにより、小さな表面占有面
積にて、所望の抵抗匝を持った半導体装riILf:得
る。By bending the resistance element in the depth direction by forming a deep groove (trench), a semiconductor device having a desired resistance value can be obtained with a small surface area.
以下、この発明の一実施例を図について説明する。第1
図はこの発明の一実施例である抵抗素子の表面図、第2
図は第1図の■−■線における断面側面図、第3図はP
型シリコン基板に深溝(トレンチ)を形成した状態を示
す断面図、■4図は第3図の表面図、第5図は第4図を
レジストパターニングを行った後の表面図である。An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is a surface view of a resistor element which is an embodiment of the present invention.
The figure is a cross-sectional side view taken along the line ■-■ in Figure 1, and Figure 3 is a P
A sectional view showing a state in which a deep groove (trench) is formed in a mold silicon substrate, Figure 4 is a surface view of Figure 3, and Figure 5 is a surface view of Figure 4 after resist patterning.
まず、P型シリコン基板に深溝(トレンチ)を第4図の
ように形成する。次に、レジストを塗布し、写真製版技
術によりパターニングする(第5図)。次に、レジスト
をマスクにして不純物を注入するCP型シリコン基板に
対しては、N型不純物P、^Sなど、またN型シリコン
基板に対してはP型不純物Bなど)。次にレジストを除
去し1アニールすれば、第1図、第2図の抵抗素子が得
られる。First, a deep groove (trench) is formed in a P-type silicon substrate as shown in FIG. Next, a resist is applied and patterned using photolithography (FIG. 5). Next, using a resist as a mask, impurities are implanted into a CP type silicon substrate (for example, N type impurities P, ^S, etc., and for an N type silicon substrate, P type impurities B, etc.). Next, by removing the resist and performing one anneal, the resistor elements shown in FIGS. 1 and 2 are obtained.
次に動作について第6図および第10図を用いて説明す
る。第10図の抵抗素子の抵抗値をRQとすると、
RO−k LAB (k n正(n定l()
・111次に、第6図のこの発明における電極間の距離
を第10図の場合と等しくした場合、この時の抵抗値を
R】とすると、
R1=k LAB+2nkL7 (o n自然数)
・+21fll 、 f21式より R1> Ro
−(3)(2)式より、深#I(ト
レンチ)の深さり、Tおよび深溝の数nt−調整するこ
とにより、一定面積内で所望の抵抗獲を持った抵抗素子
を得ることができる。Next, the operation will be explained using FIGS. 6 and 10. If the resistance value of the resistance element in Fig. 10 is RQ, then RO-k LAB (k n positive (n constant l()
・111Next, if the distance between the electrodes in this invention in FIG. 6 is equal to that in FIG. 10, and the resistance value at this time is R], then R1=k LAB+2nkL7 (on natural number)
・+21fll, from f21 formula R1> Ro
- (3) From equation (2), by adjusting the depth of depth #I (trench), T, and the number of deep grooves nt, it is possible to obtain a resistive element with a desired resistance gain within a certain area. .
なお、上記実施例では、深#l(トレンチ)の深さLT
は一定とした場合を示したが、第7図のように深さを変
えてもよい。この場合の抵抗値をR2とすると、
R2−kLAB + 2k(LTI ” LT2 +
LT3) ・・・(4)一般的には、
Rz−kLAB+2k(LTI +LT2’p ・=
・−”LTn) ・・−(5+もちろん R2>
ROとなる。In addition, in the above embodiment, the depth #l (trench) depth LT
Although the case where the depth is constant is shown, the depth may be changed as shown in FIG. If the resistance value in this case is R2, then R2-kLAB + 2k(LTI ” LT2 +
LT3) ... (4) Generally, Rz-kLAB+2k(LTI +LT2'p ・=
・-”LTn) ・・-(5+Of course R2>
Becomes an RO.
以上のようにこの発明によれば、同一の表面占有面積内
において、深溝(トレンチ)の故および#!1111(
)レンチ)の深さを調整することにより、所望の抵抗1
[を持った抵抗素子を得ることができる0As described above, according to the present invention, deep grooves (trenches) and #! 1111(
) wrench) by adjusting the depth of the desired resistance 1
It is possible to obtain a resistive element with [0
【図面の簡単な説明】
第1図はこの発明の一実施例における抵抗素子の表面図
、第2図は第1図のn−n馴における断面側面図、第3
図はP型シリコン基板に深溝を形成した断面図、第4図
は第3図の表面向、第5図は@4図をレジストパターニ
ング後の表面図、第6図はこの発明の抵抗素子の説明図
、第7図はこの発明の他の実施例の抵抗素子の断面図、
第8図は従来の抵抗素子の表面図、第9図は第8図の■
−X線における断面側面図、第10図は従来の抵抗素子
の説明図である。
図において、(l)はシリコン基板、12)はN型不純
物拡散領域、(3)は深溝(トレンチ) 、+41は電
極A1(5)は電極B 、 171はレジスト、(8)
は電属AB間距離LAB 、 +91ij深溝の深さt
、7 、 lo+ (Ill Q21 n RC溝(’
) RサL’rt t LT21LT3である。
なお、図中、同一符号は同一または相当部分を示す。[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a surface view of a resistance element according to an embodiment of the present invention, FIG. 2 is a cross-sectional side view along n-n line in FIG.
The figure is a cross-sectional view of deep grooves formed in a P-type silicon substrate, Figure 4 is a surface view of Figure 3, Figure 5 is a surface view of Figure @4 after resist patterning, and Figure 6 is a view of the resistor element of the present invention. An explanatory diagram, FIG. 7 is a cross-sectional view of a resistance element according to another embodiment of the present invention,
Figure 8 is a surface view of a conventional resistance element, and Figure 9 is the
-A cross-sectional side view taken along the X-ray, FIG. 10 is an explanatory diagram of a conventional resistance element. In the figure, (l) is a silicon substrate, 12) is an N-type impurity diffusion region, (3) is a deep groove (trench), +41 is electrode A1 (5) is electrode B, 171 is resist, (8)
is the distance between the metal AB, LAB, +91ij, the depth t of the deep groove
, 7, lo+ (Ill Q21 n RC groove ('
) Rsa L'rt t LT21LT3. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.
Claims (1)
る場合において、深溝(トレンチ)形成により、深さ方
向に折り曲げ、限られた表面面積内で深溝の数および深
溝の深さを調整することにより、所望の抵抗値を持つた
抵抗素子を形成したことを特徴とする半導体装置。When forming a resistance element using an impurity diffusion region of a semiconductor device, by forming a deep groove (trench), bending it in the depth direction, and adjusting the number and depth of the deep groove within a limited surface area. A semiconductor device characterized in that a resistive element having a desired resistance value is formed.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3883289A JPH02216860A (en) | 1989-02-16 | 1989-02-16 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3883289A JPH02216860A (en) | 1989-02-16 | 1989-02-16 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH02216860A true JPH02216860A (en) | 1990-08-29 |
Family
ID=12536200
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3883289A Pending JPH02216860A (en) | 1989-02-16 | 1989-02-16 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH02216860A (en) |
-
1989
- 1989-02-16 JP JP3883289A patent/JPH02216860A/en active Pending
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