JPH022162A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To improve programming characteristics and realize high speed reading by a method wherein first semiconductor regions are provided on the sides of gate electrodes to which data lines are connected and second semiconductor regions are provided on the sides of the gate electrodes to which grounding lines are connected and MISFET's are provided at cross points of data lines and word lines. CONSTITUTION:Word lines WL and data lines DL are extended from an X decoder 17 and a Y decoder 16 respectively. A memory cell Qm is composed of a MISFET having a floating gate electrode 5 and a control gate electrode 7. The cells Qm are provided at the respective cross points of the word lines WL and the data lines DL and connected to them. Among n<+>-type semiconductor regions 9 and 10 which are used as sources at the time of reading, the regions 9 are provided under the side walls 13 of the respective memory cells and the regions 10 are extended on the surface of a substrate 1 along the direction of the extension of the word lines WL. The n<+>-type semiconductor region 10 and a plurality of the memory cells on both the sides of the region 10 are formed into one body. Grounding lines SL are composed of the n<+>-type semiconductor regions 10 extended to the same direction as the word lines WL and the n<+>-type semiconductor regions 9 provided under the side walls 13.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor memory device, and in particular,
The memory cell is a MISFET (Metal In5) having a floating gate electrode and a control gate electrode.
ulator Sem1conduator Field
dEffect Transistor),
This is effective when applied to a semiconductor memory device in which information is written by injecting carriers into a floating gate electrode.

[Prior art]

EEPROM (Electronic Memory) is a type of non-volatile memory.
trlcally Erasable and Pro
gramnable ROM), and the technology in which the memory cell of this is configured with one MISFET having a floating gate electrode and a control gate electrode is
1985 FIED M-Technical Digest p616-619 (IEDMTechnl
cal Digest 1985 pp 616~
617). To write information into this memory cell, hot electrons are generated at the drain end by applying 12.5 V to the control gate electrode, 8 V to the drain, and Ov to the source, and flowing a drain current of, for example, 500 μAa. Hot electrons are injected into the floating gate electrode. On the other hand, information is erased by applying 12.5 V to the source and Ov to each of the drain and control gate electrodes to release the electrons in the floating gate electrode into the substrate. Do by doing.

However, the semiconductor memory device has a single power supply, that is, it does not require multiple types of t-sources to be supplied within the semiconductor chip.

For example, it has come to be only 5V, and the
．． High voltages such as 5Vf8V are now being generated by a booster circuit installed in a four-body chip.

However, since a booster circuit is composed of a diode and a capacitor, increasing the current capacity requires a large area, and the current capacity is usually 100 μA, which is small and chronic. Not enough supply and good -I! It is important to obtain the insertion characteristic.

Also, during erasing, it is necessary to apply a high voltage of 12.5V to the source, but since the breakdown voltage between the source and the substrate is small, there is a large leakage to the substrate, and a voltage as high as 12.5V is applied to the source. It was difficult to apply.

Therefore, the present applicant attempted to improve the write characteristics by providing a p+ layer in contact with and surrounding the drain, and also provided an n layer outside the n layer for the source to form a layer between the source and the substrate. We proposed a semiconductor memory device with high junction breakdown voltage (U,
S, 5etia: l f'h O53.

730) In this way, by providing the drain in the p+ layer, the electric field at the end of the drain on the channel side during injection becomes stronger, increasing the hot electron generation efficiency, and improving the sinking characteristics. can be increased. On the other hand, since the avalanche breakdown voltage between the source and the substrate is high, erasing characteristics can be improved by applying a high voltage of about 12.5 V to erase information.

[Problem to be solved by the invention]

In the semiconductor memory device filed by the present applicant based on studies by the present applicant, in a structure in which the drain is thrown into the p+ layer, writing is performed by injecting hot electrons generated at the end of the drain into the floating gate, and erasing is performed by injecting hot electrons generated at the end of the drain into the floating gate. It has been found that there are the following problems when performing tunnel emission to the source.

First, since the drain is provided in contact with the p+ layer,
The minimum voltage (threHold vol-tage) to be applied to the control gate necessary to form a channel between the drain region and the source region and conduction becomes higher, and the junction capacitance and (threHold vol-tage) at the drain increase
The speed of reading t decreases.

On the other hand, the breakdown voltage between the source and the substrate has been increased, but in order to increase the erase speed (in order to increase the erase speed), if the odor of the gate oxidation under the floating gate is reduced to less than 100 A, for example, if an erase voltage of 12.5 V is applied, It has been found that there is a leakage of about 101A for every 1 bit of memory cell.If the memory container is, for example, 1 megabit, and the data is erased all at once, the leakage during erasing can be as high as 1OA, which causes the voltage boost inside the semiconductor chip to rise. It is difficult to erase information using a circuit.Also, as the erasing operation progresses, the threshold tolerance voltage Vth of the memory cell decreases to When the temperature drops to near
er-Nordhe im) In addition to tunnel emission, hot hole injection from the semiconductor substrate to the floating gate electrode becomes significant, resulting in a problem that the controllability of the erase operation and the 1M reliability are impaired.

This situation will be briefly explained below using FIGS. 25 to 27.

25 and 26 are cross-sectional views of a memory cell, in which the p-type semiconductor substrate 1. Tunnel oxide film 2. Floating gate' electrode 3. - Insulation between 7 and 4. Control gate electrode5. n+ type semiconductor region (-m of source region
)6. n+ type semiconductor region (drain region)7. MISFE consisting of 8 n'''' semiconductor regions (part of the source region)
It is composed of T. control goo) 445. )
'L/in Wi area 7. By applying a high positive voltage vs to the source region 6 with the pq semiconductor substrate grounded, electron tunneling 9 occurs from the 70-teing gate electrode 3 to the source region 6, and an erase operation is performed.

At the initial stage of erasing, many electrons are held in the floating gate electrode 3, so no channel current flows even if a high voltage is applied to the source region 6.

As shown in FIG. 27, when the erasure progresses and the floating gate 'tIL pole 3 approaches an electrically neutral state, the channel current 10 increases due to the effect of the brutal coupling between the source region 6 and the floating gate electrode 30. It starts to flow. Due to this channel current 10, avalanche occurs in the high electric field region at the end of the source region, and some of the generated hot holes are injected into the tunnel oxide film 2 as shown by reference numeral 11.

Injection of hot holes accelerates the generation of interface states and significantly degrades the quality of the tunnel oxide film, which poses a major problem in terms of the reliability of the erase operation, including the number of times it can be replaced. .

Also, the injected hot hole is a floating gate! , the electron Fo is held at the pole and increases its potential.
The erase operation will proceed with the wler-Nordhelm tunnel emission. At this time, as shown in FIG. 27, the erasing speed is rapidly accelerated (120
Part> It becomes extremely difficult to maintain controllability of vth.

An object of the present invention is to provide a technology for increasing the speed of reading information in a memory cell consisting of an MI 5FET having a floating gate (Flff4) and a control gate electrode, and in which a thin tunnel oxide film is used instead of a gate oxide film. There is a particular thing.

Another object of the present invention is to improve write characteristics in the memory cell.

Another object of the present invention is to provide a technique that allows good writing and erasing to be performed in the memory cell using an external pressure circuit within a semiconductor chip.

Another object of the present invention is to provide a highly reliable electrical erasing method with little characteristic deterioration in erasing written information.

The above and other objects and novel features of the present invention will become apparent from the description of the present invention and the accompanying drawings.

[Means to solve the problem]

A brief summary of representative inventions among the inventions disclosed in this application is as follows.

That is, the memory cell consists of a MISFET having a floating group and a control gate electrode, and information is written from the substrate side through the gate insulator.
11. In the semiconductor memory device #, which is performed by injecting electrons into the floating gate voltage, writing is performed by connecting a predetermined high potential and a data knob to the second semiconductor region to which the grounding machine is connected. Information is erased by applying a predetermined low potential to the first semiconductor region and a predetermined high potential to the control gate electrode, and erasing information is performed by applying a predetermined high potential and a ground line to the first semiconductor region to which data is connected. A predetermined low potential is applied to the connected second semiconductor region and a predetermined low potential is applied to the control gate electrode. Information is read by applying a predetermined low potential to the connected second semiconductor region and the control gate electrode. This is done by using the second semiconductor region connected to as a source and applying a predetermined potential to the control gate electrode.

Further, a semiconductor region of an opposite conductivity type is provided at least at an end on the channel side of the second semiconductor region to which the grounding machine is connected, and the first semiconductor region to which the data line is connected has a low impurity concentration. It has a double structure in which a semiconductor region with a high impurity concentration is provided within a semiconductor region.

[Effect]

According to the above-described means, the junction capacitance between the first semiconductor region and the substrate connecting the data collar is reduced, so that the information reading speed can be increased.

Furthermore, writing is performed by applying a predetermined voltage to the ground line, and an opposite 4'lI type semiconductor region is provided at the channel side end of the second semiconductor region to which the grounding device is connected. , depletion) - is suppressed, and the generation rate of hot electrons is higher than when there is no semiconductor region of the opposite conductivity type at the channel side end of the seedling half-body region. can be increased.

In addition, since information is erased data by data, the number of memory cells that are erased at one time is small, which reduces leakage current, so the voltage generated by the booster circuit built into the semiconductor chip is reduced. You can erase it with .

In addition, a second half to which a predetermined high potential is applied during feeding;
The presence of a semiconductor region of the opposite conductivity type at the end of the donor region on the channel side increases the generation rate of hot electrons and lowers the floating voltage. It can be carried out.

Further, when erasing information, a predetermined high potential is applied to the first.
Since the semiconductor region has a 2M tough structure with a high concentration layer in the low leakage layer, the breakdown pressure with the substrate is high, so a high potential can be applied.
Therefore, the erase characteristics by tunneling can be improved.

〔Example〕

Hereinafter, embodiments of the present invention will be explained.

The circuit configuration of the memory cell array will be explained using FIG.

FIG. 1 is a circuit diagram of an EEPROM memory cell array.

In FIG. 1, 17 is an X decoder, 16 is an X decoder, 23 is a write/erase control path, 24 is a write/erase circuit, and 25 is a sense amplifier. Word f#WL extends from X decoder 16, and data DL extends from X decoder 17, respectively. Qm is a memory cell consisting of an MI 5FET having a floating gate electrode 5 and a control gate electrode 7. Memory cell Qm has respective word #WL and data DL
and are connected as shown. S
L is a ground line, which extends in the same direction as the word line WL. Qs is a source MISFET for applying a write voltage, and a voltage of, for example, 5V is applied to the ground #5LICVa6 when writing information.

For l megabit EEFROM, one data sDL
For example, a 1024-bit memory cell Qm is connected to.

Next, the read operation and write operation of information in the memory cell Qm will be explained using FIG. 2, and the erase operation will be explained using FIG. 2, FIG. 3, and FIG. 4.

FIG. 2 is a diagram for explaining the information read operation, filling operation, and erasing operation of the memory cell Qm, and FIGS. 3 and 4 are diagrams for explaining other erasing operations. , only four memory cells Qm are shown.

8 in FIG. 2, Qat is a P-channel MISFET, Qpt e QDt e Qat e Q
Ws *Q W4 e Qws # Qat #
Qat@QeseQ71#Qyt is an N-channel MISFET. MISFE TQw+t
Qwt s Q”s # Q e+ p Q
at is provided in the write/erase control circuit 23, and M I S F ETQ Qs p Qyt
j Q)'*aQW4#QWsp is provided in the pledge/erase circuit 24. In addition, Qst
e Qat is composed of a depressurized 7 type N-channel MISFET a Vac*vpP-V
pzs Wl, Wl.

W, , E, , E, , D are terminals, respectively.

A data input signal is applied to the terminal r when writing information.

In the following operation description, four memory cells Q m t~Q
Among m 4, memory cell Q m t is X decoder 1
The following description will be made assuming that the memory cells Qmt to Qm4 are in a selected state by the memory cell 7 and the X decoder 16, and the other memory cells Qmt to Qm4 are in a non-selected state.

[Reading operation]

The terminal V66eVpp and VPE have a power supply voltage of, for example, 5v.
Apply. The X decoder 17 sets the word line WL1 to, for example, 5V, and the word line WLt to, for example, Ov. Also, MISFETQy,
is in ON state, MISFET Q)'! is OFF・
has been in a state. Further, the terminal WD is set to, for example, Ov, the terminals W and %W are set to, for example, 5V, and the terminals E and E are set to, for example, Ov.

As a result, M I S F E T Q o I,
M I S F ETQ DI, M I S F
E T Qat is OFF% MISFE T Q Wl
, Q ws , Q W4 are ON1MISFETQ6t
, Qes is turned OFF. In addition, since the terminal line is set to Ov at the time of reading, MISFETQw- is OFF. At this time, since MISFETQs and -QWs are ON, the ground asL becomes Ov, for example. Therefore, the potential changes depending on the information written in the memory cell Q m I ? Determination is made by sense amplifier SA.

[Pushing operation]

For example, 5■ is applied to the terminal VPP. X decoder 17
A boosted voltage, for example, 12.5 V is applied to the word il $ W L i )Ls word line WL, for example, Ov
is applied. On the other hand, the Y decoder 16
si'E'rqy is ON, and MISFETQ y t is 0FFK. Further, the terminal WD is, for example, 5■, and the terminal W is, for example, Ov%W! For example, 12.5 V%Ws
For example, 5V, E, and E are set to OV, for example. This allows MI 5FETQot, Qnz and M
I S F E T Qwt # QW! is ON-Qw
s becomes OFF. Also, MISFET Qel, Qe
a is OFF and h. Also, MISFETQw,
is ON. Further, vac is 5v. here,
In order to write, a data input signal, for example 5V, is applied to the data input terminal, and the MISFET Qws t”O
NK.

At this time, since M I S F E T Q'/I and QW4 are ON, only DL of all the data DL becomes Ov, for example. On the other hand, since word line WL1 is set to 12.5V, for example, MI
SFETQal turns ON and kiIsFETQW+
* Ground 1JsL, K, for example 5v, is applied through Qwt, Qli. As a result, memory cell Q m +
When writing information, current flows from the drain (source when reading) to the source (drain when reading), and convolution is performed. In addition, data #)D
Lt IIC ha M I S F E T QD! is 0
N1Q)'! is OFF, so for example 3.5
v is applied. As a result, unselected data will not be turned on during the write operation, so that the unselected memory cell Qm will not be erroneously written.

[Erase operation]

First, the operation of embedding information in the memory cell Qm will be explained using FIG.

Terminal Vpg VC7ft constant boosted potential, e.g. 12.5V
is applied. The X decoder 17 decodes all words di
In addition, the Y decoder 16 outputs MI 5FETQ7.
For example, if 12.5V is applied to the gate of 'RL', MI
5FETQ) For example, OV is applied to the 'gate' electrode.

Further, for example, 5V is applied to the terminal VPPe vcc, and the terminals WD and W1 to W Hatake are set to OV. Also, for example, 5V is applied to terminal E, and terminal E! For example, 12.5V is applied to t6. Ko(D) knee@, MISFETQw4 and QW
s is OFF, and MIS FET
Q 3' Ia Q 7! Only Qyl is ON
Therefore, a predetermined high potential, for example, 12.5V, is applied only to DL of the data iD Lt and D Lm, and the memory cell Q connected to this data DL is
The information of only m, , Qmm is erased. In addition, other data DL! Memory cell Qm* connected to
, Qm4 information is erased by MISFE in the Y decoder 16.
By selecting TQ)'t, the same procedure as above is performed. Also, when erasing Qmt to Qm4 at the same time,
M I S F ETQ)'t in the Y decoder 16,
Q) Select '* at the same time. In the above explanation, the terminal VP
P is the same voltage as VCC, for example 5V, and the high voltage during writing and erasing is boosted by an internal circuit, but it is also possible to apply it from the outside. In this case, terminal VPP
For example, 12.5V is applied.

In order to suppress the injection of hot holes into the floating gate electrode, which occurs as the erasing operation progresses, to a low level, the following erasing method may be used. In the circuit shown in FIG. 3, the erasing method described in FIG. Terminal V p
For example, Ov is applied to the gate electrode of I#MISFETQyl, eg, 12.5V MISFETQy. Also, the terminal VPP,
For example, 5V is applied to VCC, and the terminals WD, WI~W
, is OVK tf6. When 12.5V, for example, is applied to the terminal B, the knee, tf, a predetermined high potential, for example 12.5V, is applied to the data DL, and the memory cells Qm, ,Q
ms information is erased. At this time, MI SFE
TQw, , Qws are OFF, that is, the ground connected thereto, including the ground SL and the semiconductor region connected to SL, are in a floating state. By doing this, the potential of the drain region increases due to the channel current that begins to flow as erasing progresses, and this works in the direction of decreasing channel 1m, so even if erasing progresses, hot hole generation and injection can be kept at a low level. This improves the erasing characteristics. Furthermore, as shown in FIG. 4, the same erase potential Vpz may be applied from both the DL line and the ground line with both MISFETs Qyt and Qyt turned on. By doing this, even if the erase operation progresses, the channel current will not change. Since there is no flow, undesirable hot hole generation and injection phenomena can be avoided.

Next, the structure of the memory cell of the first embodiment will be explained.

FIG. 5 is a plan view of a part of the memory cell array, and FIG. 6 is a cross-sectional view taken along the line AA in FIG. 5. In addition, in FIG. 8g5, in order to make it easier to understand the structure of the memory cell, insulation films other than the field insulating film are not shown.

In FIGS. 5 and 6, 1 is a substrate made of single crystal silicon, 2 is a field insulating film, and 3 is a P-type channel stopper.

The number of MISFETs constituting one memory cell is 10.
A first gate electrode film 4 having a film thickness of about 0 A, a floating gate electrode 5, a second gate film 6 having a film thickness of about 250 A, a control gate electrode 7, an n+ type semiconductor serving as a source and a drain. It consists of a region 9, an n+ type semiconductor region 10, and an n type semiconductor region 12. The first gate insulating film is made of a silicon oxide film formed by thermally oxidizing the second surface of the semiconductor substrate 1, for example. floaty/
For example, X&5 is made of polycrystalline silicon. The second gate insulation id6 is made of a silicon oxide film formed by thermal oxidation on a different surface of the polycrystalline silicon film that is the floating gate electrode 5, and has a film thickness of 250 to 350 hs degrees. The control gate (IM) and pole 7 are made of a two-layer film in which a high melting point metal silicide film such as WSt is formed on a polycrystalline silicon film. Further, the control gate electrode 7 is integrally formed with the word @WL.

n+ type semiconductor regions 9 and 10 on both sides of gate electrodes 5 and 7
Of these, the n+ type semiconductor regions 9 and 10 to which the data DL is connected through the connection hole 15 have ends defined by the gate electrodes 5 and 7 in the direction in which the data and DL extend. or is defined by a sidewall 13 made of silicon oxide. The end portion in the direction in which the word 1jWL extends is defined by the field insulating film 2. In this way, the n+ type semiconductor region 9. below the connection hole 15. IO is provided separately for each connection hole 15.

Also, the n+ type semiconductor region 9°10 below this connection hole 15
is an n-type semiconductor region (semiconductor region with low impurity concentration) 12
It is located inside. Therefore, nu semiconductor region 1
2 also has a gate electrode 5.7 and a field insulating film 2 on both sides of the contact hole 15, similar to the n+ type semiconductor region 9°10.
It is provided for each area enclosed by. n+ type semiconductor to which the data line DL is connected 9. The lO and n-type semiconductor regions 12 serve as drains when reading and erasing information, and are used as sources when storing information. -! t,n+
The type semiconductor region 10 and the n-type semiconductor region 12 are shared by two memory cells connected to the same data #DL through one connection hole 15.

At both ends of the n+ type semiconductor region 10 to which the data mDL is connected, 70-
An n + -type semiconductor region 9 is provided so as to extend under the covering gate pole 5 . The length of the n + cleft semiconductor region 9 in the channel length direction is defined by the sidewall 13 .

On the other hand, the n+ type semiconductor regions 9 and 10 on the opposite side of the gate electrodes 5 and 7 to which the data line DL is connected are used as sources when reading information and as drains when storing information. When erasing information, a predetermined low potential, for example Ov, is applied, but it is not used as a source.Among the n+ type semiconductor regions 9 and 100 that become sources during reading, the n+ type semiconductor region 9 is applied to each memory cell. It is provided under the side wall 13, and is slightly inserted under the floating gate (fb) and pole 5. However, the n+ type semiconductor region 10 extends on the surface of the substrate 10 in the direction in which the word line WL extends, and has a structure in which the n+ type semiconductor regions 10 of a plurality of memory cells on both sides are integrally formed. ing. And this word +J
The n+ type semiconductor region 10 extending in the same direction as WL and the n+ type semiconductor region 9 provided under the sidewall 13 form a ground fat SLt-m. This ground wire SL
A P + -type semiconductor region 11 is provided so as to surround the periphery and bottom of the n + -type semiconductor region 9j 10 . Therefore, P+ type semiconductor region 11 also extends in the direction in which word +WWL extends. However, the P+ type semiconductor region 11 does not necessarily have to be provided over the entire bottom of the n◆ type semiconductor regions 9, 100, but may be provided at the end of the n+ type semiconductor region 9 on the channel side.

The depth from the top surface to the bottom of the n+ type semiconductor region 9 (hereinafter referred to as junction depth) is about 0.1 to 0.2 μm, n+
The junction depth of the type semiconductor region 1o is about 0.2 to 0.3 μm, and the junction depth of the n-type semiconductor region 12 and the P + type semiconductor region 11 is about 0.4 to 0.6 μm.

Field insulation jμ2 and floating gate electrode 5
The semiconductor substrate 10 exposed from above, the side surface of the floating gate electrode 5 and the control gate electrode 7
The side and top surfaces of are covered with a thin silicon oxide film 8. Reference numeral 14 denotes a layer-interlayer film constructed by laminating, for example, a phosphosilicate glass (PSG) film on a silicon oxide film. The data mDL is of the aluminum family.

Incidentally, in order to reduce the junction capacitance between the drain and the substrate 10 when reading information, the drain during reading may be formed only of the n-type semiconductor region 12.

On the other hand, n+ type semiconductor regions 9 and 10 forming the ground asL
Although the 0 side is provided in the P+ type semiconductor region 11, it is also possible to omit this P+ type semiconductor region 11 and form the grounding and I#SLt-m only with the n+ type semiconductor regions 9 and 10. can. However, in this embodiment I, a P+ type semiconductor region 11 is provided in order to improve the efficiency of writing information.

Therefore, the following three types of memory cells can be configured.

In the memory cell of the first column, the semiconductor region to which data DL is connected, that is, the drain at the time of reading, is connected to the n-type semiconductor region 1.
2! On the other hand, n+ which is grounded #SL
P+ type semiconductor region 1 surrounding type semiconductor regions 9 and 10
1 should not be provided.

In the second memory cell, the drain when reading information is composed of n+ type semiconductor regions 9 and 10, and the n type semiconductor region 1
2 should not be provided. Further, a P+ type semiconductor region 11 is provided around the n+ type semiconductor region 9°lO constituting the grounding leg S Lt-.

In the third memory cell, the drain when reading information is made up of only the n-type semiconductor region 12, while the P+-type semiconductor region 11 is formed around the n+-type semiconductor region 9°10 that makes up the ground aSL. establish.

Note that the structure of the memory cell shown in FIGS. 3 and 4 is as follows:
It can be applied not only to EEPROMP but also to EPROM. In EPROIVI, information is erased by irradiating the channel region of the memory cell with ultraviolet light.

The following effects can be obtained from the configuration of the memory cell described above.

First, the effects of the structure of the first type memory cell will be described.

Memory cells are stacked on the substrate 1 (floating/groove)? tLk5 and control cat electrode 7,
A first semiconductor region (n/
.
ET, and the MISFET has each data D.
The first semiconductor region (1st layer 12) is connected to the data @DL, and the second semiconductor region (n+10th layer, 10) is connected to the # grounding line SLK. The control gate electrode 7 is a semiconductor memory device connected to the word #WL, and the control gate electrode 7 is connected to the m1 semiconductor region (1
The impurity concentration of the second semiconductor region (layer 12) is set to
0) lower than the ground ffs
The second semiconductor region (n”r#9,1
0), a predetermined high potential (for example, 5), a predetermined low potential (for example, OV) to the first semiconductor region (1 layer 12) to which the data internal DL is connected, and a predetermined high potential, for example, 12 to the front control gate electrode 7. The information is read by applying .5V to the first semiconductor region (1) to which the data DL is connected.
By using the layer 12) as a drain and the second semiconductor region (n+ layer 10) to which the ground line SL is connected as a source, and applying a predetermined potential, for example, 5V to the control gate electrode 7, ・n+ The drain at the time of writing, that is, the ground ai, is composed of type semiconductor regions 9 and 10.
The electric field at the end of the channel side of sL is stronger than when the drain structure is an n-layer structure like the semiconductor region on the data side during writing, and hot electrons can be generated efficiently. Characteristics can be enhanced. Furthermore, by connecting the drain, that is, the n-type semiconductor region 12, to the data DL during reading, the capacitance attached to the data can be reduced, so that the reading speed can be increased.

Next, the effects of the structure of the second type of memory cell will be described.

The memory cell includes a floating gate electrode 5 and a control gate electrode 7 provided overlappingly on the substrate 1, and a first semiconductor provided on the side of the surface of the substrate 10 where the data DL of the gate electrodes 5 and 7 are connected. area (this is n”/
The combination of i#9 and i#10 is simply the first semiconductor region.

) and a second semiconductor region provided on the side to which the ground line SL is connected (this is simply the second semiconductor region together with n''/QJ9.10).
The MISFET is arranged at the intersection of each data aDL and word @WL, the first semiconductor region (n+10 layer, 10) is connected to the data #DL, and the second semiconductor region (n layer 9.10) The grounded fiIS
The control gate electrode 7 is connected to the word line WL.
a semiconductor memory device connected to the channel side end of the second semiconductor region (n+10 layers,
and a sixth semiconductor region (p
+10 layers 1) are provided, and the information is transmitted through the ground wire SL.
The second semiconductor region (n+10 layer, 10) to which the data DL is connected is set to a predetermined high potential, for example, 5V, and the first semiconductor region (n+10 layer, 10) to which the data DL is connected is set to a predetermined low potential (for example, Ov). ), the control gate 't! A predetermined high potential, for example, 12.5 V, is applied to the L pole 7, and the information is read by using the first semiconductor region (n+10 layer, 10) in 110 as the drain, and the second semiconductor region connected to the ground line SL as the drain. By using the semiconductor region (n middle layer 9.10) as a source and applying a predetermined potential, for example 5V, to the control gate electrode 7, the electric field at the drain, that is, the channel side end of the ground line SL during writing is It is much stronger than when the p+ layer 1 is not provided, so that the write characteristics can be improved. Furthermore, since the p-type intermediate layer 11 is not in contact with the drain during reading, the junction capacitance with the substrate 1 is reduced, making it possible to speed up reading.

Next, the effects of the structure of the third cypress memory cell will be described.

A memory cell is provided on the side where the data MDL of the gate electrodes 5 and 7 on the surface of the substrate 1 are connected to the control gate electrode 7 and the 70-bit gate electrode 11m5 provided in a dished manner on the substrate 1. The first semiconductor region (layer 1 12) and the second semiconductor region provided on the side to which the ground object SL is connected (this is simply the second semiconductor region, including the n+10 layers and 10). The MI 5FET is arranged at the intersection of each data line DL and word line WL, and the first semiconductor region ((
The n-layer 12) is connected to the data i DL and the second
The semiconductor region (n+ layers 9, 10) is connected to the ground line SL, and the control gate electrode 7 is connected to the word line WL.
The first and second
A sixth semiconductor region (p+ layer 11
), and information is written by applying a predetermined high potential, for example, 5V, to the second semiconductor region (n+ layer 9.10) to which the ground line SL is connected, and applying a first semiconductor region (n+ layer 9.10) to which the data iDL is connected. layer 12) at a predetermined low potential (for example, OV), and the control gate electrode 7 at a predetermined high potential, for example, 12
．． 5V is applied, and information is read by using the first semiconductor region (n layer 12) as the drain, the second semiconductor region (n+ layer 9, 10) connected to the ground dsL as the source, and reading the information. By applying a predetermined potential, for example 5V, to the control gate electrode 7, the electric field at the drain when * is included, that is, at the end of the channel side of the ground line SL, becomes p+
Since the strength is much stronger than when the layer 11 is not provided, the write characteristics can be improved. Also%! Since the junction capacitance between the drain, that is, the n-type semiconductor region 12 and the substrate 1 during e'e protrusion is reduced, read speed can be increased.

Next, effects other than those described above of the memory cells in the first to third blocks will be described.

When information is erased for each data store DL or several data storage DLs, the n-type semiconductor region 12 (or n+ layer 9, 10 of each memory cell to which the data DL is connected) is deleted.
) by applying a predetermined high potential, for example, 12.5V, the leakage current that leaks into the substrate 1 during one erasing operation is reduced, so erasing is performed using a booster circuit with a white value on the semiconductor chip. be able to.

In addition, data mD can be erased using a Y decoder.
Since the data line is selected and an erase voltage is applied to the multiple memory cells connected to the data line, a source line decoder is not required to select the source line required for erasing using the source line. Therefore, the chip size does not increase.

In addition, a second
With the semiconductor region in a floating state, a positive high voltage V is applied to the first semiconductor region provided on the side to which data is connected.
When information is erased by applying , the potential of the 70-ting gate electrode rises with the erase operation, and even if the erase progresses to a state where an inversion channel begins to be formed under the floating gate electrode, a steady state remains. No channel current flows, and as a result, generation and injection of hot holes caused by the channel current are suppressed. This prevents a sudden increase in erasing speed, making it possible to realize an erasing operation with high controllability. Furthermore, since deterioration of the quality of the tunnel oxide film due to hot hole injection is suppressed, it is possible to realize an erase operation with high reliability such as the number of rewrites possible.

In addition, since the semiconductor region to which a predetermined high voltage is applied during the erase operation is the n-type semiconductor region 12 with a low concentration of unobservable objects, the junction breakdown voltage with the substrate 1 is high, and leakage per memory cell is reduced. Current can be reduced.

Furthermore, by providing the n+ type semi-2.1 body region 9.10 in the nm#- conductor region 12, the resistance value of the drain when reading information can be reduced, so that the reading speed can be increased. I can figure it out. Furthermore, in the EEPROM, information can be erased faster.

Further, by providing the n+ type semiconductor region 9 with a shallow junction depth at the channel side end of the n+ type semiconductor region 10 on both sides of the gate electrodes 5 and 7, the floating gate 'a@! , 5 becomes smaller, and the capacitance between the floating gate electrode 5 and the floating gate electrode 5 can be reduced. This makes it possible to increase the read speed.

Furthermore, by providing the n+ type semiconductor region 10 with a deep junction depth in both the drain and the ground line SL during reading, the resistance values of the drain and the ground line SL can be lowered. From now on, it is possible to increase the speed of each write, read, and erase operation.

Next, a method for manufacturing the mesoricell shown in FIGS. 5 and 6 will be described.

7 to 20 are cross-sectional views or plan views of the same portion of the memory cell as shown in FIG. 6 during the manufacturing process.

First, as shown in FIG.
A silicon oxide film 18 is formed by chemical vapor deposition, and on this silicon oxide film 18 is formed by CVD.
A silicon nitride film 19 is selectively formed. Field insulating film 2 is formed by thermally oxidizing the top surface of semiconductor substrate 1 using silicon nitride film 19 as a mask. The p-type channel stopper 3 is formed by implanting a p-type impurity such as boron (I) by ion implantation using the silicone film 19 as a mask before forming the field insulating film 2.
on implantation). After forming the field insulating film 2, the silicon nitride film 19 and the silicon oxide film 18 are removed.

Next, as shown in FIG. 8, the surface of the substrate 1 exposed from the field insulating film 2 is thermally oxidized to form a first gate insulating film 4 having a thickness of about 100 Å.

Next, as shown in FIG. 9, in order to form the floating gate electrode 5, the entire surface of the semiconductor substrate 1 is covered with, for example, carbon dioxide.
A polycrystalline silicon film 5 is formed by VD. In order to reduce the resistance of the polycrystalline silicon film 5, an n-type impurity such as phosphorus (P) is introduced by thermal diffusion, ion implantation, or the like.

Next, as shown in FIG. 10, the polycrystalline silicon film 5 is
By etching using a resist film (not shown) as a mask, the floating gate electrodes 5 are patterned to extend at predetermined intervals in the direction in which data +l D L extends. In other words, in this etching process,
Polycrystalline silicon 5 is patterned into a pattern that integrates the floating gate electrodes 5 of a plurality of memory cells connected to the same data and IDL. Polycrystalline silicon! After patterning JE5, the mask made of the resist film is removed.

Next, as shown in FIG. 11, the surface of the polycrystalline silicon film 5 is oxidized to form a second gate insulating film 6 made of a silicon oxide film. The film thickness is about 200 to 250A. A gate insulating film of MISFET constituting the peripheral circuit in this oxidation step is formed.

2) In order to form the electrode 7 and the word hawk WL, a polycrystalline silicon pattern 7 is formed on the entire surface of the semiconductor substrate 1 by, for example, CVD. In order to reduce the resistance of the polycrystalline silicon pattern 7, an n-type impurity such as phosphorus is introduced by thermal diffusion, ion implantation, or the like.

Next, as shown in FIG. 12, the control gate electrode 7 is etched by etching the polycrystalline silicon film 7 using a mask made of resist 1 (not shown).
and form a word warabi WL.

In this etching process, the gate electrode of MISFET in the peripheral circuit is also formed. Following the etching, the second gate insulating film 6 exposed from the floating gate electrode 7 is etched, and the polycrystalline silicon film 5 is etched to form the floating gate electrode 5. After this series of etching, the mask made of resist film is removed.

In addition, control gate electrode l pole 7, word, gland WL
The gate insulating film of the MI 5FET in the peripheral circuit is Mo.
, W, Ta, TI, etc. or its silicide film or polycrystalline silicon film. A#
Alternatively, it may be a 2N film with an IJ layer of silicide layers.

Next, as shown in FIG. 13, the floating gate electrode 5 and the control gate electrode 7 (word; 汲WL)
The exposed surface of the silicon oxide is oxidized by pA to form silicon oxide. Due to this oxidation, the floating gate electrode 5
The surface of the semiconductor substrate 10 exposed from the control gate electrode 7 is oxidized to form a silicon oxide film 8.

Next, as shown in FIG. 14, p+
Mask 2 made of a resist film for forming type semiconductor region 11
Next, a p-type impurity, such as boron, is added to the surface of the semiconductor substrate 10 by ion implantation to form 10" to 10".
About 4 atoms/cr/l are introduced. After removing the mask 20, annealing is performed to obtain a 0.4 to 0.6
The p4p type semiconductor region 11 is formed by diffusion to a junction depth of about μm.

Next, as shown in FIG. 15, a mask 21 made of a resist for forming an n-type semiconductor region 12 is formed on the substrate 1.Next, an n-type impurity, for example, is added to the surface of the substrate 1 by ion implantation. Phosphorus is introduced at a dose of about 10'' atoms/atl. Thereafter, the mask 20 is removed and the n-type semiconductor region 12 is formed by annealing to a depth of 0.4-0.6 μm.

Next, as shown in FIG. 16, using the floating gate electrode 5 and the control gate electrode 7 as masks, an n-type impurity, such as hydrogen, is implanted into the surface of the semiconductor substrate 10 by ion implantation at a dose of about 10 to 10'' atoms/crIl. The n+ semiconductor region 9 is formed by introducing the n+ semiconductor region 9.
During this ion implantation, the peripheral circuit area is covered with a mask made of resist d so that ions are implanted only into the memory cell area, and the memory cell area is further covered with a mask made of a resist film to inject n-type impurities into the peripheral circuit area. Example Eva I
By implanting ions of about 10" atoms/c11, the source and drain regions t-LDD of the N-channel MISFET that constitutes the peripheral circuit are
(Lightlly Doped Drain)
It can also be made into m-structure. In this case, the mask made of a resist film provided in the peripheral circuit area is removed after ion implantation.

Next, as shown in FIG. 17, a silicon oxide film 12 for forming a sidewall 12 is formed on the entire surface of the semiconductor substrate 1 by, for example, 4D.

Next, as shown in FIG. 18, the silicon oxide film 12 is etched by reactive ion etching (RIE'') until the surface of the semiconductor substrate 10 is exposed.
- MI for configuring the 0 peripheral circuit that forms the module 12
A side wall 12 is also formed in the 1ll11 portion of the gate electrode of the 5FET. The surface of the semiconductor substrate 10 exposed by the etching is oxidized again to form a silicon oxide film 8.

Next, as shown in FIG. 19, using the floating gate electrode 5, the control gate' electrode 7, and the side wells 12 as masks, an n-type impurity such as arsenic is implanted by ion implantation in an amount of, for example, 5 x 10'' to I x 10.
The n+ type semiconductor region 10 is formed by introducing at a dose of about atoms/-. In this ion implantation step, high concentration layers for the source and drain regions of the N-channel MISFET in the peripheral circuit are also formed.

Note that the region where the P-channel MI 5FET of the peripheral circuit is formed is covered with a mask made of a resist film to prevent the n-type impurity from being introduced. The mask made of this resist film is removed after ion implantation. N
After forming the channel MI 5FET, although not shown, the N-channel MISFET region and memory cell region of one peripheral circuit are memorized using a mask made of a resist film.
P-channel MISFE of peripheral circuit by ion implantation
A p-type impurity, such as boron, is introduced into the T region to form the source and drain regions of the P-channel MI 5FET. N
A mask made of a resist film covering the channel MI 5FET and the memory cell region is removed after introducing the P-type impurity.

Next, as shown in FIG. 20, an insulating film 13 made of P S Gd is formed on the entire surface of the semiconductor substrate 1 by, for example, CVD.
form. After this, data #D consisting of the connection hole 14 shown in FIGS. 1 and 2, aluminum, l, % 15
L, final protection not shown;

As explained above, according to the manufacturing method of this example,
Between the N-channel MI 5FET that constitutes the peripheral circuit and the line.
Memory cells can be formed in a process.

The drain when reading information may be composed of an n + -type semiconductor region 10 and an n-type semiconductor region 12 as shown in FIG. It is about 10 atoma/d. This makes it possible to make the gradient of impurities in the drain very gentle during reading, and to increase the drain junction breakdown voltage.

Note that the junction depth and other structures of each semiconductor region are the same as in the previous embodiment.

FIG. 22 is a sectional view of a memory cell according to another embodiment of the present invention.

In this embodiment, the n+ type semiconductor region 9 constituting the ground @SL
, 10 is eliminated, and a p+ type semiconductor region 22 is provided in the channel region. In contact with area 12, and also on the ground side S
It is provided in contact with the n+ type semiconductor region 9 forming the L. p+
The concentration of nel Il compound (boron) in the type semiconductor region 22 is 1
It is about 011-10 atoms/all.

In this configuration, the n-type semiconductor region 12 increases the breakdown voltage of the junction between the semiconductor substrates l.

Further, the p+ type semicircular region 22 can strengthen the electric field applied to the end of the drain region when writing information. On the other hand, the junction capacity of the ground line SL with the semiconductor substrate 1 can be reduced.

FIG. 23 is a sectional view of a memory cell according to still another embodiment of the present invention.

In this embodiment, the drain during readout is composed of only the n-type semiconductor region 10 and the n-type semiconductor region 12, and the ground line S
It is composed of only an L (source) tn+ type semiconductor region 10. The junction depth of the n+ type semiconductor region 10 of the drain and ground line SL is set to about 0.3 μm to ensure that the drain and ground line SL go under the floating gate electrode 5. Thereby, the amount of overlap with the floating gate electrode 5 becomes stable, and information writing and erasing characteristics can be improved. The n+ type semiconductor region 10 constituting the ground line SL is provided in the p+ type semiconductor region 11 to increase writing efficiency.

The 24th item is a cross-sectional view of a memory cell according to still another embodiment of the present invention.

In this embodiment, the drain at the time of reading is composed only of the n-type semiconductor region 12. This configuration reduces the overlap capacitance between the drain and floating electrode 5 during reading. This makes it possible to increase the speed at which information is read.

Although the present invention has been specifically explained above based on Examples, the present invention is not limited to the above Examples.
It goes without saying that various changes can be made without departing from the gist of the invention.

〔Effect of the invention〕

A brief explanation of the effects of typical inventions disclosed in this application is as follows.

(1) A memory cell includes a floating gate electrode and a control gate electrode provided overlappingly on the substrate, and a first semiconductor region provided on the side of the surface of the substrate 10 to which data of each of the gate electrodes is connected. , a second semiconductor region provided on the side to which the grounding is connected.
ISF"ET, the MI SFEτ is arranged at the intersection of each data and word line, and the MISFET is arranged at the intersection of each data and word line.
A first semiconductor region of ET is connected to the data and the g
c2 is a semiconductor memory device in which the semiconductor region is connected to the ground, and the control gate electrode is connected to the word line, wherein the impurity concentration of the first semiconductor region is lower than that of the second semiconductor region; This is done by applying a predetermined high potential to the M2 semiconductor region to which the ground line is connected, a predetermined low potential to the first semiconductor region to which the nine terminals are connected, and a predetermined high potential to the control gate electrode. For reading, the first semiconductor region connected to the data is used as a drain, the second semiconductor region connected to the ground voltage is used as a source, and the control gate ? [By applying a predetermined potential to IM, the electric field at the end of the drain (ie, ground) gland on the channel side becomes stronger during writing, so the writing characteristics can be improved. In addition, since the junction capacitance between the drain, that is, the n-type semiconductor region, and the substrate during reading becomes small, reading can be performed at high speed.

(2) A first semiconductor region in which the memory cell is provided on the side where the floating gate electrode and control gate electrode, which are provided overlappingly on the substrate, and the data of the respective gate electrodes on the surface of the substrate are connected. and a second semiconductor region provided on the side to which the ground line is connected.
The MISFET is arranged at the intersection of each data and word line, the first semiconductor region is connected to the data line, the second semiconductor region is connected to the ground source, and the control gate electrode is connected to the ground source. In a semiconductor memory device connected to a word line, a sixth semiconductor region having a conductivity type opposite to that of the first and second semiconductor regions is provided at an end of the second semiconductor region on the channel side, and writing information is performed by: This is performed by applying a predetermined high potential to the second semiconductor region to which the ground line is connected, a predetermined low potential to the first semiconductor region to which data is connected, and a predetermined high potential to the control gate electrode. The readout is performed by using the first semiconductor region as a drain and the second semiconductor region connected to the grounded rice as a source, and applying a predetermined potential to the control gate electrode. Since the electric field at the end of the ground cliff on the channel side becomes much stronger than when the sixth semiconductor region is not provided, write characteristics can be improved. Furthermore, since the junction capacitance between the drain, that is, the n-type semiconductor region, and the substrate during reading is reduced, reading can be performed at higher speeds.

(3) 70- in which memory cells are provided overlappingly on the substrate
A first semiconductor region provided on the side where the data of the gate electrode and the control gate electrode on the surface of the substrate are connected, and a second semiconductor region provided on the side where the ground leg is connected. MIS composed of semiconductor area
The MI 5FET is arranged at the intersection of each data and word line, and the first semiconductor region is connected to the data! 'j! Ic connection, the second semiconductor region is connected to the ground rod, and the control gate electrode is connected to the word line. A sixth semiconductor region having a conductivity type opposite to that of the second semiconductor region is provided, and information is written at a predetermined high potential to the second semiconductor region connected to the ground layer, and to the first semiconductor region connected to the data. A predetermined low potential and a predetermined high potential are applied to the control gate electrode, and information reading is performed by using the first semiconductor region as a drain and the second semiconductor region connected to the ground as a source. By applying a predetermined potential to the control gate electrode, the electric field at the channel side end of the drain, that is, the ground line during writing, is
Since the strength is much stronger than when no semiconductor region is provided, the write characteristics can be improved. In addition, since the junction capacitance between the drain, that is, the n-type semiconductor region, and the substrate during reading becomes small, reading can be performed at high speed.

[Brief explanation of the drawing]

FIG. 1 is an equivalent circuit diagram of an EEFROM memory cell array. FIGS. 2 to 4 are diagrams for explaining information write operation, read operation, and erase operation of memory cells. The fifth factor is: 61 is a plan view of a part of the memory cell array according to the first embodiment of the invention; FIG. ? Directions, Figures 7 to I! 20 is a cross-sectional view of the manufacturing process of a memory cell according to the first embodiment of the invention, FIGS. 21 to 24 are cross-sectional views of other memory cells of the present invention, and FIGS. 25 and 26 are FIG. 27 is a sectional view of a memory cell illustrating the problems of the conventional erasing method. FIG. 27 is an erase characteristic diagram of the conventional erasing method. In the figure, 1... Semiconductor substrate, 2... Field insulating film, 3... Channel stopper region, 4... First gate block film, 5... 70-Ting gate outside, 6...・・・
second gate insulating film, 7... control gate electrode,
8... Silicon oxide film, 9, 10... n+ type semiconductor region, 11... P+ type semiconductor region, 12... n type semiconductor region, 13... side wall spacer, 14...
... Insulating film, 15... Connection hole, 16.17... Decoder, 18... Base film (silicon oxide d), 19...
・Thermal oxidation mask (silicon nitride film), 20.21...
Resist group, 22...P+ type semiconductor region, 23.24
...Writing, erasing circuit, 25...Sense amplifier,
Qm...memory cell, DL...data, V, WL・
・・Word border, SL・・Contact number ■ Diagram concave diagram I 1 1st Ward Jiungin (appointment side 1)

Claims (1)

[Claims] 1. A semiconductor substrate of a first conductivity type, a floating gate electrode provided over the substrate, a control gate electrode, and a second gate formed between the two gate electrodes. an insulating film; a first gate insulating film formed between the semiconductor substrate and the floating gate electrode;
A first semiconductor region of a second conductivity type provided on the side of the surface of the semiconductor substrate to which the data lines of the floating gate electrode and the control gate electrode connect, and a first semiconductor region of the second conductivity type provided on the side of the surface to which the ground line connects. A semiconductor memory device having a memory cell including a MISFET configured with a second semiconductor region of a second conductivity type, wherein the MISFET is arranged at an intersection of each data line and a word line, and the second semiconductor region is connected to a ground line extending in the same direction as the word line, a control gate electrode is connected to the word line, the first semiconductor region is connected to the data line, and the impurity concentration is the same as that of the second semiconductor region. lower than the impurity concentration of the region,
The memory cell has a predetermined high potential applied to a second semiconductor region to which the ground line is connected, a predetermined low potential to a first semiconductor region to which the data line is connected, and a predetermined high potential to the control gate electrode. The first semiconductor region connected to the data line is used as a drain, the second semiconductor region connected to the ground line is used as a source, and a predetermined potential is applied to the control electrode. A semiconductor memory device characterized in that information is read by applying a voltage. 2. The semiconductor memory device according to claim 1, wherein the first and second conductivity types are P type and n type. 3. To erase information from the memory cell, apply a predetermined high potential to the first semiconductor region connected to the data line, a predetermined low potential to the second semiconductor region connected to the ground line, and apply a predetermined low potential to the control gate electrode. 2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is operated by respectively applying a predetermined low potential. 4. The semiconductor memory device according to claim 1, wherein information in the memory cell is erased by irradiating ultraviolet rays. 5. The semiconductor memory device according to claim 1, wherein the first semiconductor region is formed to cover a third semiconductor region formed in the same process as the second semiconductor region. 6. The second semiconductor region and the third semiconductor region consist of a fourth semiconductor region and a fifth semiconductor region, the fourth semiconductor region is formed between the channel region and the fifth semiconductor region, and the fourth semiconductor region 6. The semiconductor memory device according to claim 5, wherein the semiconductor memory device is formed shallower than the region. 7. The fourth semiconductor region has a junction depth of approximately 0.1 to 0.2 μm at the end on the channel region side, and the fifth semiconductor region is a portion other than the fourth semiconductor region, and the junction depth thereof is approximately 0.1 to 0.2 μm. is 0
．． 7. The semiconductor memory device according to claim 6, wherein the thickness is about 2 to 0.3 μm. 8. The first semiconductor region has a junction depth of 0.4 to 0.6.
2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is formed to have a thickness of approximately μm. 9. The first semiconductor region to which the data line is connected has a junction depth of 0.2 and is spaced apart so as not to go under the floating gate electrode and the control gate electrode.
The second semiconductor region is formed to cover the fifth semiconductor region with a thickness of approximately 0.3 μm and is connected to the fourth semiconductor region at the end on the channel region side, and the fourth semiconductor region at the end on the channel region side. 2. The semiconductor memory device according to claim 1, further comprising a fifth semiconductor region. 10. The first semiconductor region connecting the data line of the MISFET has a junction depth of about 0.4 to 0.6 μm, and a fifth semiconductor region with a junction depth of about 0.3 μm is formed on this surface.
2. The semiconductor memory device according to claim 1, wherein the second semiconductor region having the semiconductor region and connecting the ground line has a junction depth of about 0.3 μm. 11. The first semiconductor region that connects the data line of the MISFET has a deep junction depth of about 0.4 to 0.6 μm, and the second semiconductor region that connects the ground line has a junction depth at the end on the channel side. The fourth junction has a shallow junction of about 0.1 to 0.2 μm.
0.0, which forms the semiconductor region and a portion spaced apart from the channel.
2. The semiconductor memory device according to claim 1, further comprising a fifth semiconductor region having a junction of about 2 to 0.3 μm. 12. Erasing the information in the memory cell involves applying a predetermined potential to the first semiconductor region to which the data is connected to draw out the information charge stored in the floating gate electrode, and then electrically discharging the second region. 2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is operated in a floating state. 13. Erasing the information in the memory cell applies substantially the same predetermined potential to both the first semiconductor region and the second semiconductor region to erase the information charges stored in the floating gate electrode. 2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is formed by drawing out the semiconductor memory into the first and second semiconductor regions. 14. A semiconductor substrate of a first conductivity type, a floating gate electrode provided over the substrate, a control gate electrode, a second gate insulating film formed between the two gate electrodes, and the semiconductor substrate. a first gate insulating film formed between the substrate and the floating gate electrode; and a second conductive film provided on the side of the surface of the semiconductor substrate where the data lines of the floating gate electrode and the control gate electrode are connected. A semiconductor memory device having a memory cell consisting of a MISFET configured of a first semiconductor region of a type and a second semiconductor region of a second conductivity type provided on a side to which a ground line is connected, the MISFET comprising: , arranged at the intersection of each data line and word line, the first semiconductor region is connected to the data line, and the second semiconductor region is connected to a ground line extending in the same direction as the word line; A sixth semiconductor region of a first conductivity type is formed at an end of the second semiconductor region on the channel side; in this, the memory cell is connected to a predetermined region of the second semiconductor region to which the ground line is connected. Information is written by applying a high potential to a first semiconductor region to which the data line is connected, a predetermined low potential to the first semiconductor region to which the data line is connected, and a predetermined high potential to the control gate electrode. A semiconductor memory device characterized in that a first semiconductor region connected to the ground line is used as a drain, a second semiconductor region connected to the ground line is used as a source, and information is read by applying a predetermined potential to the control electrode. . 15. The semiconductor memory device according to claim 14, wherein the first and second conductivity types are p-type and n-type. 16. The semiconductor memory device according to claim 14, wherein the sixth semiconductor region is a p^+ type semiconductor region. 17. Information in the memory cell is erased by applying a predetermined high potential to the first semiconductor region to which the data line is connected, a predetermined low potential to the second semiconductor region to which the ground line is connected, and a control gate electrode. 15. The semiconductor memory device according to claim 14, wherein the semiconductor memory device is operated by applying a predetermined low potential to each of the semiconductor memory devices. 18. The semiconductor memory device according to claim 14, wherein information in the memory cell is erased by irradiating ultraviolet light. 19. The semiconductor memory device according to claim 14, wherein the first semiconductor region is formed to cover a third semiconductor region consisting of fourth and fifth semiconductor regions. 20. The semiconductor memory device according to claim 14, wherein the first semiconductor region has a deep junction of about 0.4 to 0.6 μm, and the second semiconductor region has a deep junction of about 0.3 μm. 21. Each of the third semiconductor region and the second semiconductor region consists of a fourth semiconductor region with a shallow junction of about 0.1 to 0.2 μm at the end on the channel side, and the portion other than the fourth semiconductor region is The fifth layer has a bond of about 0.2 to 0.3 μm.
20. The semiconductor memory device according to claim 19, comprising a semiconductor region. 22. The semiconductor memory device according to claim 14, wherein the sixth semiconductor region is formed only in a channel region in contact with the second semiconductor region. 23. A semiconductor substrate of a first conductivity type, a floating gate electrode provided over the substrate, a control gate electrode, a second gate insulating film formed between the two gate electrodes, and the semiconductor substrate. a first gate insulating film formed between the substrate and the floating gate electrode; and a second conductive film provided on the side of the surface of the semiconductor substrate where the data lines of the floating gate electrode and the control gate electrode are connected. A semiconductor memory device having a memory cell consisting of a MISFET configured of a first semiconductor region of a type and a second semiconductor region of a second conductivity type provided on a side to which a ground line is connected, the MISFET comprising: , disposed at the intersection of each data line and word line, the first semiconductor region being connected to the data line, and the second semiconductor region being connected to a ground line extending in the same direction as the word line;
A control gate electrode is a semiconductor memory device connected to a word line, the impurity concentration of the first semiconductor region is lower than that of the second semiconductor region, and the control gate electrode is connected to the channel side end of the second semiconductor region. A sixth semiconductor region having a conductivity type opposite to that of the second semiconductor region is provided. In this case, the memory cell has a predetermined high potential in a second semiconductor region connected to the ground line, a predetermined low potential in a first semiconductor region connected to the data line, and a predetermined potential in the control gate electrode. Information is written by applying a high potential of Information is read by applying a predetermined potential, and information is erased by applying a predetermined high potential to the first semiconductor region to which the data line is connected, and to the second semiconductor region to which the ground line is connected. 1. A semiconductor memory device characterized in that a predetermined low potential is applied to a control electrode and a predetermined low potential is applied to a control electrode. 24. The semiconductor memory device according to claim 23, wherein the first and second conductivity types are p-type and n-type. 25, the first semiconductor region has the second semiconductor region within the region;
24. The semiconductor memory device according to claim 23, further comprising a third semiconductor region formed in the same process as the semiconductor region. 26. The second semiconductor region and the third semiconductor region include a fourth semiconductor region having a shallow junction depth of about 0.1 to 0.2 μm at the end on the channel region side, and a fourth semiconductor region having a shallow junction depth of about 0.1 to 0.2 μm in the other portions.
It is characterized by comprising a fifth semiconductor region having a junction depth of about 2 to 0.3 μm, and the fourth and fifth semiconductor regions constituting the second semiconductor region have their peripheries and bottoms 26. The semiconductor memory device according to claim 23, wherein the semiconductor memory device is surrounded by a sixth semiconductor region. 27. In the first semiconductor region to which the data line is connected, only the fifth semiconductor region with a junction depth of about 0.2 to 0.3 μm is formed so as not to go under the floating gate electrode and the control gate electrode. The second semiconductor region, which is provided at a distance from the ground line and connected to the ground line, is composed of a fourth semiconductor region at an end on the channel region side and a fifth semiconductor region at a portion away from the channel. A semiconductor memory device according to claim 23. 28. The first semiconductor region to which the data line of the MISFET is connected has a deep junction depth of about 0.4 to 0.6 μm;
A fifth semiconductor region having a thickness of about 0.3 μm is provided therein, while a second semiconductor region to which the ground line is connected has a junction depth of about 0.3 μm. 23. The semiconductor memory device according to item 23. 29. The first semiconductor region to which the data line of the MISFET is connected has a deep junction depth of about 0.4 to 0.6 μm, and there is no other semiconductor region in this region, and the ground line is connected to the first semiconductor region. The second semiconductor region has an end portion on the channel side of 0.1 to
A fourth semiconductor region having a shallow junction of about 0.2 μm and a fifth semiconductor region having a junction of about 0.2 to 0.3 μm forming a part separated from the channel. The semiconductor memory device according to scope 23.